xref: /freebsd/sys/dev/mlx5/mlx5_en/en.h (revision 895f86f15fbf6540071feb9328c3c50ed1f027b8)
1 /*-
2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef _MLX5_EN_H_
29 #define	_MLX5_EN_H_
30 
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
52 
53 #include <machine/bus.h>
54 
55 #ifdef HAVE_TURBO_LRO
56 #include "tcp_tlro.h"
57 #endif
58 
59 #include <dev/mlx5/driver.h>
60 #include <dev/mlx5/qp.h>
61 #include <dev/mlx5/cq.h>
62 #include <dev/mlx5/vport.h>
63 
64 #include <dev/mlx5/mlx5_core/wq.h>
65 #include <dev/mlx5/mlx5_core/transobj.h>
66 #include <dev/mlx5/mlx5_core/mlx5_core.h>
67 
68 #define	MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x7
69 #define	MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
70 #define	MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
71 
72 #define	MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x7
73 #define	MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
74 #define	MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
75 
76 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */
77 #define	MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 MJUM16BYTES
78 #define	MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
79 #define	MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE	0x3
80 #define	MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
81 #define	MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
82 #define	MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
83 #define	MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
84 #define	MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ         0x7
85 #define	MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
86 #define	MLX5E_HW2SW_MTU(hwmtu) \
87     ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
88 #define	MLX5E_SW2HW_MTU(swmtu) \
89     ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
90 #define	MLX5E_SW2MB_MTU(swmtu) \
91     (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
92 #define	MLX5E_MTU_MIN		72	/* Min MTU allowed by the kernel */
93 #define	MLX5E_MTU_MAX		MIN(ETHERMTU_JUMBO, MJUM16BYTES)	/* Max MTU of Ethernet
94 									 * jumbo frames */
95 
96 #define	MLX5E_BUDGET_MAX	8192	/* RX and TX */
97 #define	MLX5E_RX_BUDGET_MAX	256
98 #define	MLX5E_SQ_BF_BUDGET	16
99 #define	MLX5E_SQ_TX_QUEUE_SIZE	4096	/* SQ drbr queue size */
100 
101 #define	MLX5E_MAX_TX_NUM_TC	8	/* units */
102 #define	MLX5E_MAX_TX_HEADER	128	/* bytes */
103 #define	MLX5E_MAX_TX_PAYLOAD_SIZE	65536	/* bytes */
104 #define	MLX5E_MAX_TX_MBUF_SIZE	65536	/* bytes */
105 #define	MLX5E_MAX_TX_MBUF_FRAGS	\
106     ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
107     (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS))	/* units */
108 #define	MLX5E_MAX_TX_INLINE \
109   (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
110   sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start))	/* bytes */
111 
112 MALLOC_DECLARE(M_MLX5EN);
113 
114 struct mlx5_core_dev;
115 struct mlx5e_cq;
116 
117 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
118 
119 #define	MLX5E_STATS_COUNT(a,b,c,d) a
120 #define	MLX5E_STATS_VAR(a,b,c,d) b;
121 #define	MLX5E_STATS_DESC(a,b,c,d) c, d,
122 
123 #define	MLX5E_VPORT_STATS(m)						\
124   /* HW counters */							\
125   m(+1, u64 rx_packets, "rx_packets", "Received packets")		\
126   m(+1, u64 rx_bytes, "rx_bytes", "Received bytes")			\
127   m(+1, u64 tx_packets, "tx_packets", "Transmitted packets")		\
128   m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes")			\
129   m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
130   m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes")	\
131   m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
132   m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
133   m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
134   m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
135   m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
136   m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
137   m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
138   m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
139   m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
140   m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
141   m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
142   m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
143   m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
144   m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
145   m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
146   /* SW counters */							\
147   m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets")	\
148   m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes")		\
149   m(+1, u64 lro_packets, "lro_packets", "Received LRO packets")		\
150   m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes")		\
151   m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO")	\
152   m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO")	\
153   m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
154   m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
155   m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
156   m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
157   m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
158   m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors")
159 
160 #define	MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
161 
162 struct mlx5e_vport_stats {
163 	struct	sysctl_ctx_list ctx;
164 	u64	arg [0];
165 	MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
166 	u32	rx_out_of_buffer_prev;
167 };
168 
169 #define	MLX5E_PPORT_IEEE802_3_STATS(m)					\
170   m(+1, u64 frames_tx, "frames_tx", "Frames transmitted")		\
171   m(+1, u64 frames_rx, "frames_rx", "Frames received")			\
172   m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors")		\
173   m(+1, u64 alignment_err, "alignment_err", "Alignment errors")	\
174   m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted")		\
175   m(+1, u64 octets_received, "octets_received", "Bytes received")	\
176   m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
177   m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
178   m(+1, u64 multicast_rx, "multicast_rx", "Multicast received")	\
179   m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received")	\
180   m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
181   m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
182   m(+1, u64 too_long_errors, "too_long_errors", "Too long errors")	\
183   m(+1, u64 symbol_err, "symbol_err", "Symbol errors")			\
184   m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
185   m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received")	\
186   m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
187   m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received")	\
188   m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
189 
190 #define	MLX5E_PPORT_RFC2819_STATS(m)					\
191   m(+1, u64 drop_events, "drop_events", "Dropped events")		\
192   m(+1, u64 octets, "octets", "Octets")					\
193   m(+1, u64 pkts, "pkts", "Packets")					\
194   m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets")	\
195   m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets")	\
196   m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
197   m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets")	\
198   m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets")	\
199   m(+1, u64 fragments, "fragments", "Fragments")			\
200   m(+1, u64 jabbers, "jabbers", "Jabbers")				\
201   m(+1, u64 collisions, "collisions", "Collisions")
202 
203 #define	MLX5E_PPORT_RFC2819_STATS_DEBUG(m)				\
204   m(+1, u64 p64octets, "p64octets", "Bytes")				\
205   m(+1, u64 p65to127octets, "p65to127octets", "Bytes")			\
206   m(+1, u64 p128to255octets, "p128to255octets", "Bytes")		\
207   m(+1, u64 p256to511octets, "p256to511octets", "Bytes")		\
208   m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes")		\
209   m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes")		\
210   m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes")		\
211   m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes")		\
212   m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes")		\
213   m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
214 
215 #define	MLX5E_PPORT_RFC2863_STATS_DEBUG(m)				\
216   m(+1, u64 in_octets, "in_octets", "In octets")			\
217   m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets")	\
218   m(+1, u64 in_discards, "in_discards", "In discards")			\
219   m(+1, u64 in_errors, "in_errors", "In errors")			\
220   m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
221   m(+1, u64 out_octets, "out_octets", "Out octets")			\
222   m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets")	\
223   m(+1, u64 out_discards, "out_discards", "Out discards")		\
224   m(+1, u64 out_errors, "out_errors", "Out errors")			\
225   m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
226   m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
227   m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
228   m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
229 
230 #define	MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)                                    		\
231   m(+1, u64 time_since_last_clear, "time_since_last_clear",				\
232 			"Time since the last counters clear event (msec)")		\
233   m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors")				\
234   m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter")	\
235   m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0",					\
236 			"Indicates the number of PRBS errors on lane 0")		\
237   m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1",					\
238 			"Indicates the number of PRBS errors on lane 1")		\
239   m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2",					\
240 			"Indicates the number of PRBS errors on lane 2")		\
241   m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3",					\
242 			"Indicates the number of PRBS errors on lane 3")		\
243   m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0",			\
244 			"FEC correctable block counter lane 0")				\
245   m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1",			\
246 			"FEC correctable block counter lane 1")				\
247   m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2",			\
248 			"FEC correctable block counter lane 2")				\
249   m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3",			\
250 			"FEC correctable block counter lane 3")				\
251   m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks",					\
252 			"FEC correcable block counter")					\
253   m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks",				\
254 			"FEC uncorrecable block counter")				\
255   m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks",					\
256 			"The number of RS-FEC blocks received that had no errors")	\
257   m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks",				\
258 			"The number of corrected RS-FEC blocks received that had"	\
259 			"exactly 1 error symbol")					\
260   m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total",			\
261 			"Port FEC corrected symbol counter")				\
262   m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0",			\
263 			"FEC corrected symbol counter lane 0")				\
264   m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1",			\
265 			"FEC corrected symbol counter lane 1")				\
266   m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2",			\
267 			"FEC corrected symbol counter lane 2")				\
268   m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3",			\
269 			"FEC corrected symbol counter lane 3")				\
270 
271 /*
272  * Make sure to update mlx5e_update_pport_counters()
273  * when adding a new MLX5E_PPORT_STATS block
274  */
275 #define	MLX5E_PPORT_STATS(m)			\
276   MLX5E_PPORT_IEEE802_3_STATS(m)		\
277   MLX5E_PPORT_RFC2819_STATS(m)
278 
279 #define	MLX5E_PORT_STATS_DEBUG(m)		\
280   MLX5E_PPORT_RFC2819_STATS_DEBUG(m)		\
281   MLX5E_PPORT_RFC2863_STATS_DEBUG(m)		\
282   MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
283 
284 #define	MLX5E_PPORT_IEEE802_3_STATS_NUM \
285   (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
286 #define	MLX5E_PPORT_RFC2819_STATS_NUM \
287   (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
288 #define	MLX5E_PPORT_STATS_NUM \
289   (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
290 
291 #define	MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
292   (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
293 #define	MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
294   (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
295 #define	MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
296   (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
297 #define	MLX5E_PORT_STATS_DEBUG_NUM \
298   (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
299 
300 struct mlx5e_pport_stats {
301 	struct	sysctl_ctx_list ctx;
302 	u64	arg [0];
303 	MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
304 };
305 
306 struct mlx5e_port_stats_debug {
307 	struct	sysctl_ctx_list ctx;
308 	u64	arg [0];
309 	MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
310 };
311 
312 #define	MLX5E_RQ_STATS(m)					\
313   m(+1, u64 packets, "packets", "Received packets")		\
314   m(+1, u64 csum_none, "csum_none", "Received packets")		\
315   m(+1, u64 lro_packets, "lro_packets", "Received packets")	\
316   m(+1, u64 lro_bytes, "lro_bytes", "Received packets")		\
317   m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO")	\
318   m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO")	\
319   m(+1, u64 wqe_err, "wqe_err", "Received packets")
320 
321 #define	MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
322 
323 struct mlx5e_rq_stats {
324 	struct	sysctl_ctx_list ctx;
325 	u64	arg [0];
326 	MLX5E_RQ_STATS(MLX5E_STATS_VAR)
327 };
328 
329 #define	MLX5E_SQ_STATS(m)						\
330   m(+1, u64 packets, "packets", "Transmitted packets")			\
331   m(+1, u64 tso_packets, "tso_packets", "Transmitted packets")		\
332   m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes")		\
333   m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets")	\
334   m(+1, u64 defragged, "defragged", "Transmitted packets")		\
335   m(+1, u64 dropped, "dropped", "Transmitted packets")			\
336   m(+1, u64 nop, "nop", "Transmitted packets")
337 
338 #define	MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
339 
340 struct mlx5e_sq_stats {
341 	struct	sysctl_ctx_list ctx;
342 	u64	arg [0];
343 	MLX5E_SQ_STATS(MLX5E_STATS_VAR)
344 };
345 
346 struct mlx5e_stats {
347 	struct mlx5e_vport_stats vport;
348 	struct mlx5e_pport_stats pport;
349 	struct mlx5e_port_stats_debug port_stats_debug;
350 };
351 
352 struct mlx5e_params {
353 	u8	log_sq_size;
354 	u8	log_rq_size;
355 	u16	num_channels;
356 	u8	default_vlan_prio;
357 	u8	num_tc;
358 	u8	rx_cq_moderation_mode;
359 	u16	rx_cq_moderation_usec;
360 	u16	rx_cq_moderation_pkts;
361 	u16	tx_cq_moderation_usec;
362 	u16	tx_cq_moderation_pkts;
363 	u16	min_rx_wqes;
364 	bool	hw_lro_en;
365 	u32	lro_wqe_sz;
366 	u16	rx_hash_log_tbl_sz;
367 };
368 
369 #define	MLX5E_PARAMS(m)							\
370   m(+1, u64 tx_pauseframe_control, "tx_pauseframe_control", "Set to enable TX pause frames. Clear to disable.") \
371   m(+1, u64 rx_pauseframe_control, "rx_pauseframe_control", "Set to enable RX pause frames. Clear to disable.") \
372   m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
373   m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
374   m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size")	\
375   m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
376   m(+1, u64 channels, "channels", "Default number of channels")		\
377   m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
378   m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
379   m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
380   m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
381   m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
382   m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
383   m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
384   m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro")
385 
386 #define	MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
387 
388 struct mlx5e_params_ethtool {
389 	u64	arg [0];
390 	MLX5E_PARAMS(MLX5E_STATS_VAR)
391 };
392 
393 /* EEPROM Standards for plug in modules */
394 #ifndef MLX5E_ETH_MODULE_SFF_8472
395 #define	MLX5E_ETH_MODULE_SFF_8472	0x1
396 #define	MLX5E_ETH_MODULE_SFF_8472_LEN	128
397 #endif
398 
399 #ifndef MLX5E_ETH_MODULE_SFF_8636
400 #define	MLX5E_ETH_MODULE_SFF_8636	0x2
401 #define	MLX5E_ETH_MODULE_SFF_8636_LEN	256
402 #endif
403 
404 #ifndef MLX5E_ETH_MODULE_SFF_8436
405 #define	MLX5E_ETH_MODULE_SFF_8436	0x3
406 #define	MLX5E_ETH_MODULE_SFF_8436_LEN	256
407 #endif
408 
409 /* EEPROM I2C Addresses */
410 #define	MLX5E_I2C_ADDR_LOW		0x50
411 #define	MLX5E_I2C_ADDR_HIGH		0x51
412 
413 #define	MLX5E_EEPROM_LOW_PAGE		0x0
414 #define	MLX5E_EEPROM_HIGH_PAGE		0x3
415 
416 #define	MLX5E_EEPROM_HIGH_PAGE_OFFSET	128
417 #define	MLX5E_EEPROM_PAGE_LENGTH	256
418 
419 #define	MLX5E_EEPROM_INFO_BYTES		0x3
420 
421 struct mlx5e_cq {
422 	/* data path - accessed per cqe */
423 	struct mlx5_cqwq wq;
424 
425 	/* data path - accessed per HW polling */
426 	struct mlx5_core_cq mcq;
427 	struct mlx5e_channel *channel;
428 
429 	/* control */
430 	struct mlx5_wq_ctrl wq_ctrl;
431 } __aligned(MLX5E_CACHELINE_SIZE);
432 
433 struct mlx5e_rq_mbuf {
434 	bus_dmamap_t	dma_map;
435 	caddr_t		data;
436 	struct mbuf	*mbuf;
437 };
438 
439 struct mlx5e_rq {
440 	/* data path */
441 	struct mlx5_wq_ll wq;
442 	struct mtx mtx;
443 	bus_dma_tag_t dma_tag;
444 	u32	wqe_sz;
445 	struct mlx5e_rq_mbuf *mbuf;
446 	struct device *pdev;
447 	struct ifnet *ifp;
448 	struct mlx5e_rq_stats stats;
449 	struct mlx5e_cq cq;
450 #ifdef HAVE_TURBO_LRO
451 	struct tlro_ctrl lro;
452 #else
453 	struct lro_ctrl lro;
454 #endif
455 	volatile int enabled;
456 	int	ix;
457 
458 	/* control */
459 	struct mlx5_wq_ctrl wq_ctrl;
460 	u32	rqn;
461 	struct mlx5e_channel *channel;
462 } __aligned(MLX5E_CACHELINE_SIZE);
463 
464 struct mlx5e_sq_mbuf {
465 	bus_dmamap_t dma_map;
466 	struct mbuf *mbuf;
467 	u32	num_bytes;
468 	u32	num_wqebbs;
469 };
470 
471 enum {
472 	MLX5E_SQ_READY,
473 	MLX5E_SQ_FULL
474 };
475 
476 struct mlx5e_sq {
477 	/* data path */
478 	struct	mtx lock;
479 	bus_dma_tag_t dma_tag;
480 	struct	mtx comp_lock;
481 
482 	/* dirtied @completion */
483 	u16	cc;
484 
485 	/* dirtied @xmit */
486 	u16	pc __aligned(MLX5E_CACHELINE_SIZE);
487 	u16	bf_offset;
488 	struct	mlx5e_sq_stats stats;
489 
490 	struct	mlx5e_cq cq;
491 	struct	task sq_task;
492 	struct	taskqueue *sq_tq;
493 
494 	/* pointers to per packet info: write@xmit, read@completion */
495 	struct	mlx5e_sq_mbuf *mbuf;
496 	struct	buf_ring *br;
497 
498 	/* read only */
499 	struct	mlx5_wq_cyc wq;
500 	void	__iomem *uar_map;
501 	void	__iomem *uar_bf_map;
502 	u32	sqn;
503 	u32	bf_buf_size;
504 	struct  device *pdev;
505 	u32	mkey_be;
506 
507 	/* control path */
508 	struct	mlx5_wq_ctrl wq_ctrl;
509 	struct	mlx5_uar uar;
510 	struct	mlx5e_channel *channel;
511 	int	tc;
512 	unsigned int queue_state;
513 } __aligned(MLX5E_CACHELINE_SIZE);
514 
515 static inline bool
516 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
517 {
518 	return ((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n ||
519 	    sq->cc == sq->pc);
520 }
521 
522 struct mlx5e_channel {
523 	/* data path */
524 	struct mlx5e_rq rq;
525 	struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
526 	struct device *pdev;
527 	struct ifnet *ifp;
528 	u32	mkey_be;
529 	u8	num_tc;
530 
531 	/* control */
532 	struct mlx5e_priv *priv;
533 	int	ix;
534 	int	cpu;
535 } __aligned(MLX5E_CACHELINE_SIZE);
536 
537 enum mlx5e_traffic_types {
538 	MLX5E_TT_IPV4_TCP,
539 	MLX5E_TT_IPV6_TCP,
540 	MLX5E_TT_IPV4_UDP,
541 	MLX5E_TT_IPV6_UDP,
542 	MLX5E_TT_IPV4_IPSEC_AH,
543 	MLX5E_TT_IPV6_IPSEC_AH,
544 	MLX5E_TT_IPV4_IPSEC_ESP,
545 	MLX5E_TT_IPV6_IPSEC_ESP,
546 	MLX5E_TT_IPV4,
547 	MLX5E_TT_IPV6,
548 	MLX5E_TT_ANY,
549 	MLX5E_NUM_TT,
550 };
551 
552 enum {
553 	MLX5E_RQT_SPREADING = 0,
554 	MLX5E_RQT_DEFAULT_RQ = 1,
555 	MLX5E_NUM_RQT = 2,
556 };
557 
558 struct mlx5e_eth_addr_info {
559 	u8	addr [ETH_ALEN + 2];
560 	u32	tt_vec;
561 	u32	ft_ix[MLX5E_NUM_TT];	/* flow table index per traffic type */
562 };
563 
564 #define	MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
565 
566 struct mlx5e_eth_addr_hash_node;
567 
568 struct mlx5e_eth_addr_hash_head {
569 	struct mlx5e_eth_addr_hash_node *lh_first;
570 };
571 
572 struct mlx5e_eth_addr_db {
573 	struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
574 	struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
575 	struct mlx5e_eth_addr_info broadcast;
576 	struct mlx5e_eth_addr_info allmulti;
577 	struct mlx5e_eth_addr_info promisc;
578 	bool	broadcast_enabled;
579 	bool	allmulti_enabled;
580 	bool	promisc_enabled;
581 };
582 
583 enum {
584 	MLX5E_STATE_ASYNC_EVENTS_ENABLE,
585 	MLX5E_STATE_OPENED,
586 };
587 
588 struct mlx5e_vlan_db {
589 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
590 	u32	active_vlans_ft_ix[VLAN_N_VID];
591 	u32	untagged_rule_ft_ix;
592 	u32	any_vlan_rule_ft_ix;
593 	bool	filter_disabled;
594 };
595 
596 struct mlx5e_flow_table {
597 	void   *vlan;
598 	void   *main;
599 };
600 
601 struct mlx5e_priv {
602 	/* priv data path fields - start */
603 	int	order_base_2_num_channels;
604 	int	queue_mapping_channel_mask;
605 	int	num_tc;
606 	int	default_vlan_prio;
607 	/* priv data path fields - end */
608 
609 	unsigned long state;
610 	int	gone;
611 #define	PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
612 #define	PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
613 #define	PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
614 	struct sx state_lock;		/* Protects Interface state */
615 	struct mlx5_uar cq_uar;
616 	u32	pdn;
617 	u32	tdn;
618 	struct mlx5_core_mr mr;
619 
620 	struct mlx5e_channel *volatile *channel;
621 	u32	tisn[MLX5E_MAX_TX_NUM_TC];
622 	u32	rqtn;
623 	u32	tirn[MLX5E_NUM_TT];
624 
625 	struct mlx5e_flow_table ft;
626 	struct mlx5e_eth_addr_db eth_addr;
627 	struct mlx5e_vlan_db vlan;
628 
629 	struct mlx5e_params params;
630 	struct mlx5e_params_ethtool params_ethtool;
631 	struct mtx async_events_mtx;	/* sync hw events */
632 	struct work_struct update_stats_work;
633 	struct work_struct update_carrier_work;
634 	struct work_struct set_rx_mode_work;
635 
636 	struct mlx5_core_dev *mdev;
637 	struct ifnet *ifp;
638 	struct sysctl_ctx_list sysctl_ctx;
639 	struct sysctl_oid *sysctl_ifnet;
640 	struct sysctl_oid *sysctl_hw;
641 	int	sysctl_debug;
642 	struct mlx5e_stats stats;
643 	int	counter_set_id;
644 
645 	eventhandler_tag vlan_detach;
646 	eventhandler_tag vlan_attach;
647 	struct ifmedia media;
648 	int	media_status_last;
649 	int	media_active_last;
650 
651 	struct callout watchdog;
652 };
653 
654 #define	MLX5E_NET_IP_ALIGN 2
655 
656 struct mlx5e_tx_wqe {
657 	struct mlx5_wqe_ctrl_seg ctrl;
658 	struct mlx5_wqe_eth_seg eth;
659 };
660 
661 struct mlx5e_rx_wqe {
662 	struct mlx5_wqe_srq_next_seg next;
663 	struct mlx5_wqe_data_seg data;
664 };
665 
666 struct mlx5e_eeprom {
667 	int	lock_bit;
668 	int	i2c_addr;
669 	int	page_num;
670 	int	device_addr;
671 	int	module_num;
672 	int	len;
673 	int	type;
674 	int	page_valid;
675 	u32	*data;
676 };
677 
678 enum mlx5e_link_mode {
679 	MLX5E_1000BASE_CX_SGMII = 0,
680 	MLX5E_1000BASE_KX = 1,
681 	MLX5E_10GBASE_CX4 = 2,
682 	MLX5E_10GBASE_KX4 = 3,
683 	MLX5E_10GBASE_KR = 4,
684 	MLX5E_20GBASE_KR2 = 5,
685 	MLX5E_40GBASE_CR4 = 6,
686 	MLX5E_40GBASE_KR4 = 7,
687 	MLX5E_56GBASE_R4 = 8,
688 	MLX5E_10GBASE_CR = 12,
689 	MLX5E_10GBASE_SR = 13,
690 	MLX5E_10GBASE_ER = 14,
691 	MLX5E_40GBASE_SR4 = 15,
692 	MLX5E_40GBASE_LR4 = 16,
693 	MLX5E_100GBASE_CR4 = 20,
694 	MLX5E_100GBASE_SR4 = 21,
695 	MLX5E_100GBASE_KR4 = 22,
696 	MLX5E_100GBASE_LR4 = 23,
697 	MLX5E_100BASE_TX = 24,
698 	MLX5E_100BASE_T = 25,
699 	MLX5E_10GBASE_T = 26,
700 	MLX5E_25GBASE_CR = 27,
701 	MLX5E_25GBASE_KR = 28,
702 	MLX5E_25GBASE_SR = 29,
703 	MLX5E_50GBASE_CR2 = 30,
704 	MLX5E_50GBASE_KR2 = 31,
705 	MLX5E_LINK_MODES_NUMBER,
706 };
707 
708 #define	MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
709 #define	MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
710 
711 int	mlx5e_xmit(struct ifnet *, struct mbuf *);
712 
713 int	mlx5e_open_locked(struct ifnet *);
714 int	mlx5e_close_locked(struct ifnet *);
715 
716 void	mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
717 void	mlx5e_rx_cq_comp(struct mlx5_core_cq *);
718 void	mlx5e_tx_cq_comp(struct mlx5_core_cq *);
719 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
720 void	mlx5e_tx_que(void *context, int pending);
721 
722 int	mlx5e_open_flow_table(struct mlx5e_priv *priv);
723 void	mlx5e_close_flow_table(struct mlx5e_priv *priv);
724 void	mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
725 void	mlx5e_set_rx_mode_work(struct work_struct *work);
726 
727 void	mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
728 void	mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
729 void	mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
730 void	mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
731 int	mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
732 void	mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
733 
734 static inline void
735 mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
736     struct mlx5e_tx_wqe *wqe, int bf_sz)
737 {
738 	u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
739 
740 	/* ensure wqe is visible to device before updating doorbell record */
741 	wmb();
742 
743 	*sq->wq.db = cpu_to_be32(sq->pc);
744 
745 	/*
746 	 * Ensure the doorbell record is visible to device before ringing
747 	 * the doorbell:
748 	 */
749 	wmb();
750 
751 	if (bf_sz) {
752 		__iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);
753 
754 		/* flush the write-combining mapped buffer */
755 		wmb();
756 
757 	} else {
758 		mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
759 	}
760 
761 	sq->bf_offset ^= sq->bf_buf_size;
762 }
763 
764 static inline void
765 mlx5e_cq_arm(struct mlx5e_cq *cq)
766 {
767 	struct mlx5_core_cq *mcq;
768 
769 	mcq = &cq->mcq;
770 	mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
771 }
772 
773 extern const struct ethtool_ops mlx5e_ethtool_ops;
774 void	mlx5e_create_ethtool(struct mlx5e_priv *);
775 void	mlx5e_create_stats(struct sysctl_ctx_list *,
776     struct sysctl_oid_list *, const char *,
777     const char **, unsigned, u64 *);
778 void	mlx5e_send_nop(struct mlx5e_sq *, u32, bool);
779 
780 #endif					/* _MLX5_EN_H_ */
781