1 /*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _MLX5_EN_H_ 29 #define _MLX5_EN_H_ 30 31 #include <linux/kmod.h> 32 #include <linux/page.h> 33 #include <linux/slab.h> 34 #include <linux/if_vlan.h> 35 #include <linux/if_ether.h> 36 #include <linux/vmalloc.h> 37 #include <linux/moduleparam.h> 38 #include <linux/delay.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 42 #include <netinet/in_systm.h> 43 #include <netinet/in.h> 44 #include <netinet/if_ether.h> 45 #include <netinet/ip.h> 46 #include <netinet/ip6.h> 47 #include <netinet/tcp.h> 48 #include <netinet/tcp_lro.h> 49 #include <netinet/udp.h> 50 #include <net/ethernet.h> 51 #include <net/pfil.h> 52 #include <sys/buf_ring.h> 53 #include <sys/kthread.h> 54 55 #include "opt_rss.h" 56 57 #ifdef RSS 58 #include <net/rss_config.h> 59 #include <netinet/in_rss.h> 60 #endif 61 62 #include <machine/bus.h> 63 64 #include <dev/mlx5/driver.h> 65 #include <dev/mlx5/qp.h> 66 #include <dev/mlx5/cq.h> 67 #include <dev/mlx5/port.h> 68 #include <dev/mlx5/vport.h> 69 #include <dev/mlx5/diagnostics.h> 70 71 #include <dev/mlx5/mlx5_core/wq.h> 72 #include <dev/mlx5/mlx5_core/transobj.h> 73 #include <dev/mlx5/mlx5_core/mlx5_core.h> 74 75 #define IEEE_8021QAZ_MAX_TCS 8 76 77 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 78 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 79 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 80 81 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 82 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 83 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 84 85 #define MLX5E_MAX_RX_SEGS 7 86 87 #ifndef MLX5E_MAX_RX_BYTES 88 #define MLX5E_MAX_RX_BYTES MCLBYTES 89 #endif 90 91 #if (MLX5E_MAX_RX_SEGS == 1) 92 /* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 93 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 94 #else 95 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 96 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 97 #endif 98 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 101 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 102 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 103 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 104 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 105 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 106 #define MLX5E_HW2SW_MTU(hwmtu) \ 107 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 108 #define MLX5E_SW2HW_MTU(swmtu) \ 109 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 110 #define MLX5E_SW2MB_MTU(swmtu) \ 111 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 112 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 113 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 114 * jumbo frames */ 115 116 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 117 #define MLX5E_RX_BUDGET_MAX 256 118 #define MLX5E_SQ_BF_BUDGET 16 119 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 120 121 #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 122 #define MLX5E_MAX_TX_HEADER 128 /* bytes */ 123 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 124 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 125 #define MLX5E_MAX_TX_MBUF_FRAGS \ 126 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 127 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 128 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 129 #define MLX5E_MAX_TX_INLINE \ 130 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 131 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 132 133 #define MLX5E_100MB (100000) 134 #define MLX5E_1GB (1000000) 135 136 MALLOC_DECLARE(M_MLX5EN); 137 138 struct mlx5_core_dev; 139 struct mlx5e_cq; 140 141 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 142 143 #define MLX5E_STATS_COUNT(a,b,c,d) a 144 #define MLX5E_STATS_VAR(a,b,c,d) b; 145 #define MLX5E_STATS_DESC(a,b,c,d) c, d, 146 147 #define MLX5E_VPORT_STATS(m) \ 148 /* HW counters */ \ 149 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 150 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 151 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 152 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 153 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 154 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 155 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 156 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 157 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 158 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 159 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 160 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 161 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 162 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 163 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 164 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 165 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 166 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 167 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 168 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 169 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 170 /* SW counters */ \ 171 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 172 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 173 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 174 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 175 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 176 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 177 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 178 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 179 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 180 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 181 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 182 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 183 m(+1, u64 tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") 184 185 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 186 187 struct mlx5e_vport_stats { 188 struct sysctl_ctx_list ctx; 189 u64 arg [0]; 190 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 191 u32 rx_out_of_buffer_prev; 192 }; 193 194 #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 195 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 196 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 197 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 198 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 199 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 200 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 201 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 202 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 203 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 204 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 205 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 206 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 207 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 208 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 209 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 210 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 211 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 212 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 213 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 214 215 #define MLX5E_PPORT_RFC2819_STATS(m) \ 216 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 217 m(+1, u64 octets, "octets", "Octets") \ 218 m(+1, u64 pkts, "pkts", "Packets") \ 219 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 220 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 221 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 222 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 223 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 224 m(+1, u64 fragments, "fragments", "Fragments") \ 225 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 226 m(+1, u64 collisions, "collisions", "Collisions") 227 228 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 229 m(+1, u64 p64octets, "p64octets", "Bytes") \ 230 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 231 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 232 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 233 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 234 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 235 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 236 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 237 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 238 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 239 240 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 241 m(+1, u64 in_octets, "in_octets", "In octets") \ 242 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 243 m(+1, u64 in_discards, "in_discards", "In discards") \ 244 m(+1, u64 in_errors, "in_errors", "In errors") \ 245 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 246 m(+1, u64 out_octets, "out_octets", "Out octets") \ 247 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 248 m(+1, u64 out_discards, "out_discards", "Out discards") \ 249 m(+1, u64 out_errors, "out_errors", "Out errors") \ 250 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 251 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 252 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 253 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 254 255 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 256 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 257 "Time since the last counters clear event (msec)") \ 258 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 259 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 260 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 261 "Indicates the number of PRBS errors on lane 0") \ 262 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 263 "Indicates the number of PRBS errors on lane 1") \ 264 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 265 "Indicates the number of PRBS errors on lane 2") \ 266 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 267 "Indicates the number of PRBS errors on lane 3") \ 268 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 269 "FEC correctable block counter lane 0") \ 270 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 271 "FEC correctable block counter lane 1") \ 272 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 273 "FEC correctable block counter lane 2") \ 274 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 275 "FEC correctable block counter lane 3") \ 276 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 277 "FEC correcable block counter") \ 278 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 279 "FEC uncorrecable block counter") \ 280 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 281 "The number of RS-FEC blocks received that had no errors") \ 282 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 283 "The number of corrected RS-FEC blocks received that had" \ 284 "exactly 1 error symbol") \ 285 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 286 "Port FEC corrected symbol counter") \ 287 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 288 "FEC corrected symbol counter lane 0") \ 289 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 290 "FEC corrected symbol counter lane 1") \ 291 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 292 "FEC corrected symbol counter lane 2") \ 293 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 294 "FEC corrected symbol counter lane 3") 295 296 /* Per priority statistics for PFC */ 297 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 298 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 299 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 300 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 301 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 302 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 303 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 304 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 305 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 306 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 307 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 308 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 309 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 310 "Received pause duration") \ 311 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 312 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 313 "Transmitted pause duration") \ 314 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 315 "Received pause transitions") \ 316 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 317 m(n, p, +1, u64, device_stall_minor_watermark, \ 318 "device_stall_minor_watermark", "Device stall minor watermark") \ 319 m(n, p, +1, u64, device_stall_critical_watermark, \ 320 "device_stall_critical_watermark", "Device stall critical watermark") 321 322 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 323 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 324 325 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 326 327 #define MLX5E_PPORT_PER_PRIO_STATS(m) \ 328 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 329 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 330 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 331 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 332 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 333 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 334 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 335 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 336 337 /* 338 * Make sure to update mlx5e_update_pport_counters() 339 * when adding a new MLX5E_PPORT_STATS block 340 */ 341 #define MLX5E_PPORT_STATS(m) \ 342 MLX5E_PPORT_PER_PRIO_STATS(m) \ 343 MLX5E_PPORT_IEEE802_3_STATS(m) \ 344 MLX5E_PPORT_RFC2819_STATS(m) 345 346 #define MLX5E_PORT_STATS_DEBUG(m) \ 347 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 348 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 349 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 350 351 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 352 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 353 #define MLX5E_PPORT_RFC2819_STATS_NUM \ 354 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 355 #define MLX5E_PPORT_STATS_NUM \ 356 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 357 358 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 359 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 360 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 361 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 362 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 363 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 364 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 365 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 366 #define MLX5E_PORT_STATS_DEBUG_NUM \ 367 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 368 369 struct mlx5e_pport_stats { 370 struct sysctl_ctx_list ctx; 371 u64 arg [0]; 372 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 373 }; 374 375 struct mlx5e_port_stats_debug { 376 struct sysctl_ctx_list ctx; 377 u64 arg [0]; 378 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 379 }; 380 381 #define MLX5E_RQ_STATS(m) \ 382 m(+1, u64 packets, "packets", "Received packets") \ 383 m(+1, u64 bytes, "bytes", "Received bytes") \ 384 m(+1, u64 csum_none, "csum_none", "Received packets") \ 385 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 386 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 387 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 388 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 389 m(+1, u64 wqe_err, "wqe_err", "Received packets") 390 391 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 392 393 struct mlx5e_rq_stats { 394 struct sysctl_ctx_list ctx; 395 u64 arg [0]; 396 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 397 }; 398 399 #define MLX5E_SQ_STATS(m) \ 400 m(+1, u64 packets, "packets", "Transmitted packets") \ 401 m(+1, u64 bytes, "bytes", "Transmitted bytes") \ 402 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 403 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 404 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 405 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 406 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 407 m(+1, u64 nop, "nop", "Transmitted packets") 408 409 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 410 411 struct mlx5e_sq_stats { 412 struct sysctl_ctx_list ctx; 413 u64 arg [0]; 414 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 415 }; 416 417 struct mlx5e_stats { 418 struct mlx5e_vport_stats vport; 419 struct mlx5e_pport_stats pport; 420 struct mlx5e_port_stats_debug port_stats_debug; 421 }; 422 423 struct mlx5e_rq_param { 424 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 425 struct mlx5_wq_param wq; 426 }; 427 428 struct mlx5e_sq_param { 429 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 430 struct mlx5_wq_param wq; 431 }; 432 433 struct mlx5e_cq_param { 434 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 435 struct mlx5_wq_param wq; 436 }; 437 438 struct mlx5e_params { 439 u8 log_sq_size; 440 u8 log_rq_size; 441 u16 num_channels; 442 u8 default_vlan_prio; 443 u8 num_tc; 444 u8 rx_cq_moderation_mode; 445 u8 tx_cq_moderation_mode; 446 u16 rx_cq_moderation_usec; 447 u16 rx_cq_moderation_pkts; 448 u16 tx_cq_moderation_usec; 449 u16 tx_cq_moderation_pkts; 450 u16 min_rx_wqes; 451 bool hw_lro_en; 452 bool cqe_zipping_en; 453 u32 lro_wqe_sz; 454 u16 rx_hash_log_tbl_sz; 455 u32 tx_pauseframe_control __aligned(4); 456 u32 rx_pauseframe_control __aligned(4); 457 u32 tx_priority_flow_control __aligned(4); 458 u32 rx_priority_flow_control __aligned(4); 459 u16 tx_max_inline; 460 u8 tx_min_inline_mode; 461 u8 channels_rsss; 462 }; 463 464 #define MLX5E_PARAMS(m) \ 465 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 466 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 467 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 468 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 469 m(+1, u64 channels, "channels", "Default number of channels") \ 470 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 471 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 472 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 473 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 474 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 475 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 476 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 477 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 478 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 479 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 480 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 481 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 482 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 483 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 484 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 485 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 486 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 487 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \ 488 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 489 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 490 491 492 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 493 494 struct mlx5e_params_ethtool { 495 u64 arg [0]; 496 MLX5E_PARAMS(MLX5E_STATS_VAR) 497 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 498 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 499 u8 prio_tc[IEEE_8021QAZ_MAX_TCS]; 500 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 501 u8 trust_state; 502 }; 503 504 /* EEPROM Standards for plug in modules */ 505 #ifndef MLX5E_ETH_MODULE_SFF_8472 506 #define MLX5E_ETH_MODULE_SFF_8472 0x1 507 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128 508 #endif 509 510 #ifndef MLX5E_ETH_MODULE_SFF_8636 511 #define MLX5E_ETH_MODULE_SFF_8636 0x2 512 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256 513 #endif 514 515 #ifndef MLX5E_ETH_MODULE_SFF_8436 516 #define MLX5E_ETH_MODULE_SFF_8436 0x3 517 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256 518 #endif 519 520 /* EEPROM I2C Addresses */ 521 #define MLX5E_I2C_ADDR_LOW 0x50 522 #define MLX5E_I2C_ADDR_HIGH 0x51 523 524 #define MLX5E_EEPROM_LOW_PAGE 0x0 525 #define MLX5E_EEPROM_HIGH_PAGE 0x3 526 527 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 528 #define MLX5E_EEPROM_PAGE_LENGTH 256 529 530 #define MLX5E_EEPROM_INFO_BYTES 0x3 531 532 struct mlx5e_cq { 533 /* data path - accessed per cqe */ 534 struct mlx5_cqwq wq; 535 536 /* data path - accessed per HW polling */ 537 struct mlx5_core_cq mcq; 538 539 /* control */ 540 struct mlx5e_priv *priv; 541 struct mlx5_wq_ctrl wq_ctrl; 542 } __aligned(MLX5E_CACHELINE_SIZE); 543 544 struct mlx5e_rq_mbuf { 545 bus_dmamap_t dma_map; 546 caddr_t data; 547 struct mbuf *mbuf; 548 }; 549 550 struct mlx5e_rq { 551 /* data path */ 552 struct mlx5_wq_ll wq; 553 struct mtx mtx; 554 bus_dma_tag_t dma_tag; 555 u32 wqe_sz; 556 u32 nsegs; 557 struct mlx5e_rq_mbuf *mbuf; 558 struct ifnet *ifp; 559 struct mlx5e_rq_stats stats; 560 struct mlx5e_cq cq; 561 struct lro_ctrl lro; 562 volatile int enabled; 563 int ix; 564 565 /* control */ 566 struct mlx5_wq_ctrl wq_ctrl; 567 u32 rqn; 568 struct mlx5e_channel *channel; 569 struct callout watchdog; 570 } __aligned(MLX5E_CACHELINE_SIZE); 571 572 struct mlx5e_sq_mbuf { 573 bus_dmamap_t dma_map; 574 struct mbuf *mbuf; 575 u32 num_bytes; 576 u32 num_wqebbs; 577 }; 578 579 enum { 580 MLX5E_SQ_READY, 581 MLX5E_SQ_FULL 582 }; 583 584 struct mlx5e_snd_tag { 585 struct m_snd_tag m_snd_tag; /* send tag */ 586 u32 type; /* tag type */ 587 }; 588 589 struct mlx5e_sq { 590 /* data path */ 591 struct mtx lock; 592 bus_dma_tag_t dma_tag; 593 struct mtx comp_lock; 594 595 /* dirtied @completion */ 596 u16 cc; 597 598 /* dirtied @xmit */ 599 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 600 u16 bf_offset; 601 u16 cev_counter; /* completion event counter */ 602 u16 cev_factor; /* completion event factor */ 603 u16 cev_next_state; /* next completion event state */ 604 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 605 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 606 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 607 u16 running; /* set if SQ is running */ 608 struct callout cev_callout; 609 union { 610 u32 d32[2]; 611 u64 d64; 612 } doorbell; 613 struct mlx5e_sq_stats stats; 614 615 struct mlx5e_cq cq; 616 617 /* pointers to per packet info: write@xmit, read@completion */ 618 struct mlx5e_sq_mbuf *mbuf; 619 struct buf_ring *br; 620 621 /* read only */ 622 struct mlx5_wq_cyc wq; 623 struct mlx5_uar uar; 624 struct ifnet *ifp; 625 u32 sqn; 626 u32 bf_buf_size; 627 u32 mkey_be; 628 u16 max_inline; 629 u8 min_inline_mode; 630 u8 min_insert_caps; 631 #define MLX5E_INSERT_VLAN 1 632 #define MLX5E_INSERT_NON_VLAN 2 633 634 /* control path */ 635 struct mlx5_wq_ctrl wq_ctrl; 636 struct mlx5e_priv *priv; 637 int tc; 638 } __aligned(MLX5E_CACHELINE_SIZE); 639 640 static inline bool 641 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 642 { 643 u16 cc = sq->cc; 644 u16 pc = sq->pc; 645 646 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 647 } 648 649 static inline u32 650 mlx5e_sq_queue_level(struct mlx5e_sq *sq) 651 { 652 u16 cc; 653 u16 pc; 654 655 if (sq == NULL) 656 return (0); 657 658 cc = sq->cc; 659 pc = sq->pc; 660 661 return (((sq->wq.sz_m1 & (pc - cc)) * 662 IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1); 663 } 664 665 struct mlx5e_channel { 666 /* data path */ 667 struct mlx5e_rq rq; 668 struct mlx5e_snd_tag tag; 669 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 670 u32 mkey_be; 671 u8 num_tc; 672 673 /* control */ 674 struct mlx5e_priv *priv; 675 int ix; 676 int cpu; 677 } __aligned(MLX5E_CACHELINE_SIZE); 678 679 enum mlx5e_traffic_types { 680 MLX5E_TT_IPV4_TCP, 681 MLX5E_TT_IPV6_TCP, 682 MLX5E_TT_IPV4_UDP, 683 MLX5E_TT_IPV6_UDP, 684 MLX5E_TT_IPV4_IPSEC_AH, 685 MLX5E_TT_IPV6_IPSEC_AH, 686 MLX5E_TT_IPV4_IPSEC_ESP, 687 MLX5E_TT_IPV6_IPSEC_ESP, 688 MLX5E_TT_IPV4, 689 MLX5E_TT_IPV6, 690 MLX5E_TT_ANY, 691 MLX5E_NUM_TT, 692 }; 693 694 enum { 695 MLX5E_RQT_SPREADING = 0, 696 MLX5E_RQT_DEFAULT_RQ = 1, 697 MLX5E_NUM_RQT = 2, 698 }; 699 700 struct mlx5_flow_rule; 701 702 struct mlx5e_eth_addr_info { 703 u8 addr [ETH_ALEN + 2]; 704 u32 tt_vec; 705 /* flow table rule per traffic type */ 706 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 707 }; 708 709 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 710 711 struct mlx5e_eth_addr_hash_node; 712 713 struct mlx5e_eth_addr_hash_head { 714 struct mlx5e_eth_addr_hash_node *lh_first; 715 }; 716 717 struct mlx5e_eth_addr_db { 718 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 719 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 720 struct mlx5e_eth_addr_info broadcast; 721 struct mlx5e_eth_addr_info allmulti; 722 struct mlx5e_eth_addr_info promisc; 723 bool broadcast_enabled; 724 bool allmulti_enabled; 725 bool promisc_enabled; 726 }; 727 728 enum { 729 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 730 MLX5E_STATE_OPENED, 731 }; 732 733 enum { 734 MLX5_BW_NO_LIMIT = 0, 735 MLX5_100_MBPS_UNIT = 3, 736 MLX5_GBPS_UNIT = 4, 737 }; 738 739 struct mlx5e_vlan_db { 740 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 741 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 742 struct mlx5_flow_rule *untagged_ft_rule; 743 struct mlx5_flow_rule *any_cvlan_ft_rule; 744 struct mlx5_flow_rule *any_svlan_ft_rule; 745 bool filter_disabled; 746 }; 747 748 struct mlx5e_flow_table { 749 int num_groups; 750 struct mlx5_flow_table *t; 751 struct mlx5_flow_group **g; 752 }; 753 754 struct mlx5e_flow_tables { 755 struct mlx5_flow_namespace *ns; 756 struct mlx5e_flow_table vlan; 757 struct mlx5e_flow_table main; 758 struct mlx5e_flow_table inner_rss; 759 }; 760 761 #ifdef RATELIMIT 762 #include "en_rl.h" 763 #endif 764 765 #define MLX5E_TSTMP_PREC 10 766 767 struct mlx5e_clbr_point { 768 uint64_t base_curr; 769 uint64_t base_prev; 770 uint64_t clbr_hw_prev; 771 uint64_t clbr_hw_curr; 772 u_int clbr_gen; 773 }; 774 775 struct mlx5e_priv { 776 struct mlx5_core_dev *mdev; /* must be first */ 777 778 /* priv data path fields - start */ 779 int order_base_2_num_channels; 780 int queue_mapping_channel_mask; 781 int num_tc; 782 int default_vlan_prio; 783 /* priv data path fields - end */ 784 785 unsigned long state; 786 int gone; 787 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 788 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 789 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 790 struct sx state_lock; /* Protects Interface state */ 791 struct mlx5_uar cq_uar; 792 u32 pdn; 793 u32 tdn; 794 struct mlx5_core_mr mr; 795 volatile unsigned int channel_refs; 796 797 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 798 u32 rqtn; 799 u32 tirn[MLX5E_NUM_TT]; 800 801 struct mlx5e_flow_tables fts; 802 struct mlx5e_eth_addr_db eth_addr; 803 struct mlx5e_vlan_db vlan; 804 805 struct mlx5e_params params; 806 struct mlx5e_params_ethtool params_ethtool; 807 union mlx5_core_pci_diagnostics params_pci; 808 union mlx5_core_general_diagnostics params_general; 809 struct mtx async_events_mtx; /* sync hw events */ 810 struct work_struct update_stats_work; 811 struct work_struct update_carrier_work; 812 struct work_struct set_rx_mode_work; 813 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 814 815 struct ifnet *ifp; 816 struct sysctl_ctx_list sysctl_ctx; 817 struct sysctl_oid *sysctl_ifnet; 818 struct sysctl_oid *sysctl_hw; 819 int sysctl_debug; 820 struct mlx5e_stats stats; 821 int counter_set_id; 822 823 struct workqueue_struct *wq; 824 825 eventhandler_tag vlan_detach; 826 eventhandler_tag vlan_attach; 827 struct ifmedia media; 828 int media_status_last; 829 int media_active_last; 830 831 struct callout watchdog; 832 #ifdef RATELIMIT 833 struct mlx5e_rl_priv_data rl; 834 #endif 835 836 struct callout tstmp_clbr; 837 int clbr_done; 838 int clbr_curr; 839 struct mlx5e_clbr_point clbr_points[2]; 840 u_int clbr_gen; 841 842 struct pfil_head *pfil; 843 struct mlx5e_channel channel[]; 844 }; 845 846 #define MLX5E_NET_IP_ALIGN 2 847 848 struct mlx5e_tx_wqe { 849 struct mlx5_wqe_ctrl_seg ctrl; 850 struct mlx5_wqe_eth_seg eth; 851 }; 852 853 struct mlx5e_rx_wqe { 854 struct mlx5_wqe_srq_next_seg next; 855 struct mlx5_wqe_data_seg data[]; 856 }; 857 858 /* the size of the structure above must be power of two */ 859 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 860 861 struct mlx5e_eeprom { 862 int lock_bit; 863 int i2c_addr; 864 int page_num; 865 int device_addr; 866 int module_num; 867 int len; 868 int type; 869 int page_valid; 870 u32 *data; 871 }; 872 873 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 874 875 int mlx5e_xmit(struct ifnet *, struct mbuf *); 876 877 int mlx5e_open_locked(struct ifnet *); 878 int mlx5e_close_locked(struct ifnet *); 879 880 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 881 void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 882 void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 883 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 884 885 int mlx5e_open_flow_table(struct mlx5e_priv *priv); 886 void mlx5e_close_flow_table(struct mlx5e_priv *priv); 887 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 888 void mlx5e_set_rx_mode_work(struct work_struct *work); 889 890 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 891 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 892 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 893 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 894 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 895 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 896 897 static inline void 898 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 899 { 900 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 901 902 /* ensure wqe is visible to device before updating doorbell record */ 903 wmb(); 904 905 *sq->wq.db = cpu_to_be32(sq->pc); 906 907 /* 908 * Ensure the doorbell record is visible to device before ringing 909 * the doorbell: 910 */ 911 wmb(); 912 913 if (bf_sz) { 914 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 915 916 /* flush the write-combining mapped buffer */ 917 wmb(); 918 919 } else { 920 mlx5_write64(wqe, sq->uar.map + ofst, 921 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 922 } 923 924 sq->bf_offset ^= sq->bf_buf_size; 925 } 926 927 static inline void 928 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 929 { 930 struct mlx5_core_cq *mcq; 931 932 mcq = &cq->mcq; 933 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 934 } 935 936 static inline void 937 mlx5e_ref_channel(struct mlx5e_priv *priv) 938 { 939 940 KASSERT(priv->channel_refs < INT_MAX, 941 ("Channel refs will overflow")); 942 atomic_fetchadd_int(&priv->channel_refs, 1); 943 } 944 945 static inline void 946 mlx5e_unref_channel(struct mlx5e_priv *priv) 947 { 948 949 KASSERT(priv->channel_refs > 0, 950 ("Channel refs is not greater than zero")); 951 atomic_fetchadd_int(&priv->channel_refs, -1); 952 } 953 954 extern const struct ethtool_ops mlx5e_ethtool_ops; 955 void mlx5e_create_ethtool(struct mlx5e_priv *); 956 void mlx5e_create_stats(struct sysctl_ctx_list *, 957 struct sysctl_oid_list *, const char *, 958 const char **, unsigned, u64 *); 959 void mlx5e_send_nop(struct mlx5e_sq *, u32); 960 void mlx5e_sq_cev_timeout(void *); 961 int mlx5e_refresh_channel_params(struct mlx5e_priv *); 962 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 963 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 964 void mlx5e_close_cq(struct mlx5e_cq *); 965 void mlx5e_free_sq_db(struct mlx5e_sq *); 966 int mlx5e_alloc_sq_db(struct mlx5e_sq *); 967 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 968 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 969 void mlx5e_disable_sq(struct mlx5e_sq *); 970 void mlx5e_drain_sq(struct mlx5e_sq *); 971 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 972 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 973 void mlx5e_resume_sq(struct mlx5e_sq *sq); 974 void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 975 void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 976 977 #endif /* _MLX5_EN_H_ */ 978