1 /*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _MLX5_EN_H_ 29 #define _MLX5_EN_H_ 30 31 #include <linux/kmod.h> 32 #include <linux/page.h> 33 #include <linux/slab.h> 34 #include <linux/if_vlan.h> 35 #include <linux/if_ether.h> 36 #include <linux/vmalloc.h> 37 #include <linux/moduleparam.h> 38 #include <linux/delay.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 42 #include <netinet/in_systm.h> 43 #include <netinet/in.h> 44 #include <netinet/if_ether.h> 45 #include <netinet/ip.h> 46 #include <netinet/ip6.h> 47 #include <netinet/tcp.h> 48 #include <netinet/tcp_lro.h> 49 #include <netinet/udp.h> 50 #include <net/ethernet.h> 51 #include <sys/buf_ring.h> 52 53 #include "opt_rss.h" 54 55 #ifdef RSS 56 #include <net/rss_config.h> 57 #include <netinet/in_rss.h> 58 #endif 59 60 #include <machine/bus.h> 61 62 #include <dev/mlx5/driver.h> 63 #include <dev/mlx5/qp.h> 64 #include <dev/mlx5/cq.h> 65 #include <dev/mlx5/vport.h> 66 #include <dev/mlx5/diagnostics.h> 67 68 #include <dev/mlx5/mlx5_core/wq.h> 69 #include <dev/mlx5/mlx5_core/transobj.h> 70 #include <dev/mlx5/mlx5_core/mlx5_core.h> 71 72 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 73 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 74 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 75 76 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 77 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 78 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 79 80 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */ 81 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 84 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 85 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 86 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 87 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 88 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 89 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 90 #define MLX5E_HW2SW_MTU(hwmtu) \ 91 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 92 #define MLX5E_SW2HW_MTU(swmtu) \ 93 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 94 #define MLX5E_SW2MB_MTU(swmtu) \ 95 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 96 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 97 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 98 * jumbo frames */ 99 100 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 101 #define MLX5E_RX_BUDGET_MAX 256 102 #define MLX5E_SQ_BF_BUDGET 16 103 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 104 105 #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 106 #define MLX5E_MAX_TX_HEADER 128 /* bytes */ 107 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 108 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 109 #define MLX5E_MAX_TX_MBUF_FRAGS \ 110 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 111 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */ 112 #define MLX5E_MAX_TX_INLINE \ 113 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 114 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 115 116 MALLOC_DECLARE(M_MLX5EN); 117 118 struct mlx5_core_dev; 119 struct mlx5e_cq; 120 121 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 122 123 #define MLX5E_STATS_COUNT(a,b,c,d) a 124 #define MLX5E_STATS_VAR(a,b,c,d) b; 125 #define MLX5E_STATS_DESC(a,b,c,d) c, d, 126 127 #define MLX5E_VPORT_STATS(m) \ 128 /* HW counters */ \ 129 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 130 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 131 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 132 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 133 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 134 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 135 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 136 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 137 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 138 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 139 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 140 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 141 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 142 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 143 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 144 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 145 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 146 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 147 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 148 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 149 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 150 /* SW counters */ \ 151 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 152 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 153 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 154 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 155 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 156 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 157 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 158 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 159 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 160 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 161 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 162 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") 163 164 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 165 166 struct mlx5e_vport_stats { 167 struct sysctl_ctx_list ctx; 168 u64 arg [0]; 169 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 170 u32 rx_out_of_buffer_prev; 171 }; 172 173 #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 174 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 175 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 176 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 177 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 178 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 179 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 180 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 181 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 182 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 183 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 184 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 185 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 186 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 187 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 188 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 189 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 190 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 191 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 192 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 193 194 #define MLX5E_PPORT_RFC2819_STATS(m) \ 195 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 196 m(+1, u64 octets, "octets", "Octets") \ 197 m(+1, u64 pkts, "pkts", "Packets") \ 198 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 199 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 200 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 201 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 202 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 203 m(+1, u64 fragments, "fragments", "Fragments") \ 204 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 205 m(+1, u64 collisions, "collisions", "Collisions") 206 207 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 208 m(+1, u64 p64octets, "p64octets", "Bytes") \ 209 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 210 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 211 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 212 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 213 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 214 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 215 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 216 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 217 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 218 219 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 220 m(+1, u64 in_octets, "in_octets", "In octets") \ 221 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 222 m(+1, u64 in_discards, "in_discards", "In discards") \ 223 m(+1, u64 in_errors, "in_errors", "In errors") \ 224 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 225 m(+1, u64 out_octets, "out_octets", "Out octets") \ 226 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 227 m(+1, u64 out_discards, "out_discards", "Out discards") \ 228 m(+1, u64 out_errors, "out_errors", "Out errors") \ 229 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 230 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 231 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 232 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 233 234 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 235 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 236 "Time since the last counters clear event (msec)") \ 237 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 238 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 239 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 240 "Indicates the number of PRBS errors on lane 0") \ 241 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 242 "Indicates the number of PRBS errors on lane 1") \ 243 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 244 "Indicates the number of PRBS errors on lane 2") \ 245 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 246 "Indicates the number of PRBS errors on lane 3") \ 247 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 248 "FEC correctable block counter lane 0") \ 249 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 250 "FEC correctable block counter lane 1") \ 251 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 252 "FEC correctable block counter lane 2") \ 253 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 254 "FEC correctable block counter lane 3") \ 255 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 256 "FEC correcable block counter") \ 257 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 258 "FEC uncorrecable block counter") \ 259 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 260 "The number of RS-FEC blocks received that had no errors") \ 261 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 262 "The number of corrected RS-FEC blocks received that had" \ 263 "exactly 1 error symbol") \ 264 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 265 "Port FEC corrected symbol counter") \ 266 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 267 "FEC corrected symbol counter lane 0") \ 268 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 269 "FEC corrected symbol counter lane 1") \ 270 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 271 "FEC corrected symbol counter lane 2") \ 272 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 273 "FEC corrected symbol counter lane 3") \ 274 275 /* 276 * Make sure to update mlx5e_update_pport_counters() 277 * when adding a new MLX5E_PPORT_STATS block 278 */ 279 #define MLX5E_PPORT_STATS(m) \ 280 MLX5E_PPORT_IEEE802_3_STATS(m) \ 281 MLX5E_PPORT_RFC2819_STATS(m) 282 283 #define MLX5E_PORT_STATS_DEBUG(m) \ 284 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 285 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 286 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 287 288 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 289 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 290 #define MLX5E_PPORT_RFC2819_STATS_NUM \ 291 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 292 #define MLX5E_PPORT_STATS_NUM \ 293 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 294 295 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 296 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 297 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 298 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 299 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 300 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 301 #define MLX5E_PORT_STATS_DEBUG_NUM \ 302 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 303 304 struct mlx5e_pport_stats { 305 struct sysctl_ctx_list ctx; 306 u64 arg [0]; 307 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 308 }; 309 310 struct mlx5e_port_stats_debug { 311 struct sysctl_ctx_list ctx; 312 u64 arg [0]; 313 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 314 }; 315 316 #define MLX5E_RQ_STATS(m) \ 317 m(+1, u64 packets, "packets", "Received packets") \ 318 m(+1, u64 csum_none, "csum_none", "Received packets") \ 319 m(+1, u64 lro_packets, "lro_packets", "Received packets") \ 320 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \ 321 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 322 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 323 m(+1, u64 wqe_err, "wqe_err", "Received packets") 324 325 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 326 327 struct mlx5e_rq_stats { 328 struct sysctl_ctx_list ctx; 329 u64 arg [0]; 330 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 331 }; 332 333 #define MLX5E_SQ_STATS(m) \ 334 m(+1, u64 packets, "packets", "Transmitted packets") \ 335 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 336 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 337 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 338 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 339 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 340 m(+1, u64 nop, "nop", "Transmitted packets") 341 342 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 343 344 struct mlx5e_sq_stats { 345 struct sysctl_ctx_list ctx; 346 u64 arg [0]; 347 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 348 }; 349 350 struct mlx5e_stats { 351 struct mlx5e_vport_stats vport; 352 struct mlx5e_pport_stats pport; 353 struct mlx5e_port_stats_debug port_stats_debug; 354 }; 355 356 struct mlx5e_rq_param { 357 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 358 struct mlx5_wq_param wq; 359 }; 360 361 struct mlx5e_sq_param { 362 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 363 struct mlx5_wq_param wq; 364 }; 365 366 struct mlx5e_cq_param { 367 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 368 struct mlx5_wq_param wq; 369 }; 370 371 struct mlx5e_params { 372 u8 log_sq_size; 373 u8 log_rq_size; 374 u16 num_channels; 375 u8 default_vlan_prio; 376 u8 num_tc; 377 u8 rx_cq_moderation_mode; 378 u8 tx_cq_moderation_mode; 379 u16 rx_cq_moderation_usec; 380 u16 rx_cq_moderation_pkts; 381 u16 tx_cq_moderation_usec; 382 u16 tx_cq_moderation_pkts; 383 u16 min_rx_wqes; 384 bool hw_lro_en; 385 bool cqe_zipping_en; 386 u32 lro_wqe_sz; 387 u16 rx_hash_log_tbl_sz; 388 u32 tx_pauseframe_control; 389 u32 rx_pauseframe_control; 390 }; 391 392 #define MLX5E_PARAMS(m) \ 393 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 394 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 395 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 396 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 397 m(+1, u64 channels, "channels", "Default number of channels") \ 398 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 399 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 400 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 401 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 402 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 403 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 404 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 405 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 406 m(+1, u64 tx_bufring_disable, "tx_bufring_disable", "0: Enable bufring 1: Disable bufring") \ 407 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 408 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 409 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 410 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 411 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 412 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") 413 414 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 415 416 struct mlx5e_params_ethtool { 417 u64 arg [0]; 418 MLX5E_PARAMS(MLX5E_STATS_VAR) 419 }; 420 421 /* EEPROM Standards for plug in modules */ 422 #ifndef MLX5E_ETH_MODULE_SFF_8472 423 #define MLX5E_ETH_MODULE_SFF_8472 0x1 424 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128 425 #endif 426 427 #ifndef MLX5E_ETH_MODULE_SFF_8636 428 #define MLX5E_ETH_MODULE_SFF_8636 0x2 429 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256 430 #endif 431 432 #ifndef MLX5E_ETH_MODULE_SFF_8436 433 #define MLX5E_ETH_MODULE_SFF_8436 0x3 434 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256 435 #endif 436 437 /* EEPROM I2C Addresses */ 438 #define MLX5E_I2C_ADDR_LOW 0x50 439 #define MLX5E_I2C_ADDR_HIGH 0x51 440 441 #define MLX5E_EEPROM_LOW_PAGE 0x0 442 #define MLX5E_EEPROM_HIGH_PAGE 0x3 443 444 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 445 #define MLX5E_EEPROM_PAGE_LENGTH 256 446 447 #define MLX5E_EEPROM_INFO_BYTES 0x3 448 449 struct mlx5e_cq { 450 /* data path - accessed per cqe */ 451 struct mlx5_cqwq wq; 452 453 /* data path - accessed per HW polling */ 454 struct mlx5_core_cq mcq; 455 456 /* control */ 457 struct mlx5e_priv *priv; 458 struct mlx5_wq_ctrl wq_ctrl; 459 } __aligned(MLX5E_CACHELINE_SIZE); 460 461 struct mlx5e_rq_mbuf { 462 bus_dmamap_t dma_map; 463 caddr_t data; 464 struct mbuf *mbuf; 465 }; 466 467 struct mlx5e_rq { 468 /* data path */ 469 struct mlx5_wq_ll wq; 470 struct mtx mtx; 471 bus_dma_tag_t dma_tag; 472 u32 wqe_sz; 473 struct mlx5e_rq_mbuf *mbuf; 474 struct ifnet *ifp; 475 struct mlx5e_rq_stats stats; 476 struct mlx5e_cq cq; 477 struct lro_ctrl lro; 478 volatile int enabled; 479 int ix; 480 481 /* control */ 482 struct mlx5_wq_ctrl wq_ctrl; 483 u32 rqn; 484 struct mlx5e_channel *channel; 485 struct callout watchdog; 486 } __aligned(MLX5E_CACHELINE_SIZE); 487 488 struct mlx5e_sq_mbuf { 489 bus_dmamap_t dma_map; 490 struct mbuf *mbuf; 491 u32 num_bytes; 492 u32 num_wqebbs; 493 }; 494 495 enum { 496 MLX5E_SQ_READY, 497 MLX5E_SQ_FULL 498 }; 499 500 struct mlx5e_sq { 501 /* data path */ 502 struct mtx lock; 503 bus_dma_tag_t dma_tag; 504 struct mtx comp_lock; 505 506 /* dirtied @completion */ 507 u16 cc; 508 509 /* dirtied @xmit */ 510 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 511 u16 bf_offset; 512 u16 cev_counter; /* completion event counter */ 513 u16 cev_factor; /* completion event factor */ 514 u16 cev_next_state; /* next completion event state */ 515 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 516 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 517 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 518 u16 stopped; /* set if SQ is stopped */ 519 struct callout cev_callout; 520 union { 521 u32 d32[2]; 522 u64 d64; 523 } doorbell; 524 struct mlx5e_sq_stats stats; 525 526 struct mlx5e_cq cq; 527 struct task sq_task; 528 struct taskqueue *sq_tq; 529 530 /* pointers to per packet info: write@xmit, read@completion */ 531 struct mlx5e_sq_mbuf *mbuf; 532 struct buf_ring *br; 533 534 /* read only */ 535 struct mlx5_wq_cyc wq; 536 struct mlx5_uar uar; 537 struct ifnet *ifp; 538 u32 sqn; 539 u32 bf_buf_size; 540 u32 mkey_be; 541 542 /* control path */ 543 struct mlx5_wq_ctrl wq_ctrl; 544 struct mlx5e_priv *priv; 545 int tc; 546 unsigned int queue_state; 547 } __aligned(MLX5E_CACHELINE_SIZE); 548 549 static inline bool 550 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 551 { 552 u16 cc = sq->cc; 553 u16 pc = sq->pc; 554 555 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 556 } 557 558 struct mlx5e_channel { 559 /* data path */ 560 struct mlx5e_rq rq; 561 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 562 struct ifnet *ifp; 563 u32 mkey_be; 564 u8 num_tc; 565 566 /* control */ 567 struct mlx5e_priv *priv; 568 int ix; 569 int cpu; 570 } __aligned(MLX5E_CACHELINE_SIZE); 571 572 enum mlx5e_traffic_types { 573 MLX5E_TT_IPV4_TCP, 574 MLX5E_TT_IPV6_TCP, 575 MLX5E_TT_IPV4_UDP, 576 MLX5E_TT_IPV6_UDP, 577 MLX5E_TT_IPV4_IPSEC_AH, 578 MLX5E_TT_IPV6_IPSEC_AH, 579 MLX5E_TT_IPV4_IPSEC_ESP, 580 MLX5E_TT_IPV6_IPSEC_ESP, 581 MLX5E_TT_IPV4, 582 MLX5E_TT_IPV6, 583 MLX5E_TT_ANY, 584 MLX5E_NUM_TT, 585 }; 586 587 enum { 588 MLX5E_RQT_SPREADING = 0, 589 MLX5E_RQT_DEFAULT_RQ = 1, 590 MLX5E_NUM_RQT = 2, 591 }; 592 593 struct mlx5e_eth_addr_info { 594 u8 addr [ETH_ALEN + 2]; 595 u32 tt_vec; 596 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */ 597 }; 598 599 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 600 601 struct mlx5e_eth_addr_hash_node; 602 603 struct mlx5e_eth_addr_hash_head { 604 struct mlx5e_eth_addr_hash_node *lh_first; 605 }; 606 607 struct mlx5e_eth_addr_db { 608 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 609 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 610 struct mlx5e_eth_addr_info broadcast; 611 struct mlx5e_eth_addr_info allmulti; 612 struct mlx5e_eth_addr_info promisc; 613 bool broadcast_enabled; 614 bool allmulti_enabled; 615 bool promisc_enabled; 616 }; 617 618 enum { 619 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 620 MLX5E_STATE_OPENED, 621 }; 622 623 struct mlx5e_vlan_db { 624 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 625 u32 active_vlans_ft_ix[VLAN_N_VID]; 626 u32 untagged_rule_ft_ix; 627 u32 any_vlan_rule_ft_ix; 628 bool filter_disabled; 629 }; 630 631 struct mlx5e_flow_table { 632 void *vlan; 633 void *main; 634 }; 635 636 struct mlx5e_priv { 637 /* priv data path fields - start */ 638 int order_base_2_num_channels; 639 int queue_mapping_channel_mask; 640 int num_tc; 641 int default_vlan_prio; 642 /* priv data path fields - end */ 643 644 unsigned long state; 645 int gone; 646 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 647 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 648 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 649 struct sx state_lock; /* Protects Interface state */ 650 struct mlx5_uar cq_uar; 651 u32 pdn; 652 u32 tdn; 653 struct mlx5_core_mr mr; 654 655 struct mlx5e_channel *volatile *channel; 656 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 657 u32 rqtn; 658 u32 tirn[MLX5E_NUM_TT]; 659 660 struct mlx5e_flow_table ft; 661 struct mlx5e_eth_addr_db eth_addr; 662 struct mlx5e_vlan_db vlan; 663 664 struct mlx5e_params params; 665 struct mlx5e_params_ethtool params_ethtool; 666 union mlx5_core_pci_diagnostics params_pci; 667 union mlx5_core_general_diagnostics params_general; 668 struct mtx async_events_mtx; /* sync hw events */ 669 struct work_struct update_stats_work; 670 struct work_struct update_carrier_work; 671 struct work_struct set_rx_mode_work; 672 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 673 674 struct mlx5_core_dev *mdev; 675 struct ifnet *ifp; 676 struct sysctl_ctx_list sysctl_ctx; 677 struct sysctl_oid *sysctl_ifnet; 678 struct sysctl_oid *sysctl_hw; 679 int sysctl_debug; 680 struct mlx5e_stats stats; 681 int counter_set_id; 682 683 eventhandler_tag vlan_detach; 684 eventhandler_tag vlan_attach; 685 struct ifmedia media; 686 int media_status_last; 687 int media_active_last; 688 689 struct callout watchdog; 690 }; 691 692 #define MLX5E_NET_IP_ALIGN 2 693 694 struct mlx5e_tx_wqe { 695 struct mlx5_wqe_ctrl_seg ctrl; 696 struct mlx5_wqe_eth_seg eth; 697 }; 698 699 struct mlx5e_rx_wqe { 700 struct mlx5_wqe_srq_next_seg next; 701 struct mlx5_wqe_data_seg data; 702 }; 703 704 struct mlx5e_eeprom { 705 int lock_bit; 706 int i2c_addr; 707 int page_num; 708 int device_addr; 709 int module_num; 710 int len; 711 int type; 712 int page_valid; 713 u32 *data; 714 }; 715 716 enum mlx5e_link_mode { 717 MLX5E_1000BASE_CX_SGMII = 0, 718 MLX5E_1000BASE_KX = 1, 719 MLX5E_10GBASE_CX4 = 2, 720 MLX5E_10GBASE_KX4 = 3, 721 MLX5E_10GBASE_KR = 4, 722 MLX5E_20GBASE_KR2 = 5, 723 MLX5E_40GBASE_CR4 = 6, 724 MLX5E_40GBASE_KR4 = 7, 725 MLX5E_56GBASE_R4 = 8, 726 MLX5E_10GBASE_CR = 12, 727 MLX5E_10GBASE_SR = 13, 728 MLX5E_10GBASE_LR = 14, 729 MLX5E_40GBASE_SR4 = 15, 730 MLX5E_40GBASE_LR4 = 16, 731 MLX5E_100GBASE_CR4 = 20, 732 MLX5E_100GBASE_SR4 = 21, 733 MLX5E_100GBASE_KR4 = 22, 734 MLX5E_100GBASE_LR4 = 23, 735 MLX5E_100BASE_TX = 24, 736 MLX5E_100BASE_T = 25, 737 MLX5E_10GBASE_T = 26, 738 MLX5E_25GBASE_CR = 27, 739 MLX5E_25GBASE_KR = 28, 740 MLX5E_25GBASE_SR = 29, 741 MLX5E_50GBASE_CR2 = 30, 742 MLX5E_50GBASE_KR2 = 31, 743 MLX5E_LINK_MODES_NUMBER, 744 }; 745 746 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode)) 747 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 748 749 int mlx5e_xmit(struct ifnet *, struct mbuf *); 750 751 int mlx5e_open_locked(struct ifnet *); 752 int mlx5e_close_locked(struct ifnet *); 753 754 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 755 void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 756 void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 757 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 758 void mlx5e_tx_que(void *context, int pending); 759 760 int mlx5e_open_flow_table(struct mlx5e_priv *priv); 761 void mlx5e_close_flow_table(struct mlx5e_priv *priv); 762 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 763 void mlx5e_set_rx_mode_work(struct work_struct *work); 764 765 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 766 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 767 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 768 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 769 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 770 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 771 772 static inline void 773 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 774 { 775 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 776 777 /* ensure wqe is visible to device before updating doorbell record */ 778 wmb(); 779 780 *sq->wq.db = cpu_to_be32(sq->pc); 781 782 /* 783 * Ensure the doorbell record is visible to device before ringing 784 * the doorbell: 785 */ 786 wmb(); 787 788 if (bf_sz) { 789 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 790 791 /* flush the write-combining mapped buffer */ 792 wmb(); 793 794 } else { 795 mlx5_write64(wqe, sq->uar.map + ofst, 796 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 797 } 798 799 sq->bf_offset ^= sq->bf_buf_size; 800 } 801 802 static inline void 803 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 804 { 805 struct mlx5_core_cq *mcq; 806 807 mcq = &cq->mcq; 808 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 809 } 810 811 extern const struct ethtool_ops mlx5e_ethtool_ops; 812 void mlx5e_create_ethtool(struct mlx5e_priv *); 813 void mlx5e_create_stats(struct sysctl_ctx_list *, 814 struct sysctl_oid_list *, const char *, 815 const char **, unsigned, u64 *); 816 void mlx5e_send_nop(struct mlx5e_sq *, u32); 817 void mlx5e_sq_cev_timeout(void *); 818 int mlx5e_refresh_channel_params(struct mlx5e_priv *); 819 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 820 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 821 void mlx5e_close_cq(struct mlx5e_cq *); 822 void mlx5e_free_sq_db(struct mlx5e_sq *); 823 int mlx5e_alloc_sq_db(struct mlx5e_sq *); 824 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 825 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 826 void mlx5e_disable_sq(struct mlx5e_sq *); 827 void mlx5e_drain_sq(struct mlx5e_sq *); 828 829 #endif /* _MLX5_EN_H_ */ 830