xref: /freebsd/sys/dev/mlx5/driver.h (revision f5541f9f473430a3e608e07f623294322853d25a) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  * Copyright (c) 2022 NVIDIA corporation & affiliates.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #ifndef MLX5_DRIVER_H
28 #define MLX5_DRIVER_H
29 
30 #include "opt_ratelimit.h"
31 
32 #include <linux/kernel.h>
33 #include <linux/completion.h>
34 #include <linux/pci.h>
35 #include <linux/cache.h>
36 #include <linux/rbtree.h>
37 #include <linux/if_ether.h>
38 #include <linux/semaphore.h>
39 #include <linux/slab.h>
40 #include <linux/vmalloc.h>
41 #include <linux/radix-tree.h>
42 #include <linux/idr.h>
43 #include <linux/wait.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 #define MLX5_INVALID_QUEUE_HANDLE 0xffffffff
53 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
54 
55 enum {
56 	MLX5_BOARD_ID_LEN = 64,
57 	MLX5_MAX_NAME_LEN = 16,
58 };
59 
60 enum {
61 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
62 };
63 
64 enum {
65 	CMD_OWNER_SW		= 0x0,
66 	CMD_OWNER_HW		= 0x1,
67 	CMD_STATUS_SUCCESS	= 0,
68 };
69 
70 enum mlx5_sqp_t {
71 	MLX5_SQP_SMI		= 0,
72 	MLX5_SQP_GSI		= 1,
73 	MLX5_SQP_IEEE_1588	= 2,
74 	MLX5_SQP_SNIFFER	= 3,
75 	MLX5_SQP_SYNC_UMR	= 4,
76 };
77 
78 enum {
79 	MLX5_MAX_PORTS	= 2,
80 };
81 
82 enum {
83 	MLX5_EQ_VEC_PAGES	 = 0,
84 	MLX5_EQ_VEC_CMD		 = 1,
85 	MLX5_EQ_VEC_ASYNC	 = 2,
86 	MLX5_EQ_VEC_COMP_BASE,
87 };
88 
89 enum {
90 	MLX5_ATOMIC_MODE_OFF		= 16,
91 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
98 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
99 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
100 };
101 
102 enum {
103 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
104 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
111 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
112 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
113 };
114 
115 enum {
116 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
117 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
118 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
119 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
120 };
121 
122 enum {
123 	MLX5_REG_QPTS		 = 0x4002,
124 	MLX5_REG_QETCR		 = 0x4005,
125 	MLX5_REG_QPDP		 = 0x4007,
126 	MLX5_REG_QTCT		 = 0x400A,
127 	MLX5_REG_QPDPM		 = 0x4013,
128 	MLX5_REG_QHLL		 = 0x4016,
129 	MLX5_REG_QCAM		 = 0x4019,
130 	MLX5_REG_DCBX_PARAM	 = 0x4020,
131 	MLX5_REG_DCBX_APP	 = 0x4021,
132 	MLX5_REG_FPGA_CAP	 = 0x4022,
133 	MLX5_REG_FPGA_CTRL	 = 0x4023,
134 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
135 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
136 	MLX5_REG_PCAP		 = 0x5001,
137 	MLX5_REG_PMLP		 = 0x5002,
138 	MLX5_REG_PMTU		 = 0x5003,
139 	MLX5_REG_PTYS		 = 0x5004,
140 	MLX5_REG_PAOS		 = 0x5006,
141 	MLX5_REG_PFCC		 = 0x5007,
142 	MLX5_REG_PPCNT		 = 0x5008,
143 	MLX5_REG_PUDE		 = 0x5009,
144 	MLX5_REG_PPTB		 = 0x500B,
145 	MLX5_REG_PBMC		 = 0x500C,
146 	MLX5_REG_PELC		 = 0x500E,
147 	MLX5_REG_PVLC		 = 0x500F,
148 	MLX5_REG_PMPE		 = 0x5010,
149 	MLX5_REG_PMAOS		 = 0x5012,
150 	MLX5_REG_PPLM		 = 0x5023,
151 	MLX5_REG_PDDR		 = 0x5031,
152 	MLX5_REG_PBSR		 = 0x5038,
153 	MLX5_REG_PCAM		 = 0x507f,
154 	MLX5_REG_NODE_DESC	 = 0x6001,
155 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
156 	MLX5_REG_MTMP		 = 0x900a,
157 	MLX5_REG_MCIA		 = 0x9014,
158 	MLX5_REG_MFRL		 = 0x9028,
159 	MLX5_REG_MPCNT		 = 0x9051,
160 	MLX5_REG_MCQI		 = 0x9061,
161 	MLX5_REG_MCC		 = 0x9062,
162 	MLX5_REG_MCDA		 = 0x9063,
163 	MLX5_REG_MCAM		 = 0x907f,
164 };
165 
166 enum dbg_rsc_type {
167 	MLX5_DBG_RSC_QP,
168 	MLX5_DBG_RSC_EQ,
169 	MLX5_DBG_RSC_CQ,
170 };
171 
172 enum {
173 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
174 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
175 	MLX5_INTERFACE_NUMBER       = 2,
176 };
177 
178 struct mlx5_field_desc {
179 	int			i;
180 };
181 
182 struct mlx5_rsc_debug {
183 	struct mlx5_core_dev   *dev;
184 	void		       *object;
185 	enum dbg_rsc_type	type;
186 	struct mlx5_field_desc	fields[0];
187 };
188 
189 enum mlx5_dev_event {
190 	MLX5_DEV_EVENT_SYS_ERROR,
191 	MLX5_DEV_EVENT_PORT_UP,
192 	MLX5_DEV_EVENT_PORT_DOWN,
193 	MLX5_DEV_EVENT_PORT_INITIALIZED,
194 	MLX5_DEV_EVENT_LID_CHANGE,
195 	MLX5_DEV_EVENT_PKEY_CHANGE,
196 	MLX5_DEV_EVENT_GUID_CHANGE,
197 	MLX5_DEV_EVENT_CLIENT_REREG,
198 	MLX5_DEV_EVENT_VPORT_CHANGE,
199 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
200 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
201 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
202 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
203 };
204 
205 enum mlx5_port_status {
206 	MLX5_PORT_UP        = 1 << 0,
207 	MLX5_PORT_DOWN      = 1 << 1,
208 };
209 
210 enum {
211 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
212 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
213 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
214 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
215 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
216 	MLX5_VSC_DATA_OFFSET	 = 0x14,
217 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
218 };
219 
220 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
221 
222 struct mlx5_cmd_first {
223 	__be32		data[4];
224 };
225 
226 struct cache_ent;
227 struct mlx5_fw_page {
228 	union {
229 		struct rb_node rb_node;
230 		struct list_head list;
231 	};
232 	struct mlx5_cmd_first first;
233 	struct mlx5_core_dev *dev;
234 	bus_dmamap_t dma_map;
235 	bus_addr_t dma_addr;
236 	void *virt_addr;
237 	struct cache_ent *cache;
238 	u32 numpages;
239 	u16 load_done;
240 #define	MLX5_LOAD_ST_NONE 0
241 #define	MLX5_LOAD_ST_SUCCESS 1
242 #define	MLX5_LOAD_ST_FAILURE 2
243 	u16 func_id;
244 };
245 #define	mlx5_cmd_msg mlx5_fw_page
246 
247 struct mlx5_cmd_debug {
248 	void		       *in_msg;
249 	void		       *out_msg;
250 	u8			status;
251 	u16			inlen;
252 	u16			outlen;
253 };
254 
255 struct cache_ent {
256 	/* protect block chain allocations
257 	 */
258 	spinlock_t		lock;
259 	struct list_head	head;
260 };
261 
262 struct cmd_msg_cache {
263 	struct cache_ent	large;
264 	struct cache_ent	med;
265 
266 };
267 
268 struct mlx5_traffic_counter {
269 	u64         packets;
270 	u64         octets;
271 };
272 
273 struct mlx5_fc_pool {
274 	struct mlx5_core_dev *dev;
275 	struct mutex pool_lock; /* protects pool lists */
276 	struct list_head fully_used;
277 	struct list_head partially_used;
278 	struct list_head unused;
279 	int available_fcs;
280 	int used_fcs;
281 	int threshold;
282 };
283 
284 struct mlx5_fc_stats {
285 	spinlock_t counters_idr_lock; /* protects counters_idr */
286 	struct idr counters_idr;
287 	struct list_head counters;
288 	struct llist_head addlist;
289 	struct llist_head dellist;
290 
291 	struct workqueue_struct *wq;
292 	struct delayed_work work;
293 	unsigned long next_query;
294 	unsigned long sampling_interval; /* jiffies */
295 	u32 *bulk_query_out;
296 	int bulk_query_len;
297 	size_t num_counters;
298 	bool bulk_query_alloc_failed;
299 	unsigned long next_bulk_query_alloc;
300 	struct mlx5_fc_pool fc_pool;
301 };
302 
303 enum mlx5_cmd_mode {
304 	MLX5_CMD_MODE_POLLING,
305 	MLX5_CMD_MODE_EVENTS
306 };
307 
308 struct mlx5_cmd_stats {
309 	u64		sum;
310 	u64		n;
311 	/* protect command average calculations */
312 	spinlock_t	lock;
313 };
314 
315 struct mlx5_cmd {
316 	struct mlx5_fw_page *cmd_page;
317 	bus_dma_tag_t dma_tag;
318 	struct sx dma_sx;
319 	struct mtx dma_mtx;
320 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
321 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
322 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
323 	struct cv dma_cv;
324 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
325 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
326 	void	       *cmd_buf;
327 	dma_addr_t	dma;
328 	u16		cmdif_rev;
329 	u8		log_sz;
330 	u8		log_stride;
331 	int		max_reg_cmds;
332 	int		events;
333 	u32 __iomem    *vector;
334 
335 	/* protect command queue allocations
336 	 */
337 	spinlock_t	alloc_lock;
338 
339 	/* protect token allocations
340 	 */
341 	spinlock_t	token_lock;
342 	u8		token;
343 	unsigned long	bitmask;
344 	struct semaphore sem;
345 	struct semaphore pages_sem;
346 	enum mlx5_cmd_mode mode;
347 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
348 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
349 	struct mlx5_cmd_debug dbg;
350 	struct cmd_msg_cache cache;
351 	int checksum_disabled;
352 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
353 };
354 
355 struct mlx5_port_caps {
356 	int	gid_table_len;
357 	int	pkey_table_len;
358 	u8	ext_port_cap;
359 };
360 
361 struct mlx5_buf {
362 	bus_dma_tag_t		dma_tag;
363 	bus_dmamap_t		dma_map;
364 	struct mlx5_core_dev   *dev;
365 	struct {
366 		void	       *buf;
367 	} direct;
368 	u64		       *page_list;
369 	int			npages;
370 	int			size;
371 	u8			page_shift;
372 	u8			load_done;
373 };
374 
375 struct mlx5_frag_buf {
376 	struct mlx5_buf_list	*frags;
377 	int			npages;
378 	int			size;
379 	u8			page_shift;
380 };
381 
382 struct mlx5_eq {
383 	struct mlx5_core_dev   *dev;
384 	__be32 __iomem	       *doorbell;
385 	u32			cons_index;
386 	struct mlx5_buf		buf;
387 	int			size;
388 	u8			irqn;
389 	u8			eqn;
390 	int			nent;
391 	u64			mask;
392 	struct list_head	list;
393 	int			index;
394 	struct mlx5_rsc_debug	*dbg;
395 };
396 
397 struct mlx5_core_psv {
398 	u32	psv_idx;
399 	struct psv_layout {
400 		u32	pd;
401 		u16	syndrome;
402 		u16	reserved;
403 		u16	bg;
404 		u16	app_tag;
405 		u32	ref_tag;
406 	} psv;
407 };
408 
409 struct mlx5_core_sig_ctx {
410 	struct mlx5_core_psv	psv_memory;
411 	struct mlx5_core_psv	psv_wire;
412 	struct ib_sig_err       err_item;
413 	bool			sig_status_checked;
414 	bool			sig_err_exists;
415 	u32			sigerr_count;
416 };
417 
418 enum {
419 	MLX5_MKEY_MR = 1,
420 	MLX5_MKEY_MW,
421 	MLX5_MKEY_INDIRECT_DEVX,
422 };
423 
424 struct mlx5_core_mkey {
425 	u64			iova;
426 	u64			size;
427 	u32			key;
428 	u32			pd;
429 	u32			type;
430 };
431 
432 enum mlx5_res_type {
433 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
434 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
435 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
436 	MLX5_RES_SRQ	= 3,
437 	MLX5_RES_XSRQ	= 4,
438 	MLX5_RES_XRQ	= 5,
439 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
440 };
441 
442 struct mlx5_core_rsc_common {
443 	enum mlx5_res_type	res;
444 	atomic_t		refcount;
445 	struct completion	free;
446 };
447 
448 struct mlx5_uars_page {
449 	void __iomem	       *map;
450 	bool			wc;
451 	u32			index;
452 	struct list_head	list;
453 	unsigned int		bfregs;
454 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
455 	unsigned long	       *fp_bitmap;
456 	unsigned int		reg_avail;
457 	unsigned int		fp_avail;
458 	struct kref		ref_count;
459 	struct mlx5_core_dev   *mdev;
460 };
461 
462 struct mlx5_bfreg_head {
463 	/* protect blue flame registers allocations */
464 	struct mutex		lock;
465 	struct list_head	list;
466 };
467 
468 struct mlx5_bfreg_data {
469 	struct mlx5_bfreg_head	reg_head;
470 	struct mlx5_bfreg_head	wc_head;
471 };
472 
473 struct mlx5_sq_bfreg {
474 	void __iomem	       *map;
475 	struct mlx5_uars_page  *up;
476 	bool			wc;
477 	u32			index;
478 	unsigned int		offset;
479 };
480 
481 struct mlx5_core_srq {
482 	struct mlx5_core_rsc_common	common; /* must be first */
483 	u32				srqn;
484 	int				max;
485 	size_t				max_gs;
486 	size_t				max_avail_gather;
487 	int				wqe_shift;
488 	void				(*event)(struct mlx5_core_srq *, int);
489 	atomic_t			refcount;
490 	struct completion		free;
491 };
492 
493 struct mlx5_ib_dev;
494 struct mlx5_eq_table {
495 	void __iomem	       *update_ci;
496 	void __iomem	       *update_arm_ci;
497 	struct list_head	comp_eqs_list;
498 	struct mlx5_eq		pages_eq;
499 	struct mlx5_eq		async_eq;
500 	struct mlx5_eq		cmd_eq;
501 	int			num_comp_vectors;
502 	spinlock_t		lock;	/* protect EQs list */
503 	struct mlx5_ib_dev	*dev;	/* for devx event notifier */
504 	bool (*cb)(struct mlx5_core_dev *mdev,
505 		   uint8_t event_type, void *data);
506 };
507 
508 struct mlx5_core_health {
509 	struct mlx5_health_buffer __iomem	*health;
510 	__be32 __iomem		       *health_counter;
511 	struct timer_list		timer;
512 	u32				prev;
513 	int				miss_counter;
514 	u32				fatal_error;
515 	struct workqueue_struct	       *wq_watchdog;
516 	struct work_struct		work_watchdog;
517 	/* wq spinlock to synchronize draining */
518 	spinlock_t			wq_lock;
519 	struct workqueue_struct	       *wq;
520 	unsigned long			flags;
521 	struct work_struct		work;
522 	struct delayed_work		recover_work;
523 	unsigned int			last_reset_req;
524 	struct work_struct		work_cmd_completion;
525 	struct workqueue_struct	       *wq_cmd;
526 };
527 
528 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
529 
530 struct mlx5_cq_linear_array_entry {
531 	struct mlx5_core_cq * volatile cq;
532 };
533 
534 struct mlx5_cq_table {
535 	/* protect radix tree
536 	 */
537 	spinlock_t		writerlock;
538 	atomic_t		writercount;
539 	struct radix_tree_root	tree;
540 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
541 };
542 
543 struct mlx5_qp_table {
544 	/* protect radix tree
545 	 */
546 	spinlock_t		lock;
547 	struct radix_tree_root	tree;
548 };
549 
550 struct mlx5_srq_table {
551 	/* protect radix tree
552 	 */
553 	spinlock_t		lock;
554 	struct radix_tree_root	tree;
555 };
556 
557 struct mlx5_mr_table {
558 	/* protect radix tree
559 	 */
560 	spinlock_t		lock;
561 	struct radix_tree_root	tree;
562 };
563 
564 #ifdef RATELIMIT
565 struct mlx5_rl_entry {
566 	u32			rate;
567 	u16			burst;
568 	u16			index;
569 	u32			qos_handle; /* schedule queue handle */
570 	u32			refcount;
571 };
572 
573 struct mlx5_rl_table {
574 	struct mutex		rl_lock;
575 	u16			max_size;
576 	u32			max_rate;
577 	u32			min_rate;
578 	struct mlx5_rl_entry   *rl_entry;
579 };
580 #endif
581 
582 struct mlx5_pme_stats {
583 	u64			status_counters[MLX5_MODULE_STATUS_NUM];
584 	u64			error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
585 };
586 
587 struct mlx5_priv {
588 	char			name[MLX5_MAX_NAME_LEN];
589 	struct mlx5_eq_table	eq_table;
590 	struct msix_entry	*msix_arr;
591 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
592 	int			disable_irqs;
593 
594 	/* pages stuff */
595 	struct workqueue_struct *pg_wq;
596 	struct rb_root		page_root;
597 	s64			fw_pages;
598 	atomic_t		reg_pages;
599 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
600 	struct mlx5_core_health health;
601 
602 	struct mlx5_srq_table	srq_table;
603 
604 	/* start: qp staff */
605 	struct mlx5_qp_table	qp_table;
606 
607 	/* end: qp staff */
608 
609 	/* start: cq staff */
610 	struct mlx5_cq_table	cq_table;
611 	/* end: cq staff */
612 
613 	/* start: mr staff */
614 	struct mlx5_mr_table	mr_table;
615 	/* end: mr staff */
616 
617 	/* start: alloc staff */
618 	int			numa_node;
619 
620 	struct mutex   pgdir_mutex;
621 	struct list_head        pgdir_list;
622 	/* end: alloc staff */
623 
624 	/* protect mkey key part */
625 	spinlock_t		mkey_lock;
626 	u8			mkey_key;
627 
628 	struct list_head        dev_list;
629 	struct list_head        ctx_list;
630 	spinlock_t              ctx_lock;
631 	unsigned long		pci_dev_data;
632 #ifdef RATELIMIT
633 	struct mlx5_rl_table	rl_table;
634 #endif
635 	struct mlx5_pme_stats pme_stats;
636 
637 	struct mlx5_flow_steering *steering;
638 	struct mlx5_eswitch	*eswitch;
639 
640 	struct mlx5_bfreg_data		bfregs;
641 	struct mlx5_uars_page	       *uar;
642 	struct mlx5_fc_stats		fc_stats;
643 	struct mlx5_ft_pool             *ft_pool;
644 };
645 
646 enum mlx5_device_state {
647 	MLX5_DEVICE_STATE_UP,
648 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
649 };
650 
651 enum mlx5_interface_state {
652 	MLX5_INTERFACE_STATE_UP = 0x1,
653 	MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
654 };
655 
656 enum mlx5_pci_status {
657 	MLX5_PCI_STATUS_DISABLED,
658 	MLX5_PCI_STATUS_ENABLED,
659 };
660 
661 #define	MLX5_MAX_RESERVED_GIDS	8
662 
663 struct mlx5_rsvd_gids {
664 	unsigned int start;
665 	unsigned int count;
666 	struct ida ida;
667 };
668 
669 struct mlx5_special_contexts {
670 	int resd_lkey;
671 };
672 
673 struct mlx5_diag_cnt_id {
674 	u16	id;
675 	bool	enabled;
676 };
677 
678 struct mlx5_diag_cnt {
679 #define	DIAG_LOCK(dc) mutex_lock(&(dc)->lock)
680 #define	DIAG_UNLOCK(dc) mutex_unlock(&(dc)->lock)
681 	struct mutex lock;
682 	struct sysctl_ctx_list sysctl_ctx;
683 	struct mlx5_diag_cnt_id *cnt_id;
684 	u16	num_of_samples;
685 	u16	sample_index;
686 	u8	num_cnt_id;
687 	u8	log_num_of_samples;
688 	u8	log_sample_period;
689 	u8	flag;
690 	u8	ready;
691 };
692 
693 struct mlx5_flow_root_namespace;
694 struct mlx5_core_dev {
695 	struct pci_dev	       *pdev;
696 	/* sync pci state */
697 	struct mutex		pci_status_mutex;
698 	enum mlx5_pci_status	pci_status;
699 	char			board_id[MLX5_BOARD_ID_LEN];
700 	struct mlx5_cmd		cmd;
701 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
702 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
703 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
704 	struct {
705 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
706 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
707 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
708 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
709 	} caps;
710 	phys_addr_t		iseg_base;
711 	struct mlx5_init_seg __iomem *iseg;
712 	enum mlx5_device_state	state;
713 	/* sync interface state */
714 	struct mutex		intf_state_mutex;
715 	unsigned long		intf_state;
716 	void			(*event) (struct mlx5_core_dev *dev,
717 					  enum mlx5_dev_event event,
718 					  unsigned long param);
719 	struct mlx5_priv	priv;
720 	struct mlx5_profile	*profile;
721 	atomic_t		num_qps;
722 	struct mlx5_diag_cnt	diag_cnt;
723 	u32			vsc_addr;
724 	u32			issi;
725 	struct mlx5_special_contexts special_contexts;
726 	unsigned int module_status[MLX5_MAX_PORTS];
727 	struct mlx5_flow_root_namespace *root_ns;
728 	struct mlx5_flow_root_namespace *fdb_root_ns;
729 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
730 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
731 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
732 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
733 	struct mlx5_flow_root_namespace *nic_tx_root_ns;
734 	struct mlx5_flow_root_namespace *rdma_tx_root_ns;
735 	struct mlx5_flow_root_namespace *rdma_rx_root_ns;
736 
737 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
738 	struct mlx5_crspace_regmap *dump_rege;
739 	uint32_t *dump_data;
740 	unsigned dump_size;
741 	bool dump_valid;
742 	bool dump_copyout;
743 	struct mtx dump_lock;
744 
745 	bool			iov_pf;
746 
747 	struct sysctl_ctx_list	sysctl_ctx;
748 	int			msix_eqvec;
749 	int			pwr_status;
750 	int			pwr_value;
751 
752 	struct {
753 		struct mlx5_rsvd_gids	reserved_gids;
754 		atomic_t		roce_en;
755 	} roce;
756 
757 	struct {
758 		spinlock_t	spinlock;
759 #define	MLX5_MPFS_TABLE_MAX 32
760 		long		bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
761 	} mpfs;
762 #ifdef CONFIG_MLX5_FPGA
763 	struct mlx5_fpga_device	*fpga;
764 #endif
765 	struct xarray ipsec_sadb;
766 };
767 
768 enum {
769 	MLX5_WOL_DISABLE       = 0,
770 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
771 	MLX5_WOL_MAGIC         = 1 << 2,
772 	MLX5_WOL_ARP           = 1 << 3,
773 	MLX5_WOL_BROADCAST     = 1 << 4,
774 	MLX5_WOL_MULTICAST     = 1 << 5,
775 	MLX5_WOL_UNICAST       = 1 << 6,
776 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
777 };
778 
779 struct mlx5_db {
780 	__be32			*db;
781 	union {
782 		struct mlx5_db_pgdir		*pgdir;
783 		struct mlx5_ib_user_db_page	*user_page;
784 	}			u;
785 	dma_addr_t		dma;
786 	int			index;
787 };
788 
789 struct mlx5_net_counters {
790 	u64	packets;
791 	u64	octets;
792 };
793 
794 struct mlx5_ptys_reg {
795 	u8	an_dis_admin;
796 	u8	an_dis_ap;
797 	u8	local_port;
798 	u8	proto_mask;
799 	u32	eth_proto_cap;
800 	u16	ib_link_width_cap;
801 	u16	ib_proto_cap;
802 	u32	eth_proto_admin;
803 	u16	ib_link_width_admin;
804 	u16	ib_proto_admin;
805 	u32	eth_proto_oper;
806 	u16	ib_link_width_oper;
807 	u16	ib_proto_oper;
808 	u32	eth_proto_lp_advertise;
809 };
810 
811 struct mlx5_pvlc_reg {
812 	u8	local_port;
813 	u8	vl_hw_cap;
814 	u8	vl_admin;
815 	u8	vl_operational;
816 };
817 
818 struct mlx5_pmtu_reg {
819 	u8	local_port;
820 	u16	max_mtu;
821 	u16	admin_mtu;
822 	u16	oper_mtu;
823 };
824 
825 struct mlx5_vport_counters {
826 	struct mlx5_net_counters	received_errors;
827 	struct mlx5_net_counters	transmit_errors;
828 	struct mlx5_net_counters	received_ib_unicast;
829 	struct mlx5_net_counters	transmitted_ib_unicast;
830 	struct mlx5_net_counters	received_ib_multicast;
831 	struct mlx5_net_counters	transmitted_ib_multicast;
832 	struct mlx5_net_counters	received_eth_broadcast;
833 	struct mlx5_net_counters	transmitted_eth_broadcast;
834 	struct mlx5_net_counters	received_eth_unicast;
835 	struct mlx5_net_counters	transmitted_eth_unicast;
836 	struct mlx5_net_counters	received_eth_multicast;
837 	struct mlx5_net_counters	transmitted_eth_multicast;
838 };
839 
840 enum {
841 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
842 };
843 
844 struct mlx5_core_dct {
845 	struct mlx5_core_rsc_common	common; /* must be first */
846 	void (*event)(struct mlx5_core_dct *, int);
847 	int			dctn;
848 	struct completion	drained;
849 	struct mlx5_rsc_debug	*dbg;
850 	int			pid;
851 	u16			uid;
852 };
853 
854 enum {
855 	MLX5_PTYS_IB = 1 << 0,
856 	MLX5_PTYS_EN = 1 << 2,
857 };
858 
859 struct mlx5_db_pgdir {
860 	struct list_head	list;
861 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
862 	struct mlx5_fw_page    *fw_page;
863 	__be32		       *db_page;
864 	dma_addr_t		db_dma;
865 };
866 
867 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
868 
869 struct mlx5_cmd_work_ent {
870 	struct mlx5_cmd_msg    *in;
871 	struct mlx5_cmd_msg    *out;
872 	int			uin_size;
873 	void		       *uout;
874 	int			uout_size;
875 	mlx5_cmd_cbk_t		callback;
876         struct delayed_work     cb_timeout_work;
877 	void		       *context;
878 	int			idx;
879 	struct completion	done;
880 	struct mlx5_cmd        *cmd;
881 	struct work_struct	work;
882 	struct mlx5_cmd_layout *lay;
883 	int			ret;
884 	int			page_queue;
885 	u8			status;
886 	u8			token;
887 	u64			ts1;
888 	u64			ts2;
889 	u16			op;
890 	u8			busy;
891 	bool			polling;
892 };
893 
894 struct mlx5_pas {
895 	u64	pa;
896 	u8	log_sz;
897 };
898 
899 enum port_state_policy {
900 	MLX5_POLICY_DOWN        = 0,
901 	MLX5_POLICY_UP          = 1,
902 	MLX5_POLICY_FOLLOW      = 2,
903 	MLX5_POLICY_INVALID     = 0xffffffff
904 };
905 
906 static inline void *
907 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
908 {
909 	return ((char *)buf->direct.buf + offset);
910 }
911 
912 
913 extern struct workqueue_struct *mlx5_core_wq;
914 
915 #define STRUCT_FIELD(header, field) \
916 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
917 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
918 
919 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
920 {
921 	return pci_get_drvdata(pdev);
922 }
923 
924 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
925 {
926 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
927 }
928 
929 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
930 {
931 	return ioread32be(&dev->iseg->fw_rev) >> 16;
932 }
933 
934 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
935 {
936 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
937 }
938 
939 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
940 {
941 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
942 }
943 
944 static inline int mlx5_get_gid_table_len(u16 param)
945 {
946 	if (param > 4) {
947 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
948 		return 0;
949 	}
950 
951 	return 8 * (1 << param);
952 }
953 
954 static inline void *mlx5_vzalloc(unsigned long size)
955 {
956 	void *rtn;
957 
958 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
959 	return rtn;
960 }
961 
962 static inline void *mlx5_vmalloc(unsigned long size)
963 {
964 	void *rtn;
965 
966 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
967 	if (!rtn)
968 		rtn = vmalloc(size);
969 	return rtn;
970 }
971 
972 static inline u32 mlx5_base_mkey(const u32 key)
973 {
974 	return key & 0xffffff00u;
975 }
976 
977 int mlx5_cmd_init(struct mlx5_core_dev *dev);
978 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
979 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
980 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
981 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
982 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
983 
984 struct mlx5_async_ctx {
985 	struct mlx5_core_dev *dev;
986 	atomic_t num_inflight;
987 	struct wait_queue_head wait;
988 };
989 
990 struct mlx5_async_work;
991 
992 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
993 
994 struct mlx5_async_work {
995 	struct mlx5_async_ctx *ctx;
996 	mlx5_async_cbk_t user_callback;
997 };
998 
999 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1000 			     struct mlx5_async_ctx *ctx);
1001 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
1002 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1003 		     void *out, int out_size, mlx5_async_cbk_t callback,
1004 		     struct mlx5_async_work *work);
1005 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1006 		  int out_size);
1007 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1008 	({                                                                     \
1009 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1010 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1011 	})
1012 
1013 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1014 	({                                                                     \
1015 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1016 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1017 	})
1018 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1019 			  void *out, int out_size);
1020 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1021 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1022 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1023 		     bool map_wc, bool fast_path);
1024 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1025 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1026 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1027 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1028 int mlx5_health_init(struct mlx5_core_dev *dev);
1029 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1030 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1031 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1032 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1033 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1034 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
1035 
1036 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
1037 		   struct mlx5_buf *buf);
1038 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
1039 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1040 			 struct mlx5_srq_attr *in);
1041 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1042 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1043 			struct mlx5_srq_attr *out);
1044 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1045 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1046 		      u16 lwm, int is_srq);
1047 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
1048 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
1049 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1050 			     struct mlx5_core_mkey *mkey,
1051 			     struct mlx5_async_ctx *async_ctx, u32 *in,
1052 			     int inlen, u32 *out, int outlen,
1053 			     mlx5_async_cbk_t callback,
1054 			     struct mlx5_async_work *context);
1055 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1056 			  struct mlx5_core_mkey *mr,
1057 			  u32 *in, int inlen);
1058 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey);
1059 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1060 			 u32 *out, int outlen);
1061 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mr,
1062 			     u32 *mkey);
1063 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn, u16 uid);
1064 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid);
1065 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1066 		      u16 opmod, u8 port);
1067 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1068 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1069 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1070 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1071 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1072 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1073 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1074 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1075 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1076 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1077 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1078 				 s32 npages);
1079 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1080 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1081 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1082 void mlx5_register_debugfs(void);
1083 void mlx5_unregister_debugfs(void);
1084 int mlx5_eq_init(struct mlx5_core_dev *dev);
1085 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1086 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1087 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1088 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1089 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1090 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1091 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1092 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1093 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1094 		       int nent, u64 mask);
1095 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1096 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1097 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1098 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1099 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1100 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1101 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1102 				u64 addr);
1103 
1104 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1105 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1106 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1107 			 int size_in, void *data_out, int size_out,
1108 			 u16 reg_num, int arg, int write);
1109 
1110 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1111 
1112 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1113 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1114 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1115 		       u32 *out, int outlen);
1116 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1117 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1118 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1119 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1120 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1121 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1122 
1123 static inline struct domainset *
1124 mlx5_dev_domainset(struct mlx5_core_dev *mdev)
1125 {
1126 	return (linux_get_vm_domain_set(mdev->priv.numa_node));
1127 }
1128 
1129 const char *mlx5_command_str(int command);
1130 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1131 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1132 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1133 			 int npsvs, u32 *sig_index);
1134 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1135 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1136 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1137 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1138 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1139 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1140 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1141 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1142 			  struct mlx5_pvlc_reg *pvlc, int write);
1143 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1144 			  struct mlx5_ptys_reg *ptys, int write);
1145 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1146 			  struct mlx5_pmtu_reg *pmtu, int write);
1147 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1148 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1149 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1150 				int priority, int *is_enable);
1151 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1152 				 int priority, int enable);
1153 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1154 				void *out, int out_size);
1155 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1156 				 void *in, int in_size);
1157 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1158 				    void *out, int out_size);
1159 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1160 			       int in_size);
1161 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1162 				   u8 num_of_samples, u16 sample_index,
1163 				   void *out, int out_size);
1164 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1165 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1166 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1167 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1168 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1169 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1170 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1171 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1172 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1173 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1174 			       u16 *p_power, u8 *p_status);
1175 
1176 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1177 {
1178 	return mkey >> 8;
1179 }
1180 
1181 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1182 {
1183 	return mkey_idx << 8;
1184 }
1185 
1186 static inline u8 mlx5_mkey_variant(u32 mkey)
1187 {
1188 	return mkey & 0xff;
1189 }
1190 
1191 enum {
1192 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1193 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1194 };
1195 
1196 enum {
1197 	MAX_MR_CACHE_ENTRIES    = 15,
1198 };
1199 
1200 struct mlx5_interface {
1201 	void *			(*add)(struct mlx5_core_dev *dev);
1202 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1203 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1204 					 enum mlx5_dev_event event, unsigned long param);
1205 	void *                  (*get_dev)(void *context);
1206 	int			protocol;
1207 	struct list_head	list;
1208 };
1209 
1210 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1211 int mlx5_register_interface(struct mlx5_interface *intf);
1212 void mlx5_unregister_interface(struct mlx5_interface *intf);
1213 
1214 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1215 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1216     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1217     const u8 *mac, bool vlan, u16 vlan_id);
1218 
1219 struct mlx5_profile {
1220 	u64	mask;
1221 	u8	log_max_qp;
1222 	struct {
1223 		int	size;
1224 		int	limit;
1225 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1226 };
1227 
1228 enum {
1229 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1230 };
1231 
1232 enum {
1233 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1234 };
1235 
1236 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1237 {
1238 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1239 }
1240 #ifdef RATELIMIT
1241 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1242 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1243 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1244 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1245 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1246 int mlx5e_query_rate_limit_cmd(struct mlx5_core_dev *dev, u16 index, u32 *scq_handle);
1247 
1248 static inline u32 mlx5_rl_get_scq_handle(struct mlx5_core_dev *dev, uint16_t index)
1249 {
1250 	KASSERT(index > 0,
1251 	    ("invalid rate index for sq remap, failed retrieving SCQ handle"));
1252 
1253         return (dev->priv.rl_table.rl_entry[index - 1].qos_handle);
1254 }
1255 
1256 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1257 {
1258 	return !!(dev->priv.rl_table.max_size);
1259 }
1260 #endif
1261 
1262 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1263 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1264 
1265 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
1266 {
1267         return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
1268                        MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
1269                        MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
1270 }
1271 
1272 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev)
1273 {
1274         return !MLX5_CAP_GEN(dev, rq_ts_format) ?
1275                        MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1276                        MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
1277 }
1278 
1279 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev)
1280 {
1281         return !MLX5_CAP_GEN(dev, sq_ts_format) ?
1282                        MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1283                        MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
1284 }
1285 
1286 #endif /* MLX5_DRIVER_H */
1287