xref: /freebsd/sys/dev/mlx5/driver.h (revision e9dcd83155b39327497e7a2577d8990074144ff3) 
1 /*-
2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 enum {
53 	MLX5_BOARD_ID_LEN = 64,
54 	MLX5_MAX_NAME_LEN = 16,
55 };
56 
57 enum {
58 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
59 	MLX5_CMD_WQ_MAX_NAME	= 32,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_MAX_IRQ_NAME	= 32
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFF		= 16,
93 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
98 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
99 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
100 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
101 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
102 };
103 
104 enum {
105 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
106 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
111 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
112 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
113 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
114 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
115 };
116 
117 enum {
118 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
119 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
120 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
121 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
122 };
123 
124 enum {
125 	MLX5_REG_QPTS		 = 0x4002,
126 	MLX5_REG_QETCR		 = 0x4005,
127 	MLX5_REG_QPDP		 = 0x4007,
128 	MLX5_REG_QTCT		 = 0x400A,
129 	MLX5_REG_QPDPM		 = 0x4013,
130 	MLX5_REG_QHLL		 = 0x4016,
131 	MLX5_REG_QCAM		 = 0x4019,
132 	MLX5_REG_DCBX_PARAM	 = 0x4020,
133 	MLX5_REG_DCBX_APP	 = 0x4021,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_FPGA_CAP	 = 0x4022,
136 	MLX5_REG_FPGA_CTRL	 = 0x4023,
137 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
138 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
139 	MLX5_REG_PMTU		 = 0x5003,
140 	MLX5_REG_PTYS		 = 0x5004,
141 	MLX5_REG_PAOS		 = 0x5006,
142 	MLX5_REG_PFCC		 = 0x5007,
143 	MLX5_REG_PPCNT		 = 0x5008,
144 	MLX5_REG_PMAOS		 = 0x5012,
145 	MLX5_REG_PUDE		 = 0x5009,
146 	MLX5_REG_PPTB		 = 0x500B,
147 	MLX5_REG_PBMC		 = 0x500C,
148 	MLX5_REG_PMPE		 = 0x5010,
149 	MLX5_REG_PELC		 = 0x500e,
150 	MLX5_REG_PVLC		 = 0x500f,
151 	MLX5_REG_PMLP		 = 0x5002,
152 	MLX5_REG_NODE_DESC	 = 0x6001,
153 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
154 	MLX5_REG_MCIA		 = 0x9014,
155 	MLX5_REG_MPCNT		 = 0x9051,
156 };
157 
158 enum dbg_rsc_type {
159 	MLX5_DBG_RSC_QP,
160 	MLX5_DBG_RSC_EQ,
161 	MLX5_DBG_RSC_CQ,
162 };
163 
164 enum {
165 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
166 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
167 	MLX5_INTERFACE_NUMBER       = 2,
168 };
169 
170 struct mlx5_field_desc {
171 	struct dentry	       *dent;
172 	int			i;
173 };
174 
175 struct mlx5_rsc_debug {
176 	struct mlx5_core_dev   *dev;
177 	void		       *object;
178 	enum dbg_rsc_type	type;
179 	struct dentry	       *root;
180 	struct mlx5_field_desc	fields[0];
181 };
182 
183 enum mlx5_dev_event {
184 	MLX5_DEV_EVENT_SYS_ERROR,
185 	MLX5_DEV_EVENT_PORT_UP,
186 	MLX5_DEV_EVENT_PORT_DOWN,
187 	MLX5_DEV_EVENT_PORT_INITIALIZED,
188 	MLX5_DEV_EVENT_LID_CHANGE,
189 	MLX5_DEV_EVENT_PKEY_CHANGE,
190 	MLX5_DEV_EVENT_GUID_CHANGE,
191 	MLX5_DEV_EVENT_CLIENT_REREG,
192 	MLX5_DEV_EVENT_VPORT_CHANGE,
193 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
194 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
195 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
196 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
197 };
198 
199 enum mlx5_port_status {
200 	MLX5_PORT_UP        = 1 << 0,
201 	MLX5_PORT_DOWN      = 1 << 1,
202 };
203 
204 enum mlx5_link_mode {
205 	MLX5_1000BASE_CX_SGMII	= 0,
206 	MLX5_1000BASE_KX	= 1,
207 	MLX5_10GBASE_CX4	= 2,
208 	MLX5_10GBASE_KX4	= 3,
209 	MLX5_10GBASE_KR		= 4,
210 	MLX5_20GBASE_KR2	= 5,
211 	MLX5_40GBASE_CR4	= 6,
212 	MLX5_40GBASE_KR4	= 7,
213 	MLX5_56GBASE_R4		= 8,
214 	MLX5_10GBASE_CR		= 12,
215 	MLX5_10GBASE_SR		= 13,
216 	MLX5_10GBASE_ER		= 14,
217 	MLX5_40GBASE_SR4	= 15,
218 	MLX5_40GBASE_LR4	= 16,
219 	MLX5_100GBASE_CR4	= 20,
220 	MLX5_100GBASE_SR4	= 21,
221 	MLX5_100GBASE_KR4	= 22,
222 	MLX5_100GBASE_LR4	= 23,
223 	MLX5_100BASE_TX		= 24,
224 	MLX5_1000BASE_T		= 25,
225 	MLX5_10GBASE_T		= 26,
226 	MLX5_25GBASE_CR		= 27,
227 	MLX5_25GBASE_KR		= 28,
228 	MLX5_25GBASE_SR		= 29,
229 	MLX5_50GBASE_CR2	= 30,
230 	MLX5_50GBASE_KR2	= 31,
231 	MLX5_LINK_MODES_NUMBER,
232 };
233 
234 enum {
235 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
236 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
237 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
238 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
239 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
240 	MLX5_VSC_DATA_OFFSET	 = 0x14,
241 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
242 };
243 
244 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
245 
246 struct mlx5_uuar_info {
247 	struct mlx5_uar	       *uars;
248 	int			num_uars;
249 	int			num_low_latency_uuars;
250 	unsigned long	       *bitmap;
251 	unsigned int	       *count;
252 	struct mlx5_bf	       *bfs;
253 
254 	/*
255 	 * protect uuar allocation data structs
256 	 */
257 	struct mutex		lock;
258 	u32			ver;
259 };
260 
261 struct mlx5_bf {
262 	void __iomem	       *reg;
263 	void __iomem	       *regreg;
264 	int			buf_size;
265 	struct mlx5_uar	       *uar;
266 	unsigned long		offset;
267 	int			need_lock;
268 	/* protect blue flame buffer selection when needed
269 	 */
270 	spinlock_t		lock;
271 
272 	/* serialize 64 bit writes when done as two 32 bit accesses
273 	 */
274 	spinlock_t		lock32;
275 	int			uuarn;
276 };
277 
278 struct mlx5_cmd_first {
279 	__be32		data[4];
280 };
281 
282 struct cache_ent;
283 struct mlx5_fw_page {
284 	union {
285 		struct rb_node rb_node;
286 		struct list_head list;
287 	};
288 	struct mlx5_cmd_first first;
289 	struct mlx5_core_dev *dev;
290 	bus_dmamap_t dma_map;
291 	bus_addr_t dma_addr;
292 	void *virt_addr;
293 	struct cache_ent *cache;
294 	u32 numpages;
295 	u16 load_done;
296 #define	MLX5_LOAD_ST_NONE 0
297 #define	MLX5_LOAD_ST_SUCCESS 1
298 #define	MLX5_LOAD_ST_FAILURE 2
299 	u16 func_id;
300 };
301 #define	mlx5_cmd_msg mlx5_fw_page
302 
303 struct mlx5_cmd_debug {
304 	struct dentry	       *dbg_root;
305 	struct dentry	       *dbg_in;
306 	struct dentry	       *dbg_out;
307 	struct dentry	       *dbg_outlen;
308 	struct dentry	       *dbg_status;
309 	struct dentry	       *dbg_run;
310 	void		       *in_msg;
311 	void		       *out_msg;
312 	u8			status;
313 	u16			inlen;
314 	u16			outlen;
315 };
316 
317 struct cache_ent {
318 	/* protect block chain allocations
319 	 */
320 	spinlock_t		lock;
321 	struct list_head	head;
322 };
323 
324 struct cmd_msg_cache {
325 	struct cache_ent	large;
326 	struct cache_ent	med;
327 
328 };
329 
330 struct mlx5_traffic_counter {
331 	u64         packets;
332 	u64         octets;
333 };
334 
335 enum mlx5_cmd_mode {
336 	MLX5_CMD_MODE_POLLING,
337 	MLX5_CMD_MODE_EVENTS
338 };
339 
340 struct mlx5_cmd_stats {
341 	u64		sum;
342 	u64		n;
343 	struct dentry  *root;
344 	struct dentry  *avg;
345 	struct dentry  *count;
346 	/* protect command average calculations */
347 	spinlock_t	lock;
348 };
349 
350 struct mlx5_cmd {
351 	struct mlx5_fw_page *cmd_page;
352 	bus_dma_tag_t dma_tag;
353 	struct sx dma_sx;
354 	struct mtx dma_mtx;
355 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
356 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
357 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
358 	struct cv dma_cv;
359 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
360 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
361 	void	       *cmd_buf;
362 	dma_addr_t	dma;
363 	u16		cmdif_rev;
364 	u8		log_sz;
365 	u8		log_stride;
366 	int		max_reg_cmds;
367 	int		events;
368 	u32 __iomem    *vector;
369 
370 	/* protect command queue allocations
371 	 */
372 	spinlock_t	alloc_lock;
373 
374 	/* protect token allocations
375 	 */
376 	spinlock_t	token_lock;
377 	u8		token;
378 	unsigned long	bitmask;
379 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
380 	struct workqueue_struct *wq;
381 	struct semaphore sem;
382 	struct semaphore pages_sem;
383 	enum mlx5_cmd_mode mode;
384 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
385 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
386 	struct mlx5_cmd_debug dbg;
387 	struct cmd_msg_cache cache;
388 	int checksum_disabled;
389 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
390 };
391 
392 struct mlx5_port_caps {
393 	int	gid_table_len;
394 	int	pkey_table_len;
395 	u8	ext_port_cap;
396 };
397 
398 struct mlx5_buf {
399 	bus_dma_tag_t		dma_tag;
400 	bus_dmamap_t		dma_map;
401 	struct mlx5_core_dev   *dev;
402 	struct {
403 		void	       *buf;
404 	} direct;
405 	u64		       *page_list;
406 	int			npages;
407 	int			size;
408 	u8			page_shift;
409 	u8			load_done;
410 };
411 
412 struct mlx5_frag_buf {
413 	struct mlx5_buf_list	*frags;
414 	int			npages;
415 	int			size;
416 	u8			page_shift;
417 };
418 
419 struct mlx5_eq {
420 	struct mlx5_core_dev   *dev;
421 	__be32 __iomem	       *doorbell;
422 	u32			cons_index;
423 	struct mlx5_buf		buf;
424 	int			size;
425 	u8			irqn;
426 	u8			eqn;
427 	int			nent;
428 	u64			mask;
429 	struct list_head	list;
430 	int			index;
431 	struct mlx5_rsc_debug	*dbg;
432 };
433 
434 struct mlx5_core_psv {
435 	u32	psv_idx;
436 	struct psv_layout {
437 		u32	pd;
438 		u16	syndrome;
439 		u16	reserved;
440 		u16	bg;
441 		u16	app_tag;
442 		u32	ref_tag;
443 	} psv;
444 };
445 
446 struct mlx5_core_sig_ctx {
447 	struct mlx5_core_psv	psv_memory;
448 	struct mlx5_core_psv	psv_wire;
449 #if (__FreeBSD_version >= 1100000)
450 	struct ib_sig_err       err_item;
451 #endif
452 	bool			sig_status_checked;
453 	bool			sig_err_exists;
454 	u32			sigerr_count;
455 };
456 
457 enum {
458 	MLX5_MKEY_MR = 1,
459 	MLX5_MKEY_MW,
460 	MLX5_MKEY_MR_USER,
461 };
462 
463 struct mlx5_core_mkey {
464 	u64			iova;
465 	u64			size;
466 	u32			key;
467 	u32			pd;
468 	u32			type;
469 };
470 
471 struct mlx5_core_mr {
472 	u64			iova;
473 	u64			size;
474 	u32			key;
475 	u32			pd;
476 };
477 
478 enum mlx5_res_type {
479 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
480 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
481 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
482 	MLX5_RES_SRQ	= 3,
483 	MLX5_RES_XSRQ	= 4,
484 	MLX5_RES_DCT	= 5,
485 };
486 
487 struct mlx5_core_rsc_common {
488 	enum mlx5_res_type	res;
489 	atomic_t		refcount;
490 	struct completion	free;
491 };
492 
493 struct mlx5_core_srq {
494 	struct mlx5_core_rsc_common	common; /* must be first */
495 	u32				srqn;
496 	int				max;
497 	size_t				max_gs;
498 	size_t				max_avail_gather;
499 	int				wqe_shift;
500 	void				(*event)(struct mlx5_core_srq *, int);
501 	atomic_t			refcount;
502 	struct completion		free;
503 };
504 
505 struct mlx5_eq_table {
506 	void __iomem	       *update_ci;
507 	void __iomem	       *update_arm_ci;
508 	struct list_head	comp_eqs_list;
509 	struct mlx5_eq		pages_eq;
510 	struct mlx5_eq		async_eq;
511 	struct mlx5_eq		cmd_eq;
512 	int			num_comp_vectors;
513 	/* protect EQs list
514 	 */
515 	spinlock_t		lock;
516 };
517 
518 struct mlx5_uar {
519 	u32			index;
520 	void __iomem	       *bf_map;
521 	void __iomem	       *map;
522 };
523 
524 
525 struct mlx5_core_health {
526 	struct mlx5_health_buffer __iomem	*health;
527 	__be32 __iomem		       *health_counter;
528 	struct timer_list		timer;
529 	u32				prev;
530 	int				miss_counter;
531 	u32				fatal_error;
532 	/* wq spinlock to synchronize draining */
533 	spinlock_t			wq_lock;
534 	struct workqueue_struct	       *wq;
535 	unsigned long			flags;
536 	struct work_struct		work;
537 	struct delayed_work		recover_work;
538 };
539 
540 #ifdef RATELIMIT
541 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	(128 * 1024)
542 #else
543 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
544 #endif
545 
546 struct mlx5_cq_linear_array_entry {
547 	spinlock_t	lock;
548 	struct mlx5_core_cq * volatile cq;
549 };
550 
551 struct mlx5_cq_table {
552 	/* protect radix tree
553 	 */
554 	spinlock_t		lock;
555 	struct radix_tree_root	tree;
556 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
557 };
558 
559 struct mlx5_qp_table {
560 	/* protect radix tree
561 	 */
562 	spinlock_t		lock;
563 	struct radix_tree_root	tree;
564 };
565 
566 struct mlx5_srq_table {
567 	/* protect radix tree
568 	 */
569 	spinlock_t		lock;
570 	struct radix_tree_root	tree;
571 };
572 
573 struct mlx5_mr_table {
574 	/* protect radix tree
575 	 */
576 	spinlock_t		lock;
577 	struct radix_tree_root	tree;
578 };
579 
580 struct mlx5_irq_info {
581 	char name[MLX5_MAX_IRQ_NAME];
582 };
583 
584 #ifdef RATELIMIT
585 struct mlx5_rl_entry {
586 	u32			rate;
587 	u16			burst;
588 	u16			index;
589 	u32			refcount;
590 };
591 
592 struct mlx5_rl_table {
593 	struct mutex		rl_lock;
594 	u16			max_size;
595 	u32			max_rate;
596 	u32			min_rate;
597 	struct mlx5_rl_entry   *rl_entry;
598 };
599 #endif
600 
601 struct mlx5_priv {
602 	char			name[MLX5_MAX_NAME_LEN];
603 	struct mlx5_eq_table	eq_table;
604 	struct msix_entry	*msix_arr;
605 	struct mlx5_irq_info	*irq_info;
606 	struct mlx5_uuar_info	uuari;
607 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
608 
609 	struct io_mapping	*bf_mapping;
610 
611 	/* pages stuff */
612 	struct workqueue_struct *pg_wq;
613 	struct rb_root		page_root;
614 	s64			fw_pages;
615 	atomic_t		reg_pages;
616 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
617 	struct mlx5_core_health health;
618 
619 	struct mlx5_srq_table	srq_table;
620 
621 	/* start: qp staff */
622 	struct mlx5_qp_table	qp_table;
623 	struct dentry	       *qp_debugfs;
624 	struct dentry	       *eq_debugfs;
625 	struct dentry	       *cq_debugfs;
626 	struct dentry	       *cmdif_debugfs;
627 	/* end: qp staff */
628 
629 	/* start: cq staff */
630 	struct mlx5_cq_table	cq_table;
631 	/* end: cq staff */
632 
633 	/* start: mr staff */
634 	struct mlx5_mr_table	mr_table;
635 	/* end: mr staff */
636 
637 	/* start: alloc staff */
638 	int			numa_node;
639 
640 	struct mutex   pgdir_mutex;
641 	struct list_head        pgdir_list;
642 	/* end: alloc staff */
643 	struct dentry	       *dbg_root;
644 
645 	/* protect mkey key part */
646 	spinlock_t		mkey_lock;
647 	u8			mkey_key;
648 
649 	struct list_head        dev_list;
650 	struct list_head        ctx_list;
651 	spinlock_t              ctx_lock;
652 	unsigned long		pci_dev_data;
653 #ifdef RATELIMIT
654 	struct mlx5_rl_table	rl_table;
655 #endif
656 };
657 
658 enum mlx5_device_state {
659 	MLX5_DEVICE_STATE_UP,
660 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
661 };
662 
663 enum mlx5_interface_state {
664 	MLX5_INTERFACE_STATE_DOWN = BIT(0),
665 	MLX5_INTERFACE_STATE_UP = BIT(1),
666 	MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
667 };
668 
669 enum mlx5_pci_status {
670 	MLX5_PCI_STATUS_DISABLED,
671 	MLX5_PCI_STATUS_ENABLED,
672 };
673 
674 #define	MLX5_MAX_RESERVED_GIDS	8
675 
676 struct mlx5_rsvd_gids {
677 	unsigned int start;
678 	unsigned int count;
679 	struct ida ida;
680 };
681 
682 struct mlx5_special_contexts {
683 	int resd_lkey;
684 };
685 
686 struct mlx5_flow_root_namespace;
687 struct mlx5_dump_data;
688 struct mlx5_core_dev {
689 	struct pci_dev	       *pdev;
690 	/* sync pci state */
691 	struct mutex		pci_status_mutex;
692 	enum mlx5_pci_status	pci_status;
693 	char			board_id[MLX5_BOARD_ID_LEN];
694 	struct mlx5_cmd		cmd;
695 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
696 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
697 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
698 	struct {
699 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
700 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
701 	} caps;
702 	phys_addr_t		iseg_base;
703 	struct mlx5_init_seg __iomem *iseg;
704 	enum mlx5_device_state	state;
705 	/* sync interface state */
706 	struct mutex		intf_state_mutex;
707 	unsigned long		intf_state;
708 	void			(*event) (struct mlx5_core_dev *dev,
709 					  enum mlx5_dev_event event,
710 					  unsigned long param);
711 	struct mlx5_priv	priv;
712 	struct mlx5_profile	*profile;
713 	atomic_t		num_qps;
714 	u32			vsc_addr;
715 	u32			issi;
716 	struct mlx5_special_contexts special_contexts;
717 	unsigned int module_status[MLX5_MAX_PORTS];
718 	struct mlx5_flow_root_namespace *root_ns;
719 	struct mlx5_flow_root_namespace *fdb_root_ns;
720 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
721 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
722 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
723 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
724 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
725 	struct mlx5_dump_data	*dump_data;
726 
727 	struct sysctl_ctx_list	sysctl_ctx;
728 	int			msix_eqvec;
729 
730 	struct {
731 		struct mlx5_rsvd_gids	reserved_gids;
732 		atomic_t		roce_en;
733 	} roce;
734 #ifdef CONFIG_MLX5_FPGA
735 	struct mlx5_fpga_device	*fpga;
736 #endif
737 };
738 
739 enum {
740 	MLX5_WOL_DISABLE       = 0,
741 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
742 	MLX5_WOL_MAGIC         = 1 << 2,
743 	MLX5_WOL_ARP           = 1 << 3,
744 	MLX5_WOL_BROADCAST     = 1 << 4,
745 	MLX5_WOL_MULTICAST     = 1 << 5,
746 	MLX5_WOL_UNICAST       = 1 << 6,
747 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
748 };
749 
750 struct mlx5_db {
751 	__be32			*db;
752 	union {
753 		struct mlx5_db_pgdir		*pgdir;
754 		struct mlx5_ib_user_db_page	*user_page;
755 	}			u;
756 	dma_addr_t		dma;
757 	int			index;
758 };
759 
760 struct mlx5_net_counters {
761 	u64	packets;
762 	u64	octets;
763 };
764 
765 struct mlx5_ptys_reg {
766 	u8	an_dis_admin;
767 	u8	an_dis_ap;
768 	u8	local_port;
769 	u8	proto_mask;
770 	u32	eth_proto_cap;
771 	u16	ib_link_width_cap;
772 	u16	ib_proto_cap;
773 	u32	eth_proto_admin;
774 	u16	ib_link_width_admin;
775 	u16	ib_proto_admin;
776 	u32	eth_proto_oper;
777 	u16	ib_link_width_oper;
778 	u16	ib_proto_oper;
779 	u32	eth_proto_lp_advertise;
780 };
781 
782 struct mlx5_pvlc_reg {
783 	u8	local_port;
784 	u8	vl_hw_cap;
785 	u8	vl_admin;
786 	u8	vl_operational;
787 };
788 
789 struct mlx5_pmtu_reg {
790 	u8	local_port;
791 	u16	max_mtu;
792 	u16	admin_mtu;
793 	u16	oper_mtu;
794 };
795 
796 struct mlx5_vport_counters {
797 	struct mlx5_net_counters	received_errors;
798 	struct mlx5_net_counters	transmit_errors;
799 	struct mlx5_net_counters	received_ib_unicast;
800 	struct mlx5_net_counters	transmitted_ib_unicast;
801 	struct mlx5_net_counters	received_ib_multicast;
802 	struct mlx5_net_counters	transmitted_ib_multicast;
803 	struct mlx5_net_counters	received_eth_broadcast;
804 	struct mlx5_net_counters	transmitted_eth_broadcast;
805 	struct mlx5_net_counters	received_eth_unicast;
806 	struct mlx5_net_counters	transmitted_eth_unicast;
807 	struct mlx5_net_counters	received_eth_multicast;
808 	struct mlx5_net_counters	transmitted_eth_multicast;
809 };
810 
811 enum {
812 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
813 };
814 
815 struct mlx5_core_dct {
816 	struct mlx5_core_rsc_common	common; /* must be first */
817 	void (*event)(struct mlx5_core_dct *, int);
818 	int			dctn;
819 	struct completion	drained;
820 	struct mlx5_rsc_debug	*dbg;
821 	int			pid;
822 };
823 
824 enum {
825 	MLX5_COMP_EQ_SIZE = 1024,
826 };
827 
828 enum {
829 	MLX5_PTYS_IB = 1 << 0,
830 	MLX5_PTYS_EN = 1 << 2,
831 };
832 
833 struct mlx5_db_pgdir {
834 	struct list_head	list;
835 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
836 	struct mlx5_fw_page    *fw_page;
837 	__be32		       *db_page;
838 	dma_addr_t		db_dma;
839 };
840 
841 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
842 
843 struct mlx5_cmd_work_ent {
844 	struct mlx5_cmd_msg    *in;
845 	struct mlx5_cmd_msg    *out;
846 	int			uin_size;
847 	void		       *uout;
848 	int			uout_size;
849 	mlx5_cmd_cbk_t		callback;
850         struct delayed_work     cb_timeout_work;
851 	void		       *context;
852 	int			idx;
853 	struct completion	done;
854 	struct mlx5_cmd        *cmd;
855 	struct work_struct	work;
856 	struct mlx5_cmd_layout *lay;
857 	int			ret;
858 	int			page_queue;
859 	u8			status;
860 	u8			token;
861 	u64			ts1;
862 	u64			ts2;
863 	u16			op;
864 	u8			busy;
865 	bool			polling;
866 };
867 
868 struct mlx5_pas {
869 	u64	pa;
870 	u8	log_sz;
871 };
872 
873 enum port_state_policy {
874 	MLX5_POLICY_DOWN        = 0,
875 	MLX5_POLICY_UP          = 1,
876 	MLX5_POLICY_FOLLOW      = 2,
877 	MLX5_POLICY_INVALID     = 0xffffffff
878 };
879 
880 static inline void *
881 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
882 {
883 	return ((char *)buf->direct.buf + offset);
884 }
885 
886 
887 extern struct workqueue_struct *mlx5_core_wq;
888 
889 #define STRUCT_FIELD(header, field) \
890 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
891 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
892 
893 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
894 {
895 	return pci_get_drvdata(pdev);
896 }
897 
898 extern struct dentry *mlx5_debugfs_root;
899 
900 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
901 {
902 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
903 }
904 
905 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
906 {
907 	return ioread32be(&dev->iseg->fw_rev) >> 16;
908 }
909 
910 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
911 {
912 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
913 }
914 
915 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
916 {
917 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
918 }
919 
920 static inline int mlx5_get_gid_table_len(u16 param)
921 {
922 	if (param > 4) {
923 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
924 		return 0;
925 	}
926 
927 	return 8 * (1 << param);
928 }
929 
930 static inline void *mlx5_vzalloc(unsigned long size)
931 {
932 	void *rtn;
933 
934 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
935 	return rtn;
936 }
937 
938 static inline void *mlx5_vmalloc(unsigned long size)
939 {
940 	void *rtn;
941 
942 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
943 	if (!rtn)
944 		rtn = vmalloc(size);
945 	return rtn;
946 }
947 
948 static inline u32 mlx5_base_mkey(const u32 key)
949 {
950 	return key & 0xffffff00u;
951 }
952 
953 int mlx5_cmd_init(struct mlx5_core_dev *dev);
954 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
955 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
956 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
957 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
958 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
959 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
960 		  int out_size);
961 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
962 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
963 		     void *context);
964 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
965 			  void *out, int out_size);
966 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
967 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
968 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
969 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
970 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
971 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
972 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
973 int mlx5_health_init(struct mlx5_core_dev *dev);
974 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
975 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
976 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
977 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
978 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
979 
980 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
981 	mlx5_buf_alloc(dev, size, direct, buf)
982 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
983 		   struct mlx5_buf *buf);
984 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
985 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
986 			 struct mlx5_srq_attr *in);
987 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
988 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
989 			struct mlx5_srq_attr *out);
990 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
991 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
992 		      u16 lwm, int is_srq);
993 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
994 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
995 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
996 			     struct mlx5_core_mr *mkey,
997 			     u32 *in, int inlen,
998 			     u32 *out, int outlen,
999 			     mlx5_cmd_cbk_t callback, void *context);
1000 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1001 			  struct mlx5_core_mr *mr,
1002 			  u32 *in, int inlen);
1003 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
1004 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
1005 			 u32 *out, int outlen);
1006 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
1007 			     u32 *mkey);
1008 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1009 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1010 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1011 		      u16 opmod, u8 port);
1012 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1013 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1014 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1015 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1016 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1017 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1018 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1019 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1020 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1021 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1022 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1023 				 s32 npages);
1024 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1025 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1026 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1027 void mlx5_register_debugfs(void);
1028 void mlx5_unregister_debugfs(void);
1029 int mlx5_eq_init(struct mlx5_core_dev *dev);
1030 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1031 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1032 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1033 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1034 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1035 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1036 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1037 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1038 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1039 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
1040 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1041 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1042 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1043 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1044 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1045 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1046 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1047 				u64 addr);
1048 
1049 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1050 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1051 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1052 			 int size_in, void *data_out, int size_out,
1053 			 u16 reg_num, int arg, int write);
1054 
1055 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1056 
1057 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1058 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1059 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1060 		       u32 *out, int outlen);
1061 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1062 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1063 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1064 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1065 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1066 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1067 		       int node);
1068 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1069 
1070 const char *mlx5_command_str(int command);
1071 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1072 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1073 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1074 			 int npsvs, u32 *sig_index);
1075 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1076 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1077 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1078 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1079 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1080 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1081 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1082 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1083 			  struct mlx5_pvlc_reg *pvlc, int write);
1084 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1085 			  struct mlx5_ptys_reg *ptys, int write);
1086 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1087 			  struct mlx5_pmtu_reg *pmtu, int write);
1088 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1089 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1090 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1091 				int priority, int *is_enable);
1092 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1093 				 int priority, int enable);
1094 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1095 				void *out, int out_size);
1096 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1097 				 void *in, int in_size);
1098 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1099 				    void *out, int out_size);
1100 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1101 			       int in_size);
1102 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1103 				   u8 num_of_samples, u16 sample_index,
1104 				   void *out, int out_size);
1105 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1106 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1107 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1108 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1109 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1110 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1111 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1112 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1113 
1114 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1115 {
1116 	return mkey >> 8;
1117 }
1118 
1119 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1120 {
1121 	return mkey_idx << 8;
1122 }
1123 
1124 static inline u8 mlx5_mkey_variant(u32 mkey)
1125 {
1126 	return mkey & 0xff;
1127 }
1128 
1129 enum {
1130 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1131 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1132 };
1133 
1134 enum {
1135 	MAX_MR_CACHE_ENTRIES    = 15,
1136 };
1137 
1138 struct mlx5_interface {
1139 	void *			(*add)(struct mlx5_core_dev *dev);
1140 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1141 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1142 					 enum mlx5_dev_event event, unsigned long param);
1143 	void *                  (*get_dev)(void *context);
1144 	int			protocol;
1145 	struct list_head	list;
1146 };
1147 
1148 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1149 int mlx5_register_interface(struct mlx5_interface *intf);
1150 void mlx5_unregister_interface(struct mlx5_interface *intf);
1151 
1152 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1153 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1154     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1155     const u8 *mac, bool vlan, u16 vlan_id);
1156 
1157 struct mlx5_profile {
1158 	u64	mask;
1159 	u8	log_max_qp;
1160 	struct {
1161 		int	size;
1162 		int	limit;
1163 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1164 };
1165 
1166 enum {
1167 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1168 };
1169 
1170 enum {
1171 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1172 };
1173 
1174 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1175 {
1176 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1177 }
1178 #ifdef RATELIMIT
1179 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1180 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1181 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1182 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1183 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1184 
1185 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1186 {
1187 	return !!(dev->priv.rl_table.max_size);
1188 }
1189 #endif
1190 
1191 #endif /* MLX5_DRIVER_H */
1192