xref: /freebsd/sys/dev/mlx5/driver.h (revision daceb336172a6b0572de864b97e70b28451ca636) 
1 /*-
2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 enum {
53 	MLX5_BOARD_ID_LEN = 64,
54 	MLX5_MAX_NAME_LEN = 16,
55 };
56 
57 enum {
58 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
59 	MLX5_CMD_WQ_MAX_NAME	= 32,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_MAX_IRQ_NAME	= 32
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFF		= 16,
93 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
98 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
99 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
100 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
101 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
102 };
103 
104 enum {
105 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
106 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
111 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
112 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
113 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
114 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
115 };
116 
117 enum {
118 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
119 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
120 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
121 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
122 };
123 
124 enum {
125 	MLX5_REG_QPTS		 = 0x4002,
126 	MLX5_REG_QETCR		 = 0x4005,
127 	MLX5_REG_QPDP		 = 0x4007,
128 	MLX5_REG_QTCT		 = 0x400A,
129 	MLX5_REG_QPDPM		 = 0x4013,
130 	MLX5_REG_QHLL		 = 0x4016,
131 	MLX5_REG_QCAM		 = 0x4019,
132 	MLX5_REG_DCBX_PARAM	 = 0x4020,
133 	MLX5_REG_DCBX_APP	 = 0x4021,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_FPGA_CAP	 = 0x4022,
136 	MLX5_REG_FPGA_CTRL	 = 0x4023,
137 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
138 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
139 	MLX5_REG_PMTU		 = 0x5003,
140 	MLX5_REG_PTYS		 = 0x5004,
141 	MLX5_REG_PAOS		 = 0x5006,
142 	MLX5_REG_PFCC		 = 0x5007,
143 	MLX5_REG_PPCNT		 = 0x5008,
144 	MLX5_REG_PMAOS		 = 0x5012,
145 	MLX5_REG_PUDE		 = 0x5009,
146 	MLX5_REG_PPTB		 = 0x500B,
147 	MLX5_REG_PBMC		 = 0x500C,
148 	MLX5_REG_PMPE		 = 0x5010,
149 	MLX5_REG_PELC		 = 0x500e,
150 	MLX5_REG_PVLC		 = 0x500f,
151 	MLX5_REG_PMLP		 = 0x5002,
152 	MLX5_REG_PCAM		 = 0x507f,
153 	MLX5_REG_NODE_DESC	 = 0x6001,
154 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
155 	MLX5_REG_MTMP		 = 0x900a,
156 	MLX5_REG_MCIA		 = 0x9014,
157 	MLX5_REG_MPCNT		 = 0x9051,
158 	MLX5_REG_MCQI		 = 0x9061,
159 	MLX5_REG_MCC		 = 0x9062,
160 	MLX5_REG_MCDA		 = 0x9063,
161 	MLX5_REG_MCAM		 = 0x907f,
162 };
163 
164 enum dbg_rsc_type {
165 	MLX5_DBG_RSC_QP,
166 	MLX5_DBG_RSC_EQ,
167 	MLX5_DBG_RSC_CQ,
168 };
169 
170 enum {
171 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
172 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
173 	MLX5_INTERFACE_NUMBER       = 2,
174 };
175 
176 struct mlx5_field_desc {
177 	struct dentry	       *dent;
178 	int			i;
179 };
180 
181 struct mlx5_rsc_debug {
182 	struct mlx5_core_dev   *dev;
183 	void		       *object;
184 	enum dbg_rsc_type	type;
185 	struct dentry	       *root;
186 	struct mlx5_field_desc	fields[0];
187 };
188 
189 enum mlx5_dev_event {
190 	MLX5_DEV_EVENT_SYS_ERROR,
191 	MLX5_DEV_EVENT_PORT_UP,
192 	MLX5_DEV_EVENT_PORT_DOWN,
193 	MLX5_DEV_EVENT_PORT_INITIALIZED,
194 	MLX5_DEV_EVENT_LID_CHANGE,
195 	MLX5_DEV_EVENT_PKEY_CHANGE,
196 	MLX5_DEV_EVENT_GUID_CHANGE,
197 	MLX5_DEV_EVENT_CLIENT_REREG,
198 	MLX5_DEV_EVENT_VPORT_CHANGE,
199 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
200 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
201 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
202 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
203 };
204 
205 enum mlx5_port_status {
206 	MLX5_PORT_UP        = 1 << 0,
207 	MLX5_PORT_DOWN      = 1 << 1,
208 };
209 
210 enum {
211 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
212 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
213 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
214 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
215 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
216 	MLX5_VSC_DATA_OFFSET	 = 0x14,
217 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
218 };
219 
220 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
221 
222 struct mlx5_uuar_info {
223 	struct mlx5_uar	       *uars;
224 	int			num_uars;
225 	int			num_low_latency_uuars;
226 	unsigned long	       *bitmap;
227 	unsigned int	       *count;
228 	struct mlx5_bf	       *bfs;
229 
230 	/*
231 	 * protect uuar allocation data structs
232 	 */
233 	struct mutex		lock;
234 	u32			ver;
235 };
236 
237 struct mlx5_bf {
238 	void __iomem	       *reg;
239 	void __iomem	       *regreg;
240 	int			buf_size;
241 	struct mlx5_uar	       *uar;
242 	unsigned long		offset;
243 	int			need_lock;
244 	/* protect blue flame buffer selection when needed
245 	 */
246 	spinlock_t		lock;
247 
248 	/* serialize 64 bit writes when done as two 32 bit accesses
249 	 */
250 	spinlock_t		lock32;
251 	int			uuarn;
252 };
253 
254 struct mlx5_cmd_first {
255 	__be32		data[4];
256 };
257 
258 struct cache_ent;
259 struct mlx5_fw_page {
260 	union {
261 		struct rb_node rb_node;
262 		struct list_head list;
263 	};
264 	struct mlx5_cmd_first first;
265 	struct mlx5_core_dev *dev;
266 	bus_dmamap_t dma_map;
267 	bus_addr_t dma_addr;
268 	void *virt_addr;
269 	struct cache_ent *cache;
270 	u32 numpages;
271 	u16 load_done;
272 #define	MLX5_LOAD_ST_NONE 0
273 #define	MLX5_LOAD_ST_SUCCESS 1
274 #define	MLX5_LOAD_ST_FAILURE 2
275 	u16 func_id;
276 };
277 #define	mlx5_cmd_msg mlx5_fw_page
278 
279 struct mlx5_cmd_debug {
280 	struct dentry	       *dbg_root;
281 	struct dentry	       *dbg_in;
282 	struct dentry	       *dbg_out;
283 	struct dentry	       *dbg_outlen;
284 	struct dentry	       *dbg_status;
285 	struct dentry	       *dbg_run;
286 	void		       *in_msg;
287 	void		       *out_msg;
288 	u8			status;
289 	u16			inlen;
290 	u16			outlen;
291 };
292 
293 struct cache_ent {
294 	/* protect block chain allocations
295 	 */
296 	spinlock_t		lock;
297 	struct list_head	head;
298 };
299 
300 struct cmd_msg_cache {
301 	struct cache_ent	large;
302 	struct cache_ent	med;
303 
304 };
305 
306 struct mlx5_traffic_counter {
307 	u64         packets;
308 	u64         octets;
309 };
310 
311 enum mlx5_cmd_mode {
312 	MLX5_CMD_MODE_POLLING,
313 	MLX5_CMD_MODE_EVENTS
314 };
315 
316 struct mlx5_cmd_stats {
317 	u64		sum;
318 	u64		n;
319 	struct dentry  *root;
320 	struct dentry  *avg;
321 	struct dentry  *count;
322 	/* protect command average calculations */
323 	spinlock_t	lock;
324 };
325 
326 struct mlx5_cmd {
327 	struct mlx5_fw_page *cmd_page;
328 	bus_dma_tag_t dma_tag;
329 	struct sx dma_sx;
330 	struct mtx dma_mtx;
331 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
332 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
333 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
334 	struct cv dma_cv;
335 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
336 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
337 	void	       *cmd_buf;
338 	dma_addr_t	dma;
339 	u16		cmdif_rev;
340 	u8		log_sz;
341 	u8		log_stride;
342 	int		max_reg_cmds;
343 	int		events;
344 	u32 __iomem    *vector;
345 
346 	/* protect command queue allocations
347 	 */
348 	spinlock_t	alloc_lock;
349 
350 	/* protect token allocations
351 	 */
352 	spinlock_t	token_lock;
353 	u8		token;
354 	unsigned long	bitmask;
355 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
356 	struct workqueue_struct *wq;
357 	struct semaphore sem;
358 	struct semaphore pages_sem;
359 	enum mlx5_cmd_mode mode;
360 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
361 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
362 	struct mlx5_cmd_debug dbg;
363 	struct cmd_msg_cache cache;
364 	int checksum_disabled;
365 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
366 };
367 
368 struct mlx5_port_caps {
369 	int	gid_table_len;
370 	int	pkey_table_len;
371 	u8	ext_port_cap;
372 };
373 
374 struct mlx5_buf {
375 	bus_dma_tag_t		dma_tag;
376 	bus_dmamap_t		dma_map;
377 	struct mlx5_core_dev   *dev;
378 	struct {
379 		void	       *buf;
380 	} direct;
381 	u64		       *page_list;
382 	int			npages;
383 	int			size;
384 	u8			page_shift;
385 	u8			load_done;
386 };
387 
388 struct mlx5_frag_buf {
389 	struct mlx5_buf_list	*frags;
390 	int			npages;
391 	int			size;
392 	u8			page_shift;
393 };
394 
395 struct mlx5_eq {
396 	struct mlx5_core_dev   *dev;
397 	__be32 __iomem	       *doorbell;
398 	u32			cons_index;
399 	struct mlx5_buf		buf;
400 	int			size;
401 	u8			irqn;
402 	u8			eqn;
403 	int			nent;
404 	u64			mask;
405 	struct list_head	list;
406 	int			index;
407 	struct mlx5_rsc_debug	*dbg;
408 };
409 
410 struct mlx5_core_psv {
411 	u32	psv_idx;
412 	struct psv_layout {
413 		u32	pd;
414 		u16	syndrome;
415 		u16	reserved;
416 		u16	bg;
417 		u16	app_tag;
418 		u32	ref_tag;
419 	} psv;
420 };
421 
422 struct mlx5_core_sig_ctx {
423 	struct mlx5_core_psv	psv_memory;
424 	struct mlx5_core_psv	psv_wire;
425 #if (__FreeBSD_version >= 1100000)
426 	struct ib_sig_err       err_item;
427 #endif
428 	bool			sig_status_checked;
429 	bool			sig_err_exists;
430 	u32			sigerr_count;
431 };
432 
433 enum {
434 	MLX5_MKEY_MR = 1,
435 	MLX5_MKEY_MW,
436 	MLX5_MKEY_MR_USER,
437 };
438 
439 struct mlx5_core_mkey {
440 	u64			iova;
441 	u64			size;
442 	u32			key;
443 	u32			pd;
444 	u32			type;
445 };
446 
447 struct mlx5_core_mr {
448 	u64			iova;
449 	u64			size;
450 	u32			key;
451 	u32			pd;
452 };
453 
454 enum mlx5_res_type {
455 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
456 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
457 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
458 	MLX5_RES_SRQ	= 3,
459 	MLX5_RES_XSRQ	= 4,
460 	MLX5_RES_DCT	= 5,
461 };
462 
463 struct mlx5_core_rsc_common {
464 	enum mlx5_res_type	res;
465 	atomic_t		refcount;
466 	struct completion	free;
467 };
468 
469 struct mlx5_core_srq {
470 	struct mlx5_core_rsc_common	common; /* must be first */
471 	u32				srqn;
472 	int				max;
473 	size_t				max_gs;
474 	size_t				max_avail_gather;
475 	int				wqe_shift;
476 	void				(*event)(struct mlx5_core_srq *, int);
477 	atomic_t			refcount;
478 	struct completion		free;
479 };
480 
481 struct mlx5_eq_table {
482 	void __iomem	       *update_ci;
483 	void __iomem	       *update_arm_ci;
484 	struct list_head	comp_eqs_list;
485 	struct mlx5_eq		pages_eq;
486 	struct mlx5_eq		async_eq;
487 	struct mlx5_eq		cmd_eq;
488 	int			num_comp_vectors;
489 	/* protect EQs list
490 	 */
491 	spinlock_t		lock;
492 };
493 
494 struct mlx5_uar {
495 	u32			index;
496 	void __iomem	       *bf_map;
497 	void __iomem	       *map;
498 };
499 
500 
501 struct mlx5_core_health {
502 	struct mlx5_health_buffer __iomem	*health;
503 	__be32 __iomem		       *health_counter;
504 	struct timer_list		timer;
505 	u32				prev;
506 	int				miss_counter;
507 	u32				fatal_error;
508 	/* wq spinlock to synchronize draining */
509 	spinlock_t			wq_lock;
510 	struct workqueue_struct	       *wq;
511 	unsigned long			flags;
512 	struct work_struct		work;
513 	struct delayed_work		recover_work;
514 	unsigned int			last_reset_req;
515 };
516 
517 #ifdef RATELIMIT
518 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	(128 * 1024)
519 #else
520 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
521 #endif
522 
523 struct mlx5_cq_linear_array_entry {
524 	spinlock_t	lock;
525 	struct mlx5_core_cq * volatile cq;
526 };
527 
528 struct mlx5_cq_table {
529 	/* protect radix tree
530 	 */
531 	spinlock_t		lock;
532 	struct radix_tree_root	tree;
533 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
534 };
535 
536 struct mlx5_qp_table {
537 	/* protect radix tree
538 	 */
539 	spinlock_t		lock;
540 	struct radix_tree_root	tree;
541 };
542 
543 struct mlx5_srq_table {
544 	/* protect radix tree
545 	 */
546 	spinlock_t		lock;
547 	struct radix_tree_root	tree;
548 };
549 
550 struct mlx5_mr_table {
551 	/* protect radix tree
552 	 */
553 	spinlock_t		lock;
554 	struct radix_tree_root	tree;
555 };
556 
557 struct mlx5_irq_info {
558 	char name[MLX5_MAX_IRQ_NAME];
559 };
560 
561 #ifdef RATELIMIT
562 struct mlx5_rl_entry {
563 	u32			rate;
564 	u16			burst;
565 	u16			index;
566 	u32			refcount;
567 };
568 
569 struct mlx5_rl_table {
570 	struct mutex		rl_lock;
571 	u16			max_size;
572 	u32			max_rate;
573 	u32			min_rate;
574 	struct mlx5_rl_entry   *rl_entry;
575 };
576 #endif
577 
578 struct mlx5_priv {
579 	char			name[MLX5_MAX_NAME_LEN];
580 	struct mlx5_eq_table	eq_table;
581 	struct msix_entry	*msix_arr;
582 	struct mlx5_irq_info	*irq_info;
583 	struct mlx5_uuar_info	uuari;
584 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
585 	int			disable_irqs;
586 
587 	struct io_mapping	*bf_mapping;
588 
589 	/* pages stuff */
590 	struct workqueue_struct *pg_wq;
591 	struct rb_root		page_root;
592 	s64			fw_pages;
593 	atomic_t		reg_pages;
594 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
595 	struct mlx5_core_health health;
596 
597 	struct mlx5_srq_table	srq_table;
598 
599 	/* start: qp staff */
600 	struct mlx5_qp_table	qp_table;
601 	struct dentry	       *qp_debugfs;
602 	struct dentry	       *eq_debugfs;
603 	struct dentry	       *cq_debugfs;
604 	struct dentry	       *cmdif_debugfs;
605 	/* end: qp staff */
606 
607 	/* start: cq staff */
608 	struct mlx5_cq_table	cq_table;
609 	/* end: cq staff */
610 
611 	/* start: mr staff */
612 	struct mlx5_mr_table	mr_table;
613 	/* end: mr staff */
614 
615 	/* start: alloc staff */
616 	int			numa_node;
617 
618 	struct mutex   pgdir_mutex;
619 	struct list_head        pgdir_list;
620 	/* end: alloc staff */
621 	struct dentry	       *dbg_root;
622 
623 	/* protect mkey key part */
624 	spinlock_t		mkey_lock;
625 	u8			mkey_key;
626 
627 	struct list_head        dev_list;
628 	struct list_head        ctx_list;
629 	spinlock_t              ctx_lock;
630 	unsigned long		pci_dev_data;
631 #ifdef RATELIMIT
632 	struct mlx5_rl_table	rl_table;
633 #endif
634 };
635 
636 enum mlx5_device_state {
637 	MLX5_DEVICE_STATE_UP,
638 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
639 };
640 
641 enum mlx5_interface_state {
642 	MLX5_INTERFACE_STATE_UP,
643 };
644 
645 enum mlx5_pci_status {
646 	MLX5_PCI_STATUS_DISABLED,
647 	MLX5_PCI_STATUS_ENABLED,
648 };
649 
650 #define	MLX5_MAX_RESERVED_GIDS	8
651 
652 struct mlx5_rsvd_gids {
653 	unsigned int start;
654 	unsigned int count;
655 	struct ida ida;
656 };
657 
658 struct mlx5_special_contexts {
659 	int resd_lkey;
660 };
661 
662 struct mlx5_flow_root_namespace;
663 struct mlx5_dump_data;
664 struct mlx5_core_dev {
665 	struct pci_dev	       *pdev;
666 	/* sync pci state */
667 	struct mutex		pci_status_mutex;
668 	enum mlx5_pci_status	pci_status;
669 	char			board_id[MLX5_BOARD_ID_LEN];
670 	struct mlx5_cmd		cmd;
671 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
672 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
673 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
674 	struct {
675 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
676 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
677 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
678 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
679 	} caps;
680 	phys_addr_t		iseg_base;
681 	struct mlx5_init_seg __iomem *iseg;
682 	enum mlx5_device_state	state;
683 	/* sync interface state */
684 	struct mutex		intf_state_mutex;
685 	unsigned long		intf_state;
686 	void			(*event) (struct mlx5_core_dev *dev,
687 					  enum mlx5_dev_event event,
688 					  unsigned long param);
689 	struct mlx5_priv	priv;
690 	struct mlx5_profile	*profile;
691 	atomic_t		num_qps;
692 	u32			vsc_addr;
693 	u32			issi;
694 	struct mlx5_special_contexts special_contexts;
695 	unsigned int module_status[MLX5_MAX_PORTS];
696 	struct mlx5_flow_root_namespace *root_ns;
697 	struct mlx5_flow_root_namespace *fdb_root_ns;
698 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
699 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
700 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
701 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
702 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
703 	struct mlx5_dump_data	*dump_data;
704 
705 	struct sysctl_ctx_list	sysctl_ctx;
706 	int			msix_eqvec;
707 
708 	struct {
709 		struct mlx5_rsvd_gids	reserved_gids;
710 		atomic_t		roce_en;
711 	} roce;
712 #ifdef CONFIG_MLX5_FPGA
713 	struct mlx5_fpga_device	*fpga;
714 #endif
715 };
716 
717 enum {
718 	MLX5_WOL_DISABLE       = 0,
719 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
720 	MLX5_WOL_MAGIC         = 1 << 2,
721 	MLX5_WOL_ARP           = 1 << 3,
722 	MLX5_WOL_BROADCAST     = 1 << 4,
723 	MLX5_WOL_MULTICAST     = 1 << 5,
724 	MLX5_WOL_UNICAST       = 1 << 6,
725 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
726 };
727 
728 struct mlx5_db {
729 	__be32			*db;
730 	union {
731 		struct mlx5_db_pgdir		*pgdir;
732 		struct mlx5_ib_user_db_page	*user_page;
733 	}			u;
734 	dma_addr_t		dma;
735 	int			index;
736 };
737 
738 struct mlx5_net_counters {
739 	u64	packets;
740 	u64	octets;
741 };
742 
743 struct mlx5_ptys_reg {
744 	u8	an_dis_admin;
745 	u8	an_dis_ap;
746 	u8	local_port;
747 	u8	proto_mask;
748 	u32	eth_proto_cap;
749 	u16	ib_link_width_cap;
750 	u16	ib_proto_cap;
751 	u32	eth_proto_admin;
752 	u16	ib_link_width_admin;
753 	u16	ib_proto_admin;
754 	u32	eth_proto_oper;
755 	u16	ib_link_width_oper;
756 	u16	ib_proto_oper;
757 	u32	eth_proto_lp_advertise;
758 };
759 
760 struct mlx5_pvlc_reg {
761 	u8	local_port;
762 	u8	vl_hw_cap;
763 	u8	vl_admin;
764 	u8	vl_operational;
765 };
766 
767 struct mlx5_pmtu_reg {
768 	u8	local_port;
769 	u16	max_mtu;
770 	u16	admin_mtu;
771 	u16	oper_mtu;
772 };
773 
774 struct mlx5_vport_counters {
775 	struct mlx5_net_counters	received_errors;
776 	struct mlx5_net_counters	transmit_errors;
777 	struct mlx5_net_counters	received_ib_unicast;
778 	struct mlx5_net_counters	transmitted_ib_unicast;
779 	struct mlx5_net_counters	received_ib_multicast;
780 	struct mlx5_net_counters	transmitted_ib_multicast;
781 	struct mlx5_net_counters	received_eth_broadcast;
782 	struct mlx5_net_counters	transmitted_eth_broadcast;
783 	struct mlx5_net_counters	received_eth_unicast;
784 	struct mlx5_net_counters	transmitted_eth_unicast;
785 	struct mlx5_net_counters	received_eth_multicast;
786 	struct mlx5_net_counters	transmitted_eth_multicast;
787 };
788 
789 enum {
790 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
791 };
792 
793 struct mlx5_core_dct {
794 	struct mlx5_core_rsc_common	common; /* must be first */
795 	void (*event)(struct mlx5_core_dct *, int);
796 	int			dctn;
797 	struct completion	drained;
798 	struct mlx5_rsc_debug	*dbg;
799 	int			pid;
800 };
801 
802 enum {
803 	MLX5_COMP_EQ_SIZE = 1024,
804 };
805 
806 enum {
807 	MLX5_PTYS_IB = 1 << 0,
808 	MLX5_PTYS_EN = 1 << 2,
809 };
810 
811 struct mlx5_db_pgdir {
812 	struct list_head	list;
813 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
814 	struct mlx5_fw_page    *fw_page;
815 	__be32		       *db_page;
816 	dma_addr_t		db_dma;
817 };
818 
819 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
820 
821 struct mlx5_cmd_work_ent {
822 	struct mlx5_cmd_msg    *in;
823 	struct mlx5_cmd_msg    *out;
824 	int			uin_size;
825 	void		       *uout;
826 	int			uout_size;
827 	mlx5_cmd_cbk_t		callback;
828         struct delayed_work     cb_timeout_work;
829 	void		       *context;
830 	int			idx;
831 	struct completion	done;
832 	struct mlx5_cmd        *cmd;
833 	struct work_struct	work;
834 	struct mlx5_cmd_layout *lay;
835 	int			ret;
836 	int			page_queue;
837 	u8			status;
838 	u8			token;
839 	u64			ts1;
840 	u64			ts2;
841 	u16			op;
842 	u8			busy;
843 	bool			polling;
844 };
845 
846 struct mlx5_pas {
847 	u64	pa;
848 	u8	log_sz;
849 };
850 
851 enum port_state_policy {
852 	MLX5_POLICY_DOWN        = 0,
853 	MLX5_POLICY_UP          = 1,
854 	MLX5_POLICY_FOLLOW      = 2,
855 	MLX5_POLICY_INVALID     = 0xffffffff
856 };
857 
858 static inline void *
859 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
860 {
861 	return ((char *)buf->direct.buf + offset);
862 }
863 
864 
865 extern struct workqueue_struct *mlx5_core_wq;
866 
867 #define STRUCT_FIELD(header, field) \
868 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
869 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
870 
871 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
872 {
873 	return pci_get_drvdata(pdev);
874 }
875 
876 extern struct dentry *mlx5_debugfs_root;
877 
878 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
879 {
880 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
881 }
882 
883 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
884 {
885 	return ioread32be(&dev->iseg->fw_rev) >> 16;
886 }
887 
888 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
889 {
890 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
891 }
892 
893 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
894 {
895 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
896 }
897 
898 static inline int mlx5_get_gid_table_len(u16 param)
899 {
900 	if (param > 4) {
901 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
902 		return 0;
903 	}
904 
905 	return 8 * (1 << param);
906 }
907 
908 static inline void *mlx5_vzalloc(unsigned long size)
909 {
910 	void *rtn;
911 
912 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
913 	return rtn;
914 }
915 
916 static inline void *mlx5_vmalloc(unsigned long size)
917 {
918 	void *rtn;
919 
920 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
921 	if (!rtn)
922 		rtn = vmalloc(size);
923 	return rtn;
924 }
925 
926 static inline u32 mlx5_base_mkey(const u32 key)
927 {
928 	return key & 0xffffff00u;
929 }
930 
931 int mlx5_cmd_init(struct mlx5_core_dev *dev);
932 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
933 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
934 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
935 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
936 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
937 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
938 		  int out_size);
939 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
940 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
941 		     void *context);
942 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
943 			  void *out, int out_size);
944 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
945 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
946 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
947 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
948 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
949 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
950 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
951 int mlx5_health_init(struct mlx5_core_dev *dev);
952 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
953 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
954 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
955 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
956 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
957 
958 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
959 	mlx5_buf_alloc(dev, size, direct, buf)
960 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
961 		   struct mlx5_buf *buf);
962 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
963 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
964 			 struct mlx5_srq_attr *in);
965 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
966 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
967 			struct mlx5_srq_attr *out);
968 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
969 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
970 		      u16 lwm, int is_srq);
971 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
972 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
973 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
974 			     struct mlx5_core_mr *mkey,
975 			     u32 *in, int inlen,
976 			     u32 *out, int outlen,
977 			     mlx5_cmd_cbk_t callback, void *context);
978 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
979 			  struct mlx5_core_mr *mr,
980 			  u32 *in, int inlen);
981 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
982 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
983 			 u32 *out, int outlen);
984 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
985 			     u32 *mkey);
986 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
987 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
988 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
989 		      u16 opmod, u8 port);
990 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
991 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
992 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
993 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
994 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
995 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
996 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
997 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
998 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
999 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1000 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1001 				 s32 npages);
1002 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1003 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1004 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1005 void mlx5_register_debugfs(void);
1006 void mlx5_unregister_debugfs(void);
1007 int mlx5_eq_init(struct mlx5_core_dev *dev);
1008 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1009 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1010 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1011 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1012 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1013 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1014 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1015 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1016 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1017 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
1018 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1019 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1020 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1021 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1022 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1023 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1024 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1025 				u64 addr);
1026 
1027 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1028 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1029 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1030 			 int size_in, void *data_out, int size_out,
1031 			 u16 reg_num, int arg, int write);
1032 
1033 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1034 
1035 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1036 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1037 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1038 		       u32 *out, int outlen);
1039 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1040 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1041 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1042 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1043 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1044 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1045 		       int node);
1046 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1047 
1048 const char *mlx5_command_str(int command);
1049 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1050 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1051 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1052 			 int npsvs, u32 *sig_index);
1053 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1054 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1055 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1056 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1057 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1058 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1059 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1060 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1061 			  struct mlx5_pvlc_reg *pvlc, int write);
1062 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1063 			  struct mlx5_ptys_reg *ptys, int write);
1064 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1065 			  struct mlx5_pmtu_reg *pmtu, int write);
1066 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1067 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1068 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1069 				int priority, int *is_enable);
1070 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1071 				 int priority, int enable);
1072 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1073 				void *out, int out_size);
1074 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1075 				 void *in, int in_size);
1076 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1077 				    void *out, int out_size);
1078 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1079 			       int in_size);
1080 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1081 				   u8 num_of_samples, u16 sample_index,
1082 				   void *out, int out_size);
1083 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1084 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1085 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1086 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1087 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1088 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1089 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1090 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1091 
1092 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1093 {
1094 	return mkey >> 8;
1095 }
1096 
1097 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1098 {
1099 	return mkey_idx << 8;
1100 }
1101 
1102 static inline u8 mlx5_mkey_variant(u32 mkey)
1103 {
1104 	return mkey & 0xff;
1105 }
1106 
1107 enum {
1108 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1109 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1110 };
1111 
1112 enum {
1113 	MAX_MR_CACHE_ENTRIES    = 15,
1114 };
1115 
1116 struct mlx5_interface {
1117 	void *			(*add)(struct mlx5_core_dev *dev);
1118 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1119 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1120 					 enum mlx5_dev_event event, unsigned long param);
1121 	void *                  (*get_dev)(void *context);
1122 	int			protocol;
1123 	struct list_head	list;
1124 };
1125 
1126 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1127 int mlx5_register_interface(struct mlx5_interface *intf);
1128 void mlx5_unregister_interface(struct mlx5_interface *intf);
1129 
1130 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1131 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1132     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1133     const u8 *mac, bool vlan, u16 vlan_id);
1134 
1135 struct mlx5_profile {
1136 	u64	mask;
1137 	u8	log_max_qp;
1138 	struct {
1139 		int	size;
1140 		int	limit;
1141 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1142 };
1143 
1144 enum {
1145 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1146 };
1147 
1148 enum {
1149 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1150 };
1151 
1152 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1153 {
1154 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1155 }
1156 #ifdef RATELIMIT
1157 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1158 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1159 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1160 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1161 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1162 
1163 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1164 {
1165 	return !!(dev->priv.rl_table.max_size);
1166 }
1167 #endif
1168 
1169 #endif /* MLX5_DRIVER_H */
1170