1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include "opt_ratelimit.h" 32 33 #include <linux/kernel.h> 34 #include <linux/completion.h> 35 #include <linux/pci.h> 36 #include <linux/cache.h> 37 #include <linux/rbtree.h> 38 #include <linux/if_ether.h> 39 #include <linux/semaphore.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <linux/radix-tree.h> 43 44 #include <dev/mlx5/device.h> 45 #include <dev/mlx5/doorbell.h> 46 #include <dev/mlx5/srq.h> 47 48 #define MLX5_QCOUNTER_SETS_NETDEV 64 49 #define MLX5_MAX_NUMBER_OF_VFS 128 50 51 enum { 52 MLX5_BOARD_ID_LEN = 64, 53 MLX5_MAX_NAME_LEN = 16, 54 }; 55 56 enum { 57 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 58 MLX5_CMD_WQ_MAX_NAME = 32, 59 }; 60 61 enum { 62 CMD_OWNER_SW = 0x0, 63 CMD_OWNER_HW = 0x1, 64 CMD_STATUS_SUCCESS = 0, 65 }; 66 67 enum mlx5_sqp_t { 68 MLX5_SQP_SMI = 0, 69 MLX5_SQP_GSI = 1, 70 MLX5_SQP_IEEE_1588 = 2, 71 MLX5_SQP_SNIFFER = 3, 72 MLX5_SQP_SYNC_UMR = 4, 73 }; 74 75 enum { 76 MLX5_MAX_PORTS = 2, 77 }; 78 79 enum { 80 MLX5_EQ_VEC_PAGES = 0, 81 MLX5_EQ_VEC_CMD = 1, 82 MLX5_EQ_VEC_ASYNC = 2, 83 MLX5_EQ_VEC_COMP_BASE, 84 }; 85 86 enum { 87 MLX5_MAX_IRQ_NAME = 32 88 }; 89 90 enum { 91 MLX5_ATOMIC_MODE_OFF = 16, 92 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 99 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 100 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 101 }; 102 103 enum { 104 MLX5_ATOMIC_MODE_DCT_OFF = 20, 105 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 112 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 113 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 114 }; 115 116 enum { 117 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 118 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 119 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 120 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 121 }; 122 123 enum { 124 MLX5_REG_QPTS = 0x4002, 125 MLX5_REG_QETCR = 0x4005, 126 MLX5_REG_QPDP = 0x4007, 127 MLX5_REG_QTCT = 0x400A, 128 MLX5_REG_QPDPM = 0x4013, 129 MLX5_REG_QHLL = 0x4016, 130 MLX5_REG_QCAM = 0x4019, 131 MLX5_REG_DCBX_PARAM = 0x4020, 132 MLX5_REG_DCBX_APP = 0x4021, 133 MLX5_REG_PCAP = 0x5001, 134 MLX5_REG_PMTU = 0x5003, 135 MLX5_REG_PTYS = 0x5004, 136 MLX5_REG_PAOS = 0x5006, 137 MLX5_REG_PFCC = 0x5007, 138 MLX5_REG_PPCNT = 0x5008, 139 MLX5_REG_PMAOS = 0x5012, 140 MLX5_REG_PUDE = 0x5009, 141 MLX5_REG_PPTB = 0x500B, 142 MLX5_REG_PBMC = 0x500C, 143 MLX5_REG_PMPE = 0x5010, 144 MLX5_REG_PELC = 0x500e, 145 MLX5_REG_PVLC = 0x500f, 146 MLX5_REG_PMLP = 0x5002, 147 MLX5_REG_NODE_DESC = 0x6001, 148 MLX5_REG_HOST_ENDIANNESS = 0x7004, 149 MLX5_REG_MCIA = 0x9014, 150 MLX5_REG_MPCNT = 0x9051, 151 }; 152 153 enum dbg_rsc_type { 154 MLX5_DBG_RSC_QP, 155 MLX5_DBG_RSC_EQ, 156 MLX5_DBG_RSC_CQ, 157 }; 158 159 enum { 160 MLX5_INTERFACE_PROTOCOL_IB = 0, 161 MLX5_INTERFACE_PROTOCOL_ETH = 1, 162 MLX5_INTERFACE_NUMBER = 2, 163 }; 164 165 struct mlx5_field_desc { 166 struct dentry *dent; 167 int i; 168 }; 169 170 struct mlx5_rsc_debug { 171 struct mlx5_core_dev *dev; 172 void *object; 173 enum dbg_rsc_type type; 174 struct dentry *root; 175 struct mlx5_field_desc fields[0]; 176 }; 177 178 enum mlx5_dev_event { 179 MLX5_DEV_EVENT_SYS_ERROR, 180 MLX5_DEV_EVENT_PORT_UP, 181 MLX5_DEV_EVENT_PORT_DOWN, 182 MLX5_DEV_EVENT_PORT_INITIALIZED, 183 MLX5_DEV_EVENT_LID_CHANGE, 184 MLX5_DEV_EVENT_PKEY_CHANGE, 185 MLX5_DEV_EVENT_GUID_CHANGE, 186 MLX5_DEV_EVENT_CLIENT_REREG, 187 MLX5_DEV_EVENT_VPORT_CHANGE, 188 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 189 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 190 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 191 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 192 }; 193 194 enum mlx5_port_status { 195 MLX5_PORT_UP = 1 << 0, 196 MLX5_PORT_DOWN = 1 << 1, 197 }; 198 199 enum mlx5_link_mode { 200 MLX5_1000BASE_CX_SGMII = 0, 201 MLX5_1000BASE_KX = 1, 202 MLX5_10GBASE_CX4 = 2, 203 MLX5_10GBASE_KX4 = 3, 204 MLX5_10GBASE_KR = 4, 205 MLX5_20GBASE_KR2 = 5, 206 MLX5_40GBASE_CR4 = 6, 207 MLX5_40GBASE_KR4 = 7, 208 MLX5_56GBASE_R4 = 8, 209 MLX5_10GBASE_CR = 12, 210 MLX5_10GBASE_SR = 13, 211 MLX5_10GBASE_ER = 14, 212 MLX5_40GBASE_SR4 = 15, 213 MLX5_40GBASE_LR4 = 16, 214 MLX5_100GBASE_CR4 = 20, 215 MLX5_100GBASE_SR4 = 21, 216 MLX5_100GBASE_KR4 = 22, 217 MLX5_100GBASE_LR4 = 23, 218 MLX5_100BASE_TX = 24, 219 MLX5_1000BASE_T = 25, 220 MLX5_10GBASE_T = 26, 221 MLX5_25GBASE_CR = 27, 222 MLX5_25GBASE_KR = 28, 223 MLX5_25GBASE_SR = 29, 224 MLX5_50GBASE_CR2 = 30, 225 MLX5_50GBASE_KR2 = 31, 226 MLX5_LINK_MODES_NUMBER, 227 }; 228 229 enum { 230 MLX5_VSC_SPACE_SUPPORTED = 0x1, 231 MLX5_VSC_SPACE_OFFSET = 0x4, 232 MLX5_VSC_COUNTER_OFFSET = 0x8, 233 MLX5_VSC_SEMA_OFFSET = 0xC, 234 MLX5_VSC_ADDR_OFFSET = 0x10, 235 MLX5_VSC_DATA_OFFSET = 0x14, 236 MLX5_VSC_MAX_RETRIES = 0x1000, 237 }; 238 239 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 240 241 struct mlx5_uuar_info { 242 struct mlx5_uar *uars; 243 int num_uars; 244 int num_low_latency_uuars; 245 unsigned long *bitmap; 246 unsigned int *count; 247 struct mlx5_bf *bfs; 248 249 /* 250 * protect uuar allocation data structs 251 */ 252 struct mutex lock; 253 u32 ver; 254 }; 255 256 struct mlx5_bf { 257 void __iomem *reg; 258 void __iomem *regreg; 259 int buf_size; 260 struct mlx5_uar *uar; 261 unsigned long offset; 262 int need_lock; 263 /* protect blue flame buffer selection when needed 264 */ 265 spinlock_t lock; 266 267 /* serialize 64 bit writes when done as two 32 bit accesses 268 */ 269 spinlock_t lock32; 270 int uuarn; 271 }; 272 273 struct mlx5_cmd_first { 274 __be32 data[4]; 275 }; 276 277 struct cache_ent; 278 struct mlx5_fw_page { 279 union { 280 struct rb_node rb_node; 281 struct list_head list; 282 }; 283 struct mlx5_cmd_first first; 284 struct mlx5_core_dev *dev; 285 bus_dmamap_t dma_map; 286 bus_addr_t dma_addr; 287 void *virt_addr; 288 struct cache_ent *cache; 289 u32 numpages; 290 u16 load_done; 291 #define MLX5_LOAD_ST_NONE 0 292 #define MLX5_LOAD_ST_SUCCESS 1 293 #define MLX5_LOAD_ST_FAILURE 2 294 u16 func_id; 295 }; 296 #define mlx5_cmd_msg mlx5_fw_page 297 298 struct mlx5_cmd_debug { 299 struct dentry *dbg_root; 300 struct dentry *dbg_in; 301 struct dentry *dbg_out; 302 struct dentry *dbg_outlen; 303 struct dentry *dbg_status; 304 struct dentry *dbg_run; 305 void *in_msg; 306 void *out_msg; 307 u8 status; 308 u16 inlen; 309 u16 outlen; 310 }; 311 312 struct cache_ent { 313 /* protect block chain allocations 314 */ 315 spinlock_t lock; 316 struct list_head head; 317 }; 318 319 struct cmd_msg_cache { 320 struct cache_ent large; 321 struct cache_ent med; 322 323 }; 324 325 struct mlx5_traffic_counter { 326 u64 packets; 327 u64 octets; 328 }; 329 330 struct mlx5_cmd_stats { 331 u64 sum; 332 u64 n; 333 struct dentry *root; 334 struct dentry *avg; 335 struct dentry *count; 336 /* protect command average calculations */ 337 spinlock_t lock; 338 }; 339 340 struct mlx5_cmd { 341 struct mlx5_fw_page *cmd_page; 342 bus_dma_tag_t dma_tag; 343 struct sx dma_sx; 344 struct mtx dma_mtx; 345 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 346 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 347 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 348 struct cv dma_cv; 349 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 350 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 351 void *cmd_buf; 352 dma_addr_t dma; 353 u16 cmdif_rev; 354 u8 log_sz; 355 u8 log_stride; 356 int max_reg_cmds; 357 int events; 358 u32 __iomem *vector; 359 360 /* protect command queue allocations 361 */ 362 spinlock_t alloc_lock; 363 364 /* protect token allocations 365 */ 366 spinlock_t token_lock; 367 u8 token; 368 unsigned long bitmask; 369 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 370 struct workqueue_struct *wq; 371 struct semaphore sem; 372 struct semaphore pages_sem; 373 int mode; 374 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 375 struct mlx5_cmd_debug dbg; 376 struct cmd_msg_cache cache; 377 int checksum_disabled; 378 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 379 }; 380 381 struct mlx5_port_caps { 382 int gid_table_len; 383 int pkey_table_len; 384 u8 ext_port_cap; 385 }; 386 387 struct mlx5_buf { 388 bus_dma_tag_t dma_tag; 389 bus_dmamap_t dma_map; 390 struct mlx5_core_dev *dev; 391 struct { 392 void *buf; 393 } direct; 394 u64 *page_list; 395 int npages; 396 int size; 397 u8 page_shift; 398 u8 load_done; 399 }; 400 401 struct mlx5_eq { 402 struct mlx5_core_dev *dev; 403 __be32 __iomem *doorbell; 404 u32 cons_index; 405 struct mlx5_buf buf; 406 int size; 407 u8 irqn; 408 u8 eqn; 409 int nent; 410 u64 mask; 411 struct list_head list; 412 int index; 413 struct mlx5_rsc_debug *dbg; 414 }; 415 416 struct mlx5_core_psv { 417 u32 psv_idx; 418 struct psv_layout { 419 u32 pd; 420 u16 syndrome; 421 u16 reserved; 422 u16 bg; 423 u16 app_tag; 424 u32 ref_tag; 425 } psv; 426 }; 427 428 struct mlx5_core_sig_ctx { 429 struct mlx5_core_psv psv_memory; 430 struct mlx5_core_psv psv_wire; 431 #if (__FreeBSD_version >= 1100000) 432 struct ib_sig_err err_item; 433 #endif 434 bool sig_status_checked; 435 bool sig_err_exists; 436 u32 sigerr_count; 437 }; 438 439 struct mlx5_core_mr { 440 u64 iova; 441 u64 size; 442 u32 key; 443 u32 pd; 444 }; 445 446 enum mlx5_res_type { 447 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 448 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 449 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 450 MLX5_RES_SRQ = 3, 451 MLX5_RES_XSRQ = 4, 452 MLX5_RES_DCT = 5, 453 }; 454 455 struct mlx5_core_rsc_common { 456 enum mlx5_res_type res; 457 atomic_t refcount; 458 struct completion free; 459 }; 460 461 struct mlx5_core_srq { 462 struct mlx5_core_rsc_common common; /* must be first */ 463 u32 srqn; 464 int max; 465 int max_gs; 466 int max_avail_gather; 467 int wqe_shift; 468 void (*event)(struct mlx5_core_srq *, int); 469 atomic_t refcount; 470 struct completion free; 471 }; 472 473 struct mlx5_eq_table { 474 void __iomem *update_ci; 475 void __iomem *update_arm_ci; 476 struct list_head comp_eqs_list; 477 struct mlx5_eq pages_eq; 478 struct mlx5_eq async_eq; 479 struct mlx5_eq cmd_eq; 480 int num_comp_vectors; 481 /* protect EQs list 482 */ 483 spinlock_t lock; 484 }; 485 486 struct mlx5_uar { 487 u32 index; 488 void __iomem *bf_map; 489 void __iomem *map; 490 }; 491 492 493 struct mlx5_core_health { 494 struct mlx5_health_buffer __iomem *health; 495 __be32 __iomem *health_counter; 496 struct timer_list timer; 497 u32 prev; 498 int miss_counter; 499 u32 fatal_error; 500 /* wq spinlock to synchronize draining */ 501 spinlock_t wq_lock; 502 struct workqueue_struct *wq; 503 unsigned long flags; 504 struct work_struct work; 505 struct delayed_work recover_work; 506 }; 507 508 #ifdef RATELIMIT 509 #define MLX5_CQ_LINEAR_ARRAY_SIZE (128 * 1024) 510 #else 511 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 512 #endif 513 514 struct mlx5_cq_linear_array_entry { 515 spinlock_t lock; 516 struct mlx5_core_cq * volatile cq; 517 }; 518 519 struct mlx5_cq_table { 520 /* protect radix tree 521 */ 522 spinlock_t lock; 523 struct radix_tree_root tree; 524 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 525 }; 526 527 struct mlx5_qp_table { 528 /* protect radix tree 529 */ 530 spinlock_t lock; 531 struct radix_tree_root tree; 532 }; 533 534 struct mlx5_srq_table { 535 /* protect radix tree 536 */ 537 spinlock_t lock; 538 struct radix_tree_root tree; 539 }; 540 541 struct mlx5_mr_table { 542 /* protect radix tree 543 */ 544 spinlock_t lock; 545 struct radix_tree_root tree; 546 }; 547 548 struct mlx5_irq_info { 549 char name[MLX5_MAX_IRQ_NAME]; 550 }; 551 552 #ifdef RATELIMIT 553 struct mlx5_rl_entry { 554 u32 rate; 555 u16 burst; 556 u16 index; 557 u32 refcount; 558 }; 559 560 struct mlx5_rl_table { 561 struct mutex rl_lock; 562 u16 max_size; 563 u32 max_rate; 564 u32 min_rate; 565 struct mlx5_rl_entry *rl_entry; 566 }; 567 #endif 568 569 struct mlx5_priv { 570 char name[MLX5_MAX_NAME_LEN]; 571 struct mlx5_eq_table eq_table; 572 struct msix_entry *msix_arr; 573 struct mlx5_irq_info *irq_info; 574 struct mlx5_uuar_info uuari; 575 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 576 577 struct io_mapping *bf_mapping; 578 579 /* pages stuff */ 580 struct workqueue_struct *pg_wq; 581 struct rb_root page_root; 582 s64 fw_pages; 583 atomic_t reg_pages; 584 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 585 struct mlx5_core_health health; 586 587 struct mlx5_srq_table srq_table; 588 589 /* start: qp staff */ 590 struct mlx5_qp_table qp_table; 591 struct dentry *qp_debugfs; 592 struct dentry *eq_debugfs; 593 struct dentry *cq_debugfs; 594 struct dentry *cmdif_debugfs; 595 /* end: qp staff */ 596 597 /* start: cq staff */ 598 struct mlx5_cq_table cq_table; 599 /* end: cq staff */ 600 601 /* start: mr staff */ 602 struct mlx5_mr_table mr_table; 603 /* end: mr staff */ 604 605 /* start: alloc staff */ 606 int numa_node; 607 608 struct mutex pgdir_mutex; 609 struct list_head pgdir_list; 610 /* end: alloc staff */ 611 struct dentry *dbg_root; 612 613 /* protect mkey key part */ 614 spinlock_t mkey_lock; 615 u8 mkey_key; 616 617 struct list_head dev_list; 618 struct list_head ctx_list; 619 spinlock_t ctx_lock; 620 unsigned long pci_dev_data; 621 #ifdef RATELIMIT 622 struct mlx5_rl_table rl_table; 623 #endif 624 }; 625 626 enum mlx5_device_state { 627 MLX5_DEVICE_STATE_UP, 628 MLX5_DEVICE_STATE_INTERNAL_ERROR, 629 }; 630 631 enum mlx5_interface_state { 632 MLX5_INTERFACE_STATE_DOWN = BIT(0), 633 MLX5_INTERFACE_STATE_UP = BIT(1), 634 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), 635 }; 636 637 enum mlx5_pci_status { 638 MLX5_PCI_STATUS_DISABLED, 639 MLX5_PCI_STATUS_ENABLED, 640 }; 641 642 struct mlx5_special_contexts { 643 int resd_lkey; 644 }; 645 646 struct mlx5_flow_root_namespace; 647 struct mlx5_dump_data; 648 struct mlx5_core_dev { 649 struct pci_dev *pdev; 650 /* sync pci state */ 651 struct mutex pci_status_mutex; 652 enum mlx5_pci_status pci_status; 653 char board_id[MLX5_BOARD_ID_LEN]; 654 struct mlx5_cmd cmd; 655 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 656 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 657 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 658 struct { 659 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 660 } caps; 661 phys_addr_t iseg_base; 662 struct mlx5_init_seg __iomem *iseg; 663 enum mlx5_device_state state; 664 /* sync interface state */ 665 struct mutex intf_state_mutex; 666 unsigned long intf_state; 667 void (*event) (struct mlx5_core_dev *dev, 668 enum mlx5_dev_event event, 669 unsigned long param); 670 struct mlx5_priv priv; 671 struct mlx5_profile *profile; 672 atomic_t num_qps; 673 u32 vsc_addr; 674 u32 issi; 675 struct mlx5_special_contexts special_contexts; 676 unsigned int module_status[MLX5_MAX_PORTS]; 677 struct mlx5_flow_root_namespace *root_ns; 678 struct mlx5_flow_root_namespace *fdb_root_ns; 679 struct mlx5_flow_root_namespace *esw_egress_root_ns; 680 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 681 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 682 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 683 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 684 struct mlx5_dump_data *dump_data; 685 686 struct sysctl_ctx_list sysctl_ctx; 687 int msix_eqvec; 688 }; 689 690 enum { 691 MLX5_WOL_DISABLE = 0, 692 MLX5_WOL_SECURED_MAGIC = 1 << 1, 693 MLX5_WOL_MAGIC = 1 << 2, 694 MLX5_WOL_ARP = 1 << 3, 695 MLX5_WOL_BROADCAST = 1 << 4, 696 MLX5_WOL_MULTICAST = 1 << 5, 697 MLX5_WOL_UNICAST = 1 << 6, 698 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 699 }; 700 701 struct mlx5_db { 702 __be32 *db; 703 union { 704 struct mlx5_db_pgdir *pgdir; 705 struct mlx5_ib_user_db_page *user_page; 706 } u; 707 dma_addr_t dma; 708 int index; 709 }; 710 711 struct mlx5_net_counters { 712 u64 packets; 713 u64 octets; 714 }; 715 716 struct mlx5_ptys_reg { 717 u8 an_dis_admin; 718 u8 an_dis_ap; 719 u8 local_port; 720 u8 proto_mask; 721 u32 eth_proto_cap; 722 u16 ib_link_width_cap; 723 u16 ib_proto_cap; 724 u32 eth_proto_admin; 725 u16 ib_link_width_admin; 726 u16 ib_proto_admin; 727 u32 eth_proto_oper; 728 u16 ib_link_width_oper; 729 u16 ib_proto_oper; 730 u32 eth_proto_lp_advertise; 731 }; 732 733 struct mlx5_pvlc_reg { 734 u8 local_port; 735 u8 vl_hw_cap; 736 u8 vl_admin; 737 u8 vl_operational; 738 }; 739 740 struct mlx5_pmtu_reg { 741 u8 local_port; 742 u16 max_mtu; 743 u16 admin_mtu; 744 u16 oper_mtu; 745 }; 746 747 struct mlx5_vport_counters { 748 struct mlx5_net_counters received_errors; 749 struct mlx5_net_counters transmit_errors; 750 struct mlx5_net_counters received_ib_unicast; 751 struct mlx5_net_counters transmitted_ib_unicast; 752 struct mlx5_net_counters received_ib_multicast; 753 struct mlx5_net_counters transmitted_ib_multicast; 754 struct mlx5_net_counters received_eth_broadcast; 755 struct mlx5_net_counters transmitted_eth_broadcast; 756 struct mlx5_net_counters received_eth_unicast; 757 struct mlx5_net_counters transmitted_eth_unicast; 758 struct mlx5_net_counters received_eth_multicast; 759 struct mlx5_net_counters transmitted_eth_multicast; 760 }; 761 762 enum { 763 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 764 }; 765 766 struct mlx5_core_dct { 767 struct mlx5_core_rsc_common common; /* must be first */ 768 void (*event)(struct mlx5_core_dct *, int); 769 int dctn; 770 struct completion drained; 771 struct mlx5_rsc_debug *dbg; 772 int pid; 773 }; 774 775 enum { 776 MLX5_COMP_EQ_SIZE = 1024, 777 }; 778 779 enum { 780 MLX5_PTYS_IB = 1 << 0, 781 MLX5_PTYS_EN = 1 << 2, 782 }; 783 784 struct mlx5_db_pgdir { 785 struct list_head list; 786 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 787 struct mlx5_fw_page *fw_page; 788 __be32 *db_page; 789 dma_addr_t db_dma; 790 }; 791 792 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 793 794 struct mlx5_cmd_work_ent { 795 struct mlx5_cmd_msg *in; 796 struct mlx5_cmd_msg *out; 797 int uin_size; 798 void *uout; 799 int uout_size; 800 mlx5_cmd_cbk_t callback; 801 struct delayed_work cb_timeout_work; 802 void *context; 803 int idx; 804 struct completion done; 805 struct mlx5_cmd *cmd; 806 struct work_struct work; 807 struct mlx5_cmd_layout *lay; 808 int ret; 809 int page_queue; 810 u8 status; 811 u8 token; 812 u64 ts1; 813 u64 ts2; 814 u16 op; 815 u8 busy; 816 bool polling; 817 }; 818 819 struct mlx5_pas { 820 u64 pa; 821 u8 log_sz; 822 }; 823 824 enum port_state_policy { 825 MLX5_POLICY_DOWN = 0, 826 MLX5_POLICY_UP = 1, 827 MLX5_POLICY_FOLLOW = 2, 828 MLX5_POLICY_INVALID = 0xffffffff 829 }; 830 831 static inline void * 832 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 833 { 834 return ((char *)buf->direct.buf + offset); 835 } 836 837 838 extern struct workqueue_struct *mlx5_core_wq; 839 840 #define STRUCT_FIELD(header, field) \ 841 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 842 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 843 844 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 845 { 846 return pci_get_drvdata(pdev); 847 } 848 849 extern struct dentry *mlx5_debugfs_root; 850 851 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 852 { 853 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 854 } 855 856 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 857 { 858 return ioread32be(&dev->iseg->fw_rev) >> 16; 859 } 860 861 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 862 { 863 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 864 } 865 866 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 867 { 868 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 869 } 870 871 static inline int mlx5_get_gid_table_len(u16 param) 872 { 873 if (param > 4) { 874 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 875 return 0; 876 } 877 878 return 8 * (1 << param); 879 } 880 881 static inline void *mlx5_vzalloc(unsigned long size) 882 { 883 void *rtn; 884 885 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 886 return rtn; 887 } 888 889 static inline void *mlx5_vmalloc(unsigned long size) 890 { 891 void *rtn; 892 893 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 894 if (!rtn) 895 rtn = vmalloc(size); 896 return rtn; 897 } 898 899 static inline u32 mlx5_base_mkey(const u32 key) 900 { 901 return key & 0xffffff00u; 902 } 903 904 int mlx5_cmd_init(struct mlx5_core_dev *dev); 905 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 906 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 907 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 908 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 909 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 910 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 911 int out_size); 912 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 913 void *out, int out_size, mlx5_cmd_cbk_t callback, 914 void *context); 915 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 916 void *out, int out_size); 917 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 918 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 919 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 920 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 921 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 922 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 923 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 924 int mlx5_health_init(struct mlx5_core_dev *dev); 925 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 926 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 927 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 928 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 929 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 930 931 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 932 mlx5_buf_alloc(dev, size, direct, buf) 933 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 934 struct mlx5_buf *buf); 935 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 936 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 937 struct mlx5_srq_attr *in); 938 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 939 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 940 struct mlx5_srq_attr *out); 941 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 942 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 943 u16 lwm, int is_srq); 944 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 945 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 946 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 947 struct mlx5_core_mr *mkey, 948 u32 *in, int inlen, 949 u32 *out, int outlen, 950 mlx5_cmd_cbk_t callback, void *context); 951 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 952 struct mlx5_core_mr *mr, 953 u32 *in, int inlen); 954 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 955 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 956 u32 *out, int outlen); 957 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 958 u32 *mkey); 959 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 960 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 961 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 962 u16 opmod, u8 port); 963 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 964 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 965 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 966 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 967 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 968 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 969 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 970 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 971 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 972 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 973 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 974 s32 npages); 975 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 976 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 977 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 978 void mlx5_register_debugfs(void); 979 void mlx5_unregister_debugfs(void); 980 int mlx5_eq_init(struct mlx5_core_dev *dev); 981 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 982 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 983 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 984 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 985 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 986 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 987 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector); 988 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 989 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 990 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 991 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 992 int mlx5_start_eqs(struct mlx5_core_dev *dev); 993 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 994 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 995 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 996 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 997 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 998 u64 addr); 999 1000 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1001 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1002 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1003 int size_in, void *data_out, int size_out, 1004 u16 reg_num, int arg, int write); 1005 1006 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1007 1008 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1009 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1010 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1011 u32 *out, int outlen); 1012 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1013 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1014 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1015 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1016 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1017 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1018 int node); 1019 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1020 1021 const char *mlx5_command_str(int command); 1022 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1023 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1024 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1025 int npsvs, u32 *sig_index); 1026 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1027 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1028 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1029 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1030 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1031 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1032 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1033 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1034 struct mlx5_pvlc_reg *pvlc, int write); 1035 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1036 struct mlx5_ptys_reg *ptys, int write); 1037 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1038 struct mlx5_pmtu_reg *pmtu, int write); 1039 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1040 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1041 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1042 int priority, int *is_enable); 1043 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1044 int priority, int enable); 1045 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1046 void *out, int out_size); 1047 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1048 void *in, int in_size); 1049 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1050 void *out, int out_size); 1051 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1052 int in_size); 1053 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1054 u8 num_of_samples, u16 sample_index, 1055 void *out, int out_size); 1056 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1057 int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1058 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1059 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1060 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1061 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1062 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1063 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1064 1065 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1066 { 1067 return mkey >> 8; 1068 } 1069 1070 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1071 { 1072 return mkey_idx << 8; 1073 } 1074 1075 static inline u8 mlx5_mkey_variant(u32 mkey) 1076 { 1077 return mkey & 0xff; 1078 } 1079 1080 enum { 1081 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1082 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1083 }; 1084 1085 enum { 1086 MAX_MR_CACHE_ENTRIES = 15, 1087 }; 1088 1089 struct mlx5_interface { 1090 void * (*add)(struct mlx5_core_dev *dev); 1091 void (*remove)(struct mlx5_core_dev *dev, void *context); 1092 void (*event)(struct mlx5_core_dev *dev, void *context, 1093 enum mlx5_dev_event event, unsigned long param); 1094 void * (*get_dev)(void *context); 1095 int protocol; 1096 struct list_head list; 1097 }; 1098 1099 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1100 int mlx5_register_interface(struct mlx5_interface *intf); 1101 void mlx5_unregister_interface(struct mlx5_interface *intf); 1102 1103 struct mlx5_profile { 1104 u64 mask; 1105 u8 log_max_qp; 1106 struct { 1107 int size; 1108 int limit; 1109 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1110 }; 1111 1112 enum { 1113 MLX5_PCI_DEV_IS_VF = 1 << 0, 1114 }; 1115 1116 enum { 1117 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1118 }; 1119 1120 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1121 { 1122 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1123 } 1124 #ifdef RATELIMIT 1125 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1126 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1127 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index); 1128 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst); 1129 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst); 1130 1131 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1132 { 1133 return !!(dev->priv.rl_table.max_size); 1134 } 1135 #endif 1136 1137 #endif /* MLX5_DRIVER_H */ 1138