1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef MLX5_DRIVER_H 30 #define MLX5_DRIVER_H 31 32 #include "opt_ratelimit.h" 33 34 #include <linux/kernel.h> 35 #include <linux/completion.h> 36 #include <linux/pci.h> 37 #include <linux/cache.h> 38 #include <linux/rbtree.h> 39 #include <linux/if_ether.h> 40 #include <linux/semaphore.h> 41 #include <linux/slab.h> 42 #include <linux/vmalloc.h> 43 #include <linux/radix-tree.h> 44 #include <linux/idr.h> 45 #include <linux/wait.h> 46 47 #include <dev/mlx5/device.h> 48 #include <dev/mlx5/doorbell.h> 49 #include <dev/mlx5/srq.h> 50 51 #define MLX5_QCOUNTER_SETS_NETDEV 64 52 #define MLX5_MAX_NUMBER_OF_VFS 128 53 54 #define MLX5_INVALID_QUEUE_HANDLE 0xffffffff 55 56 enum { 57 MLX5_BOARD_ID_LEN = 64, 58 MLX5_MAX_NAME_LEN = 16, 59 }; 60 61 enum { 62 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 63 }; 64 65 enum { 66 CMD_OWNER_SW = 0x0, 67 CMD_OWNER_HW = 0x1, 68 CMD_STATUS_SUCCESS = 0, 69 }; 70 71 enum mlx5_sqp_t { 72 MLX5_SQP_SMI = 0, 73 MLX5_SQP_GSI = 1, 74 MLX5_SQP_IEEE_1588 = 2, 75 MLX5_SQP_SNIFFER = 3, 76 MLX5_SQP_SYNC_UMR = 4, 77 }; 78 79 enum { 80 MLX5_MAX_PORTS = 2, 81 }; 82 83 enum { 84 MLX5_EQ_VEC_PAGES = 0, 85 MLX5_EQ_VEC_CMD = 1, 86 MLX5_EQ_VEC_ASYNC = 2, 87 MLX5_EQ_VEC_COMP_BASE, 88 }; 89 90 enum { 91 MLX5_ATOMIC_MODE_OFF = 16, 92 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 99 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 100 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 101 }; 102 103 enum { 104 MLX5_ATOMIC_MODE_DCT_OFF = 20, 105 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 112 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 113 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 114 }; 115 116 enum { 117 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 118 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 119 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 120 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 121 }; 122 123 enum { 124 MLX5_REG_QPTS = 0x4002, 125 MLX5_REG_QETCR = 0x4005, 126 MLX5_REG_QPDP = 0x4007, 127 MLX5_REG_QTCT = 0x400A, 128 MLX5_REG_QPDPM = 0x4013, 129 MLX5_REG_QHLL = 0x4016, 130 MLX5_REG_QCAM = 0x4019, 131 MLX5_REG_DCBX_PARAM = 0x4020, 132 MLX5_REG_DCBX_APP = 0x4021, 133 MLX5_REG_FPGA_CAP = 0x4022, 134 MLX5_REG_FPGA_CTRL = 0x4023, 135 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 136 MLX5_REG_FPGA_SHELL_CNTR = 0x4025, 137 MLX5_REG_PCAP = 0x5001, 138 MLX5_REG_PMLP = 0x5002, 139 MLX5_REG_PMTU = 0x5003, 140 MLX5_REG_PTYS = 0x5004, 141 MLX5_REG_PAOS = 0x5006, 142 MLX5_REG_PFCC = 0x5007, 143 MLX5_REG_PPCNT = 0x5008, 144 MLX5_REG_PUDE = 0x5009, 145 MLX5_REG_PPTB = 0x500B, 146 MLX5_REG_PBMC = 0x500C, 147 MLX5_REG_PELC = 0x500E, 148 MLX5_REG_PVLC = 0x500F, 149 MLX5_REG_PMPE = 0x5010, 150 MLX5_REG_PMAOS = 0x5012, 151 MLX5_REG_PPLM = 0x5023, 152 MLX5_REG_PDDR = 0x5031, 153 MLX5_REG_PBSR = 0x5038, 154 MLX5_REG_PCAM = 0x507f, 155 MLX5_REG_NODE_DESC = 0x6001, 156 MLX5_REG_HOST_ENDIANNESS = 0x7004, 157 MLX5_REG_MTMP = 0x900a, 158 MLX5_REG_MCIA = 0x9014, 159 MLX5_REG_MFRL = 0x9028, 160 MLX5_REG_MPCNT = 0x9051, 161 MLX5_REG_MCQI = 0x9061, 162 MLX5_REG_MCC = 0x9062, 163 MLX5_REG_MCDA = 0x9063, 164 MLX5_REG_MCAM = 0x907f, 165 }; 166 167 enum dbg_rsc_type { 168 MLX5_DBG_RSC_QP, 169 MLX5_DBG_RSC_EQ, 170 MLX5_DBG_RSC_CQ, 171 }; 172 173 enum { 174 MLX5_INTERFACE_PROTOCOL_IB = 0, 175 MLX5_INTERFACE_PROTOCOL_ETH = 1, 176 MLX5_INTERFACE_NUMBER = 2, 177 }; 178 179 struct mlx5_field_desc { 180 int i; 181 }; 182 183 struct mlx5_rsc_debug { 184 struct mlx5_core_dev *dev; 185 void *object; 186 enum dbg_rsc_type type; 187 struct mlx5_field_desc fields[0]; 188 }; 189 190 enum mlx5_dev_event { 191 MLX5_DEV_EVENT_SYS_ERROR, 192 MLX5_DEV_EVENT_PORT_UP, 193 MLX5_DEV_EVENT_PORT_DOWN, 194 MLX5_DEV_EVENT_PORT_INITIALIZED, 195 MLX5_DEV_EVENT_LID_CHANGE, 196 MLX5_DEV_EVENT_PKEY_CHANGE, 197 MLX5_DEV_EVENT_GUID_CHANGE, 198 MLX5_DEV_EVENT_CLIENT_REREG, 199 MLX5_DEV_EVENT_VPORT_CHANGE, 200 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 201 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 202 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 203 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 204 }; 205 206 enum mlx5_port_status { 207 MLX5_PORT_UP = 1 << 0, 208 MLX5_PORT_DOWN = 1 << 1, 209 }; 210 211 enum { 212 MLX5_VSC_SPACE_SUPPORTED = 0x1, 213 MLX5_VSC_SPACE_OFFSET = 0x4, 214 MLX5_VSC_COUNTER_OFFSET = 0x8, 215 MLX5_VSC_SEMA_OFFSET = 0xC, 216 MLX5_VSC_ADDR_OFFSET = 0x10, 217 MLX5_VSC_DATA_OFFSET = 0x14, 218 MLX5_VSC_MAX_RETRIES = 0x1000, 219 }; 220 221 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 222 223 struct mlx5_cmd_first { 224 __be32 data[4]; 225 }; 226 227 struct cache_ent; 228 struct mlx5_fw_page { 229 union { 230 struct rb_node rb_node; 231 struct list_head list; 232 }; 233 struct mlx5_cmd_first first; 234 struct mlx5_core_dev *dev; 235 bus_dmamap_t dma_map; 236 bus_addr_t dma_addr; 237 void *virt_addr; 238 struct cache_ent *cache; 239 u32 numpages; 240 u16 load_done; 241 #define MLX5_LOAD_ST_NONE 0 242 #define MLX5_LOAD_ST_SUCCESS 1 243 #define MLX5_LOAD_ST_FAILURE 2 244 u16 func_id; 245 }; 246 #define mlx5_cmd_msg mlx5_fw_page 247 248 struct mlx5_cmd_debug { 249 void *in_msg; 250 void *out_msg; 251 u8 status; 252 u16 inlen; 253 u16 outlen; 254 }; 255 256 struct cache_ent { 257 /* protect block chain allocations 258 */ 259 spinlock_t lock; 260 struct list_head head; 261 }; 262 263 struct cmd_msg_cache { 264 struct cache_ent large; 265 struct cache_ent med; 266 267 }; 268 269 struct mlx5_traffic_counter { 270 u64 packets; 271 u64 octets; 272 }; 273 274 enum mlx5_cmd_mode { 275 MLX5_CMD_MODE_POLLING, 276 MLX5_CMD_MODE_EVENTS 277 }; 278 279 struct mlx5_cmd_stats { 280 u64 sum; 281 u64 n; 282 /* protect command average calculations */ 283 spinlock_t lock; 284 }; 285 286 struct mlx5_cmd { 287 struct mlx5_fw_page *cmd_page; 288 bus_dma_tag_t dma_tag; 289 struct sx dma_sx; 290 struct mtx dma_mtx; 291 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 292 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 293 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 294 struct cv dma_cv; 295 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 296 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 297 void *cmd_buf; 298 dma_addr_t dma; 299 u16 cmdif_rev; 300 u8 log_sz; 301 u8 log_stride; 302 int max_reg_cmds; 303 int events; 304 u32 __iomem *vector; 305 306 /* protect command queue allocations 307 */ 308 spinlock_t alloc_lock; 309 310 /* protect token allocations 311 */ 312 spinlock_t token_lock; 313 u8 token; 314 unsigned long bitmask; 315 struct semaphore sem; 316 struct semaphore pages_sem; 317 enum mlx5_cmd_mode mode; 318 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS]; 319 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS]; 320 struct mlx5_cmd_debug dbg; 321 struct cmd_msg_cache cache; 322 int checksum_disabled; 323 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 324 }; 325 326 struct mlx5_port_caps { 327 int gid_table_len; 328 int pkey_table_len; 329 u8 ext_port_cap; 330 }; 331 332 struct mlx5_buf { 333 bus_dma_tag_t dma_tag; 334 bus_dmamap_t dma_map; 335 struct mlx5_core_dev *dev; 336 struct { 337 void *buf; 338 } direct; 339 u64 *page_list; 340 int npages; 341 int size; 342 u8 page_shift; 343 u8 load_done; 344 }; 345 346 struct mlx5_frag_buf { 347 struct mlx5_buf_list *frags; 348 int npages; 349 int size; 350 u8 page_shift; 351 }; 352 353 struct mlx5_eq { 354 struct mlx5_core_dev *dev; 355 __be32 __iomem *doorbell; 356 u32 cons_index; 357 struct mlx5_buf buf; 358 int size; 359 u8 irqn; 360 u8 eqn; 361 int nent; 362 u64 mask; 363 struct list_head list; 364 int index; 365 struct mlx5_rsc_debug *dbg; 366 }; 367 368 struct mlx5_core_psv { 369 u32 psv_idx; 370 struct psv_layout { 371 u32 pd; 372 u16 syndrome; 373 u16 reserved; 374 u16 bg; 375 u16 app_tag; 376 u32 ref_tag; 377 } psv; 378 }; 379 380 struct mlx5_core_sig_ctx { 381 struct mlx5_core_psv psv_memory; 382 struct mlx5_core_psv psv_wire; 383 struct ib_sig_err err_item; 384 bool sig_status_checked; 385 bool sig_err_exists; 386 u32 sigerr_count; 387 }; 388 389 enum { 390 MLX5_MKEY_MR = 1, 391 MLX5_MKEY_MW, 392 MLX5_MKEY_INDIRECT_DEVX, 393 }; 394 395 struct mlx5_core_mkey { 396 u64 iova; 397 u64 size; 398 u32 key; 399 u32 pd; 400 u32 type; 401 }; 402 403 enum mlx5_res_type { 404 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 405 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 406 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 407 MLX5_RES_SRQ = 3, 408 MLX5_RES_XSRQ = 4, 409 MLX5_RES_XRQ = 5, 410 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 411 }; 412 413 struct mlx5_core_rsc_common { 414 enum mlx5_res_type res; 415 atomic_t refcount; 416 struct completion free; 417 }; 418 419 struct mlx5_uars_page { 420 void __iomem *map; 421 bool wc; 422 u32 index; 423 struct list_head list; 424 unsigned int bfregs; 425 unsigned long *reg_bitmap; /* for non fast path bf regs */ 426 unsigned long *fp_bitmap; 427 unsigned int reg_avail; 428 unsigned int fp_avail; 429 struct kref ref_count; 430 struct mlx5_core_dev *mdev; 431 }; 432 433 struct mlx5_bfreg_head { 434 /* protect blue flame registers allocations */ 435 struct mutex lock; 436 struct list_head list; 437 }; 438 439 struct mlx5_bfreg_data { 440 struct mlx5_bfreg_head reg_head; 441 struct mlx5_bfreg_head wc_head; 442 }; 443 444 struct mlx5_sq_bfreg { 445 void __iomem *map; 446 struct mlx5_uars_page *up; 447 bool wc; 448 u32 index; 449 unsigned int offset; 450 }; 451 452 struct mlx5_core_srq { 453 struct mlx5_core_rsc_common common; /* must be first */ 454 u32 srqn; 455 int max; 456 size_t max_gs; 457 size_t max_avail_gather; 458 int wqe_shift; 459 void (*event)(struct mlx5_core_srq *, int); 460 atomic_t refcount; 461 struct completion free; 462 }; 463 464 struct mlx5_ib_dev; 465 struct mlx5_eq_table { 466 void __iomem *update_ci; 467 void __iomem *update_arm_ci; 468 struct list_head comp_eqs_list; 469 struct mlx5_eq pages_eq; 470 struct mlx5_eq async_eq; 471 struct mlx5_eq cmd_eq; 472 int num_comp_vectors; 473 spinlock_t lock; /* protect EQs list */ 474 struct mlx5_ib_dev *dev; /* for devx event notifier */ 475 bool (*cb)(struct mlx5_core_dev *mdev, 476 uint8_t event_type, void *data); 477 }; 478 479 struct mlx5_core_health { 480 struct mlx5_health_buffer __iomem *health; 481 __be32 __iomem *health_counter; 482 struct timer_list timer; 483 u32 prev; 484 int miss_counter; 485 u32 fatal_error; 486 struct workqueue_struct *wq_watchdog; 487 struct work_struct work_watchdog; 488 /* wq spinlock to synchronize draining */ 489 spinlock_t wq_lock; 490 struct workqueue_struct *wq; 491 unsigned long flags; 492 struct work_struct work; 493 struct delayed_work recover_work; 494 unsigned int last_reset_req; 495 struct work_struct work_cmd_completion; 496 struct workqueue_struct *wq_cmd; 497 }; 498 499 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 500 501 struct mlx5_cq_linear_array_entry { 502 struct mlx5_core_cq * volatile cq; 503 }; 504 505 struct mlx5_cq_table { 506 /* protect radix tree 507 */ 508 spinlock_t writerlock; 509 atomic_t writercount; 510 struct radix_tree_root tree; 511 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 512 }; 513 514 struct mlx5_qp_table { 515 /* protect radix tree 516 */ 517 spinlock_t lock; 518 struct radix_tree_root tree; 519 }; 520 521 struct mlx5_srq_table { 522 /* protect radix tree 523 */ 524 spinlock_t lock; 525 struct radix_tree_root tree; 526 }; 527 528 struct mlx5_mr_table { 529 /* protect radix tree 530 */ 531 spinlock_t lock; 532 struct radix_tree_root tree; 533 }; 534 535 #ifdef RATELIMIT 536 struct mlx5_rl_entry { 537 u32 rate; 538 u16 burst; 539 u16 index; 540 u32 qos_handle; /* schedule queue handle */ 541 u32 refcount; 542 }; 543 544 struct mlx5_rl_table { 545 struct mutex rl_lock; 546 u16 max_size; 547 u32 max_rate; 548 u32 min_rate; 549 struct mlx5_rl_entry *rl_entry; 550 }; 551 #endif 552 553 struct mlx5_pme_stats { 554 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 555 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 556 }; 557 558 struct mlx5_priv { 559 char name[MLX5_MAX_NAME_LEN]; 560 struct mlx5_eq_table eq_table; 561 struct msix_entry *msix_arr; 562 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 563 int disable_irqs; 564 565 /* pages stuff */ 566 struct workqueue_struct *pg_wq; 567 struct rb_root page_root; 568 s64 fw_pages; 569 atomic_t reg_pages; 570 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 571 struct mlx5_core_health health; 572 573 struct mlx5_srq_table srq_table; 574 575 /* start: qp staff */ 576 struct mlx5_qp_table qp_table; 577 578 /* end: qp staff */ 579 580 /* start: cq staff */ 581 struct mlx5_cq_table cq_table; 582 /* end: cq staff */ 583 584 /* start: mr staff */ 585 struct mlx5_mr_table mr_table; 586 /* end: mr staff */ 587 588 /* start: alloc staff */ 589 int numa_node; 590 591 struct mutex pgdir_mutex; 592 struct list_head pgdir_list; 593 /* end: alloc staff */ 594 595 /* protect mkey key part */ 596 spinlock_t mkey_lock; 597 u8 mkey_key; 598 599 struct list_head dev_list; 600 struct list_head ctx_list; 601 spinlock_t ctx_lock; 602 unsigned long pci_dev_data; 603 #ifdef RATELIMIT 604 struct mlx5_rl_table rl_table; 605 #endif 606 struct mlx5_pme_stats pme_stats; 607 608 struct mlx5_eswitch *eswitch; 609 610 struct mlx5_bfreg_data bfregs; 611 struct mlx5_uars_page *uar; 612 }; 613 614 enum mlx5_device_state { 615 MLX5_DEVICE_STATE_UP, 616 MLX5_DEVICE_STATE_INTERNAL_ERROR, 617 }; 618 619 enum mlx5_interface_state { 620 MLX5_INTERFACE_STATE_UP = 0x1, 621 MLX5_INTERFACE_STATE_TEARDOWN = 0x2, 622 }; 623 624 enum mlx5_pci_status { 625 MLX5_PCI_STATUS_DISABLED, 626 MLX5_PCI_STATUS_ENABLED, 627 }; 628 629 #define MLX5_MAX_RESERVED_GIDS 8 630 631 struct mlx5_rsvd_gids { 632 unsigned int start; 633 unsigned int count; 634 struct ida ida; 635 }; 636 637 struct mlx5_special_contexts { 638 int resd_lkey; 639 }; 640 641 struct mlx5_diag_cnt_id { 642 u16 id; 643 bool enabled; 644 }; 645 646 struct mlx5_diag_cnt { 647 #define DIAG_LOCK(dc) mutex_lock(&(dc)->lock) 648 #define DIAG_UNLOCK(dc) mutex_unlock(&(dc)->lock) 649 struct mutex lock; 650 struct sysctl_ctx_list sysctl_ctx; 651 struct mlx5_diag_cnt_id *cnt_id; 652 u16 num_of_samples; 653 u16 sample_index; 654 u8 num_cnt_id; 655 u8 log_num_of_samples; 656 u8 log_sample_period; 657 u8 flag; 658 u8 ready; 659 }; 660 661 struct mlx5_flow_root_namespace; 662 struct mlx5_core_dev { 663 struct pci_dev *pdev; 664 /* sync pci state */ 665 struct mutex pci_status_mutex; 666 enum mlx5_pci_status pci_status; 667 char board_id[MLX5_BOARD_ID_LEN]; 668 struct mlx5_cmd cmd; 669 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 670 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 671 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 672 struct { 673 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 674 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 675 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 676 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 677 } caps; 678 phys_addr_t iseg_base; 679 struct mlx5_init_seg __iomem *iseg; 680 enum mlx5_device_state state; 681 /* sync interface state */ 682 struct mutex intf_state_mutex; 683 unsigned long intf_state; 684 void (*event) (struct mlx5_core_dev *dev, 685 enum mlx5_dev_event event, 686 unsigned long param); 687 struct mlx5_priv priv; 688 struct mlx5_profile *profile; 689 atomic_t num_qps; 690 struct mlx5_diag_cnt diag_cnt; 691 u32 vsc_addr; 692 u32 issi; 693 struct mlx5_special_contexts special_contexts; 694 unsigned int module_status[MLX5_MAX_PORTS]; 695 struct mlx5_flow_root_namespace *root_ns; 696 struct mlx5_flow_root_namespace *fdb_root_ns; 697 struct mlx5_flow_root_namespace *esw_egress_root_ns; 698 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 699 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 700 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 701 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 702 struct mlx5_crspace_regmap *dump_rege; 703 uint32_t *dump_data; 704 unsigned dump_size; 705 bool dump_valid; 706 bool dump_copyout; 707 struct mtx dump_lock; 708 709 struct sysctl_ctx_list sysctl_ctx; 710 int msix_eqvec; 711 int pwr_status; 712 int pwr_value; 713 714 struct { 715 struct mlx5_rsvd_gids reserved_gids; 716 atomic_t roce_en; 717 } roce; 718 719 struct { 720 spinlock_t spinlock; 721 #define MLX5_MPFS_TABLE_MAX 32 722 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)]; 723 } mpfs; 724 #ifdef CONFIG_MLX5_FPGA 725 struct mlx5_fpga_device *fpga; 726 #endif 727 }; 728 729 enum { 730 MLX5_WOL_DISABLE = 0, 731 MLX5_WOL_SECURED_MAGIC = 1 << 1, 732 MLX5_WOL_MAGIC = 1 << 2, 733 MLX5_WOL_ARP = 1 << 3, 734 MLX5_WOL_BROADCAST = 1 << 4, 735 MLX5_WOL_MULTICAST = 1 << 5, 736 MLX5_WOL_UNICAST = 1 << 6, 737 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 738 }; 739 740 struct mlx5_db { 741 __be32 *db; 742 union { 743 struct mlx5_db_pgdir *pgdir; 744 struct mlx5_ib_user_db_page *user_page; 745 } u; 746 dma_addr_t dma; 747 int index; 748 }; 749 750 struct mlx5_net_counters { 751 u64 packets; 752 u64 octets; 753 }; 754 755 struct mlx5_ptys_reg { 756 u8 an_dis_admin; 757 u8 an_dis_ap; 758 u8 local_port; 759 u8 proto_mask; 760 u32 eth_proto_cap; 761 u16 ib_link_width_cap; 762 u16 ib_proto_cap; 763 u32 eth_proto_admin; 764 u16 ib_link_width_admin; 765 u16 ib_proto_admin; 766 u32 eth_proto_oper; 767 u16 ib_link_width_oper; 768 u16 ib_proto_oper; 769 u32 eth_proto_lp_advertise; 770 }; 771 772 struct mlx5_pvlc_reg { 773 u8 local_port; 774 u8 vl_hw_cap; 775 u8 vl_admin; 776 u8 vl_operational; 777 }; 778 779 struct mlx5_pmtu_reg { 780 u8 local_port; 781 u16 max_mtu; 782 u16 admin_mtu; 783 u16 oper_mtu; 784 }; 785 786 struct mlx5_vport_counters { 787 struct mlx5_net_counters received_errors; 788 struct mlx5_net_counters transmit_errors; 789 struct mlx5_net_counters received_ib_unicast; 790 struct mlx5_net_counters transmitted_ib_unicast; 791 struct mlx5_net_counters received_ib_multicast; 792 struct mlx5_net_counters transmitted_ib_multicast; 793 struct mlx5_net_counters received_eth_broadcast; 794 struct mlx5_net_counters transmitted_eth_broadcast; 795 struct mlx5_net_counters received_eth_unicast; 796 struct mlx5_net_counters transmitted_eth_unicast; 797 struct mlx5_net_counters received_eth_multicast; 798 struct mlx5_net_counters transmitted_eth_multicast; 799 }; 800 801 enum { 802 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 803 }; 804 805 struct mlx5_core_dct { 806 struct mlx5_core_rsc_common common; /* must be first */ 807 void (*event)(struct mlx5_core_dct *, int); 808 int dctn; 809 struct completion drained; 810 struct mlx5_rsc_debug *dbg; 811 int pid; 812 u16 uid; 813 }; 814 815 enum { 816 MLX5_PTYS_IB = 1 << 0, 817 MLX5_PTYS_EN = 1 << 2, 818 }; 819 820 struct mlx5_db_pgdir { 821 struct list_head list; 822 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 823 struct mlx5_fw_page *fw_page; 824 __be32 *db_page; 825 dma_addr_t db_dma; 826 }; 827 828 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 829 830 struct mlx5_cmd_work_ent { 831 struct mlx5_cmd_msg *in; 832 struct mlx5_cmd_msg *out; 833 int uin_size; 834 void *uout; 835 int uout_size; 836 mlx5_cmd_cbk_t callback; 837 struct delayed_work cb_timeout_work; 838 void *context; 839 int idx; 840 struct completion done; 841 struct mlx5_cmd *cmd; 842 struct work_struct work; 843 struct mlx5_cmd_layout *lay; 844 int ret; 845 int page_queue; 846 u8 status; 847 u8 token; 848 u64 ts1; 849 u64 ts2; 850 u16 op; 851 u8 busy; 852 bool polling; 853 }; 854 855 struct mlx5_pas { 856 u64 pa; 857 u8 log_sz; 858 }; 859 860 enum port_state_policy { 861 MLX5_POLICY_DOWN = 0, 862 MLX5_POLICY_UP = 1, 863 MLX5_POLICY_FOLLOW = 2, 864 MLX5_POLICY_INVALID = 0xffffffff 865 }; 866 867 static inline void * 868 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 869 { 870 return ((char *)buf->direct.buf + offset); 871 } 872 873 874 extern struct workqueue_struct *mlx5_core_wq; 875 876 #define STRUCT_FIELD(header, field) \ 877 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 878 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 879 880 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 881 { 882 return pci_get_drvdata(pdev); 883 } 884 885 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 886 { 887 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 888 } 889 890 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 891 { 892 return ioread32be(&dev->iseg->fw_rev) >> 16; 893 } 894 895 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 896 { 897 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 898 } 899 900 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 901 { 902 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 903 } 904 905 static inline int mlx5_get_gid_table_len(u16 param) 906 { 907 if (param > 4) { 908 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 909 return 0; 910 } 911 912 return 8 * (1 << param); 913 } 914 915 static inline void *mlx5_vzalloc(unsigned long size) 916 { 917 void *rtn; 918 919 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 920 return rtn; 921 } 922 923 static inline void *mlx5_vmalloc(unsigned long size) 924 { 925 void *rtn; 926 927 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 928 if (!rtn) 929 rtn = vmalloc(size); 930 return rtn; 931 } 932 933 static inline u32 mlx5_base_mkey(const u32 key) 934 { 935 return key & 0xffffff00u; 936 } 937 938 int mlx5_cmd_init(struct mlx5_core_dev *dev); 939 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 940 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 941 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 942 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 943 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 944 945 struct mlx5_async_ctx { 946 struct mlx5_core_dev *dev; 947 atomic_t num_inflight; 948 struct wait_queue_head wait; 949 }; 950 951 struct mlx5_async_work; 952 953 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 954 955 struct mlx5_async_work { 956 struct mlx5_async_ctx *ctx; 957 mlx5_async_cbk_t user_callback; 958 }; 959 960 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 961 struct mlx5_async_ctx *ctx); 962 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 963 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 964 void *out, int out_size, mlx5_async_cbk_t callback, 965 struct mlx5_async_work *work); 966 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 967 int out_size); 968 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 969 void *out, int out_size); 970 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 971 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 972 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 973 bool map_wc, bool fast_path); 974 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 975 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 976 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 977 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 978 int mlx5_health_init(struct mlx5_core_dev *dev); 979 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 980 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 981 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 982 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 983 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 984 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev); 985 986 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 987 struct mlx5_buf *buf); 988 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 989 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 990 struct mlx5_srq_attr *in); 991 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 992 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 993 struct mlx5_srq_attr *out); 994 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 995 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 996 u16 lwm, int is_srq); 997 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 998 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 999 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 1000 struct mlx5_core_mkey *mkey, 1001 struct mlx5_async_ctx *async_ctx, u32 *in, 1002 int inlen, u32 *out, int outlen, 1003 mlx5_async_cbk_t callback, 1004 struct mlx5_async_work *context); 1005 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 1006 struct mlx5_core_mkey *mr, 1007 u32 *in, int inlen); 1008 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey); 1009 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 1010 u32 *out, int outlen); 1011 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mr, 1012 u32 *mkey); 1013 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn, u16 uid); 1014 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid); 1015 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 1016 u16 opmod, u8 port); 1017 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 1018 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 1019 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 1020 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 1021 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 1022 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 1023 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 1024 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 1025 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 1026 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 1027 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 1028 s32 npages); 1029 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 1030 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 1031 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 1032 void mlx5_register_debugfs(void); 1033 void mlx5_unregister_debugfs(void); 1034 int mlx5_eq_init(struct mlx5_core_dev *dev); 1035 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 1036 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 1037 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); 1038 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1039 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1040 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1041 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode); 1042 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 1043 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 1044 int nent, u64 mask); 1045 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1046 int mlx5_start_eqs(struct mlx5_core_dev *dev); 1047 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 1048 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 1049 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1050 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1051 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 1052 u64 addr); 1053 1054 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1055 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1056 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1057 int size_in, void *data_out, int size_out, 1058 u16 reg_num, int arg, int write); 1059 1060 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1061 1062 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1063 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1064 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1065 u32 *out, int outlen); 1066 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1067 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1068 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1069 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1070 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1071 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1072 1073 static inline struct domainset * 1074 mlx5_dev_domainset(struct mlx5_core_dev *mdev) 1075 { 1076 return (linux_get_vm_domain_set(mdev->priv.numa_node)); 1077 } 1078 1079 const char *mlx5_command_str(int command); 1080 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1081 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1082 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1083 int npsvs, u32 *sig_index); 1084 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1085 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1086 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1087 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1088 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1089 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1090 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1091 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1092 struct mlx5_pvlc_reg *pvlc, int write); 1093 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1094 struct mlx5_ptys_reg *ptys, int write); 1095 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1096 struct mlx5_pmtu_reg *pmtu, int write); 1097 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1098 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1099 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1100 int priority, int *is_enable); 1101 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1102 int priority, int enable); 1103 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1104 void *out, int out_size); 1105 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1106 void *in, int in_size); 1107 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1108 void *out, int out_size); 1109 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1110 int in_size); 1111 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1112 u8 num_of_samples, u16 sample_index, 1113 void *out, int out_size); 1114 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1115 int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1116 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1117 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1118 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected); 1119 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1120 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1121 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1122 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1123 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev, 1124 u16 *p_power, u8 *p_status); 1125 1126 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1127 { 1128 return mkey >> 8; 1129 } 1130 1131 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1132 { 1133 return mkey_idx << 8; 1134 } 1135 1136 static inline u8 mlx5_mkey_variant(u32 mkey) 1137 { 1138 return mkey & 0xff; 1139 } 1140 1141 enum { 1142 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1143 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1144 }; 1145 1146 enum { 1147 MAX_MR_CACHE_ENTRIES = 15, 1148 }; 1149 1150 struct mlx5_interface { 1151 void * (*add)(struct mlx5_core_dev *dev); 1152 void (*remove)(struct mlx5_core_dev *dev, void *context); 1153 void (*event)(struct mlx5_core_dev *dev, void *context, 1154 enum mlx5_dev_event event, unsigned long param); 1155 void * (*get_dev)(void *context); 1156 int protocol; 1157 struct list_head list; 1158 }; 1159 1160 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1161 int mlx5_register_interface(struct mlx5_interface *intf); 1162 void mlx5_unregister_interface(struct mlx5_interface *intf); 1163 1164 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1165 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1166 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1167 const u8 *mac, bool vlan, u16 vlan_id); 1168 1169 struct mlx5_profile { 1170 u64 mask; 1171 u8 log_max_qp; 1172 struct { 1173 int size; 1174 int limit; 1175 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1176 }; 1177 1178 enum { 1179 MLX5_PCI_DEV_IS_VF = 1 << 0, 1180 }; 1181 1182 enum { 1183 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1184 }; 1185 1186 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1187 { 1188 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1189 } 1190 #ifdef RATELIMIT 1191 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1192 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1193 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index); 1194 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst); 1195 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst); 1196 int mlx5e_query_rate_limit_cmd(struct mlx5_core_dev *dev, u16 index, u32 *scq_handle); 1197 1198 static inline u32 mlx5_rl_get_scq_handle(struct mlx5_core_dev *dev, uint16_t index) 1199 { 1200 KASSERT(index > 0, 1201 ("invalid rate index for sq remap, failed retrieving SCQ handle")); 1202 1203 return (dev->priv.rl_table.rl_entry[index - 1].qos_handle); 1204 } 1205 1206 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1207 { 1208 return !!(dev->priv.rl_table.max_size); 1209 } 1210 #endif 1211 1212 void mlx5_disable_interrupts(struct mlx5_core_dev *); 1213 void mlx5_poll_interrupts(struct mlx5_core_dev *); 1214 1215 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev) 1216 { 1217 return !MLX5_CAP_ROCE(dev, qp_ts_format) ? 1218 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 1219 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 1220 } 1221 1222 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev) 1223 { 1224 return !MLX5_CAP_GEN(dev, rq_ts_format) ? 1225 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING : 1226 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT; 1227 } 1228 1229 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev) 1230 { 1231 return !MLX5_CAP_GEN(dev, sq_ts_format) ? 1232 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING : 1233 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT; 1234 } 1235 1236 #endif /* MLX5_DRIVER_H */ 1237