1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include <linux/kernel.h> 32 #include <linux/completion.h> 33 #include <linux/pci.h> 34 #include <linux/cache.h> 35 #include <linux/rbtree.h> 36 #include <linux/if_ether.h> 37 #include <linux/semaphore.h> 38 #include <linux/slab.h> 39 #include <linux/vmalloc.h> 40 #include <linux/radix-tree.h> 41 42 #include <dev/mlx5/device.h> 43 #include <dev/mlx5/doorbell.h> 44 45 #define MLX5_QCOUNTER_SETS_NETDEV 64 46 #define MLX5_MAX_NUMBER_OF_VFS 128 47 48 enum { 49 MLX5_BOARD_ID_LEN = 64, 50 MLX5_MAX_NAME_LEN = 16, 51 }; 52 53 enum { 54 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 55 MLX5_CMD_WQ_MAX_NAME = 32, 56 }; 57 58 enum { 59 CMD_OWNER_SW = 0x0, 60 CMD_OWNER_HW = 0x1, 61 CMD_STATUS_SUCCESS = 0, 62 }; 63 64 enum mlx5_sqp_t { 65 MLX5_SQP_SMI = 0, 66 MLX5_SQP_GSI = 1, 67 MLX5_SQP_IEEE_1588 = 2, 68 MLX5_SQP_SNIFFER = 3, 69 MLX5_SQP_SYNC_UMR = 4, 70 }; 71 72 enum { 73 MLX5_MAX_PORTS = 2, 74 }; 75 76 enum { 77 MLX5_EQ_VEC_PAGES = 0, 78 MLX5_EQ_VEC_CMD = 1, 79 MLX5_EQ_VEC_ASYNC = 2, 80 MLX5_EQ_VEC_COMP_BASE, 81 }; 82 83 enum { 84 MLX5_MAX_IRQ_NAME = 32 85 }; 86 87 enum { 88 MLX5_ATOMIC_MODE_OFF = 16, 89 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 90 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 91 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 98 }; 99 100 enum { 101 MLX5_ATOMIC_MODE_DCT_OFF = 20, 102 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 103 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 104 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 111 }; 112 113 enum { 114 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 115 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 116 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 117 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 118 }; 119 120 enum { 121 MLX5_REG_QETCR = 0x4005, 122 MLX5_REG_QPDP = 0x4007, 123 MLX5_REG_QTCT = 0x400A, 124 MLX5_REG_QHLL = 0x4016, 125 MLX5_REG_DCBX_PARAM = 0x4020, 126 MLX5_REG_DCBX_APP = 0x4021, 127 MLX5_REG_PCAP = 0x5001, 128 MLX5_REG_PMTU = 0x5003, 129 MLX5_REG_PTYS = 0x5004, 130 MLX5_REG_PAOS = 0x5006, 131 MLX5_REG_PFCC = 0x5007, 132 MLX5_REG_PPCNT = 0x5008, 133 MLX5_REG_PMAOS = 0x5012, 134 MLX5_REG_PUDE = 0x5009, 135 MLX5_REG_PPTB = 0x500B, 136 MLX5_REG_PBMC = 0x500C, 137 MLX5_REG_PMPE = 0x5010, 138 MLX5_REG_PELC = 0x500e, 139 MLX5_REG_PVLC = 0x500f, 140 MLX5_REG_PMLP = 0x5002, 141 MLX5_REG_NODE_DESC = 0x6001, 142 MLX5_REG_HOST_ENDIANNESS = 0x7004, 143 MLX5_REG_MCIA = 0x9014, 144 MLX5_REG_MPCNT = 0x9051, 145 }; 146 147 enum dbg_rsc_type { 148 MLX5_DBG_RSC_QP, 149 MLX5_DBG_RSC_EQ, 150 MLX5_DBG_RSC_CQ, 151 }; 152 153 enum { 154 MLX5_INTERFACE_PROTOCOL_IB = 0, 155 MLX5_INTERFACE_PROTOCOL_ETH = 1, 156 MLX5_INTERFACE_NUMBER = 2, 157 }; 158 159 struct mlx5_field_desc { 160 struct dentry *dent; 161 int i; 162 }; 163 164 struct mlx5_rsc_debug { 165 struct mlx5_core_dev *dev; 166 void *object; 167 enum dbg_rsc_type type; 168 struct dentry *root; 169 struct mlx5_field_desc fields[0]; 170 }; 171 172 enum mlx5_dev_event { 173 MLX5_DEV_EVENT_SYS_ERROR, 174 MLX5_DEV_EVENT_PORT_UP, 175 MLX5_DEV_EVENT_PORT_DOWN, 176 MLX5_DEV_EVENT_PORT_INITIALIZED, 177 MLX5_DEV_EVENT_LID_CHANGE, 178 MLX5_DEV_EVENT_PKEY_CHANGE, 179 MLX5_DEV_EVENT_GUID_CHANGE, 180 MLX5_DEV_EVENT_CLIENT_REREG, 181 MLX5_DEV_EVENT_VPORT_CHANGE, 182 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 183 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 184 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 185 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 186 }; 187 188 enum mlx5_port_status { 189 MLX5_PORT_UP = 1 << 0, 190 MLX5_PORT_DOWN = 1 << 1, 191 }; 192 193 enum mlx5_link_mode { 194 MLX5_1000BASE_CX_SGMII = 0, 195 MLX5_1000BASE_KX = 1, 196 MLX5_10GBASE_CX4 = 2, 197 MLX5_10GBASE_KX4 = 3, 198 MLX5_10GBASE_KR = 4, 199 MLX5_20GBASE_KR2 = 5, 200 MLX5_40GBASE_CR4 = 6, 201 MLX5_40GBASE_KR4 = 7, 202 MLX5_56GBASE_R4 = 8, 203 MLX5_10GBASE_CR = 12, 204 MLX5_10GBASE_SR = 13, 205 MLX5_10GBASE_ER = 14, 206 MLX5_40GBASE_SR4 = 15, 207 MLX5_40GBASE_LR4 = 16, 208 MLX5_100GBASE_CR4 = 20, 209 MLX5_100GBASE_SR4 = 21, 210 MLX5_100GBASE_KR4 = 22, 211 MLX5_100GBASE_LR4 = 23, 212 MLX5_100BASE_TX = 24, 213 MLX5_1000BASE_T = 25, 214 MLX5_10GBASE_T = 26, 215 MLX5_25GBASE_CR = 27, 216 MLX5_25GBASE_KR = 28, 217 MLX5_25GBASE_SR = 29, 218 MLX5_50GBASE_CR2 = 30, 219 MLX5_50GBASE_KR2 = 31, 220 MLX5_LINK_MODES_NUMBER, 221 }; 222 223 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 224 225 struct mlx5_uuar_info { 226 struct mlx5_uar *uars; 227 int num_uars; 228 int num_low_latency_uuars; 229 unsigned long *bitmap; 230 unsigned int *count; 231 struct mlx5_bf *bfs; 232 233 /* 234 * protect uuar allocation data structs 235 */ 236 struct mutex lock; 237 u32 ver; 238 }; 239 240 struct mlx5_bf { 241 void __iomem *reg; 242 void __iomem *regreg; 243 int buf_size; 244 struct mlx5_uar *uar; 245 unsigned long offset; 246 int need_lock; 247 /* protect blue flame buffer selection when needed 248 */ 249 spinlock_t lock; 250 251 /* serialize 64 bit writes when done as two 32 bit accesses 252 */ 253 spinlock_t lock32; 254 int uuarn; 255 }; 256 257 struct mlx5_cmd_first { 258 __be32 data[4]; 259 }; 260 261 struct cache_ent; 262 struct mlx5_fw_page { 263 union { 264 struct rb_node rb_node; 265 struct list_head list; 266 }; 267 struct mlx5_cmd_first first; 268 struct mlx5_core_dev *dev; 269 bus_dmamap_t dma_map; 270 bus_addr_t dma_addr; 271 void *virt_addr; 272 struct cache_ent *cache; 273 u32 numpages; 274 u16 load_done; 275 #define MLX5_LOAD_ST_NONE 0 276 #define MLX5_LOAD_ST_SUCCESS 1 277 #define MLX5_LOAD_ST_FAILURE 2 278 u16 func_id; 279 }; 280 #define mlx5_cmd_msg mlx5_fw_page 281 282 struct mlx5_cmd_debug { 283 struct dentry *dbg_root; 284 struct dentry *dbg_in; 285 struct dentry *dbg_out; 286 struct dentry *dbg_outlen; 287 struct dentry *dbg_status; 288 struct dentry *dbg_run; 289 void *in_msg; 290 void *out_msg; 291 u8 status; 292 u16 inlen; 293 u16 outlen; 294 }; 295 296 struct cache_ent { 297 /* protect block chain allocations 298 */ 299 spinlock_t lock; 300 struct list_head head; 301 }; 302 303 struct cmd_msg_cache { 304 struct cache_ent large; 305 struct cache_ent med; 306 307 }; 308 309 struct mlx5_traffic_counter { 310 u64 packets; 311 u64 octets; 312 }; 313 314 struct mlx5_cmd_stats { 315 u64 sum; 316 u64 n; 317 struct dentry *root; 318 struct dentry *avg; 319 struct dentry *count; 320 /* protect command average calculations */ 321 spinlock_t lock; 322 }; 323 324 struct mlx5_cmd { 325 struct mlx5_fw_page *cmd_page; 326 bus_dma_tag_t dma_tag; 327 struct sx dma_sx; 328 struct mtx dma_mtx; 329 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 330 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 331 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 332 struct cv dma_cv; 333 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 334 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 335 void *cmd_buf; 336 dma_addr_t dma; 337 u16 cmdif_rev; 338 u8 log_sz; 339 u8 log_stride; 340 int max_reg_cmds; 341 int events; 342 u32 __iomem *vector; 343 344 /* protect command queue allocations 345 */ 346 spinlock_t alloc_lock; 347 348 /* protect token allocations 349 */ 350 spinlock_t token_lock; 351 u8 token; 352 unsigned long bitmask; 353 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 354 struct workqueue_struct *wq; 355 struct semaphore sem; 356 struct semaphore pages_sem; 357 int mode; 358 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 359 struct mlx5_cmd_debug dbg; 360 struct cmd_msg_cache cache; 361 int checksum_disabled; 362 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 363 int moving_to_polling; 364 }; 365 366 struct mlx5_port_caps { 367 int gid_table_len; 368 int pkey_table_len; 369 u8 ext_port_cap; 370 }; 371 372 struct mlx5_buf { 373 bus_dma_tag_t dma_tag; 374 bus_dmamap_t dma_map; 375 struct mlx5_core_dev *dev; 376 struct { 377 void *buf; 378 } direct; 379 u64 *page_list; 380 int npages; 381 int size; 382 u8 page_shift; 383 u8 load_done; 384 }; 385 386 struct mlx5_eq { 387 struct mlx5_core_dev *dev; 388 __be32 __iomem *doorbell; 389 u32 cons_index; 390 struct mlx5_buf buf; 391 int size; 392 u8 irqn; 393 u8 eqn; 394 int nent; 395 u64 mask; 396 struct list_head list; 397 int index; 398 struct mlx5_rsc_debug *dbg; 399 }; 400 401 struct mlx5_core_psv { 402 u32 psv_idx; 403 struct psv_layout { 404 u32 pd; 405 u16 syndrome; 406 u16 reserved; 407 u16 bg; 408 u16 app_tag; 409 u32 ref_tag; 410 } psv; 411 }; 412 413 struct mlx5_core_sig_ctx { 414 struct mlx5_core_psv psv_memory; 415 struct mlx5_core_psv psv_wire; 416 #if (__FreeBSD_version >= 1100000) 417 struct ib_sig_err err_item; 418 #endif 419 bool sig_status_checked; 420 bool sig_err_exists; 421 u32 sigerr_count; 422 }; 423 424 struct mlx5_core_mr { 425 u64 iova; 426 u64 size; 427 u32 key; 428 u32 pd; 429 }; 430 431 enum mlx5_res_type { 432 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 433 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 434 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 435 MLX5_RES_SRQ = 3, 436 MLX5_RES_XSRQ = 4, 437 MLX5_RES_DCT = 5, 438 }; 439 440 struct mlx5_core_rsc_common { 441 enum mlx5_res_type res; 442 atomic_t refcount; 443 struct completion free; 444 }; 445 446 struct mlx5_core_srq { 447 struct mlx5_core_rsc_common common; /* must be first */ 448 u32 srqn; 449 int max; 450 int max_gs; 451 int max_avail_gather; 452 int wqe_shift; 453 void (*event)(struct mlx5_core_srq *, int); 454 atomic_t refcount; 455 struct completion free; 456 }; 457 458 struct mlx5_eq_table { 459 void __iomem *update_ci; 460 void __iomem *update_arm_ci; 461 struct list_head comp_eqs_list; 462 struct mlx5_eq pages_eq; 463 struct mlx5_eq async_eq; 464 struct mlx5_eq cmd_eq; 465 int num_comp_vectors; 466 /* protect EQs list 467 */ 468 spinlock_t lock; 469 }; 470 471 struct mlx5_uar { 472 u32 index; 473 void __iomem *bf_map; 474 void __iomem *map; 475 }; 476 477 478 struct mlx5_core_health { 479 struct mlx5_health_buffer __iomem *health; 480 __be32 __iomem *health_counter; 481 struct timer_list timer; 482 struct list_head list; 483 u32 prev; 484 int miss_counter; 485 }; 486 487 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 488 489 struct mlx5_cq_linear_array_entry { 490 spinlock_t lock; 491 struct mlx5_core_cq * volatile cq; 492 }; 493 494 struct mlx5_cq_table { 495 /* protect radix tree 496 */ 497 spinlock_t lock; 498 struct radix_tree_root tree; 499 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 500 }; 501 502 struct mlx5_qp_table { 503 /* protect radix tree 504 */ 505 spinlock_t lock; 506 struct radix_tree_root tree; 507 }; 508 509 struct mlx5_srq_table { 510 /* protect radix tree 511 */ 512 spinlock_t lock; 513 struct radix_tree_root tree; 514 }; 515 516 struct mlx5_mr_table { 517 /* protect radix tree 518 */ 519 spinlock_t lock; 520 struct radix_tree_root tree; 521 }; 522 523 struct mlx5_irq_info { 524 char name[MLX5_MAX_IRQ_NAME]; 525 }; 526 527 struct mlx5_priv { 528 char name[MLX5_MAX_NAME_LEN]; 529 struct mlx5_eq_table eq_table; 530 struct msix_entry *msix_arr; 531 struct mlx5_irq_info *irq_info; 532 struct mlx5_uuar_info uuari; 533 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 534 535 struct io_mapping *bf_mapping; 536 537 /* pages stuff */ 538 struct workqueue_struct *pg_wq; 539 struct rb_root page_root; 540 s64 fw_pages; 541 atomic_t reg_pages; 542 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 543 struct mlx5_core_health health; 544 545 struct mlx5_srq_table srq_table; 546 547 /* start: qp staff */ 548 struct mlx5_qp_table qp_table; 549 struct dentry *qp_debugfs; 550 struct dentry *eq_debugfs; 551 struct dentry *cq_debugfs; 552 struct dentry *cmdif_debugfs; 553 /* end: qp staff */ 554 555 /* start: cq staff */ 556 struct mlx5_cq_table cq_table; 557 /* end: cq staff */ 558 559 /* start: mr staff */ 560 struct mlx5_mr_table mr_table; 561 /* end: mr staff */ 562 563 /* start: alloc staff */ 564 int numa_node; 565 566 struct mutex pgdir_mutex; 567 struct list_head pgdir_list; 568 /* end: alloc staff */ 569 struct dentry *dbg_root; 570 571 /* protect mkey key part */ 572 spinlock_t mkey_lock; 573 u8 mkey_key; 574 575 struct list_head dev_list; 576 struct list_head ctx_list; 577 spinlock_t ctx_lock; 578 unsigned long pci_dev_data; 579 }; 580 581 enum mlx5_device_state { 582 MLX5_DEVICE_STATE_UP, 583 MLX5_DEVICE_STATE_INTERNAL_ERROR, 584 }; 585 586 struct mlx5_special_contexts { 587 int resd_lkey; 588 }; 589 590 struct mlx5_flow_root_namespace; 591 struct mlx5_core_dev { 592 struct pci_dev *pdev; 593 char board_id[MLX5_BOARD_ID_LEN]; 594 struct mlx5_cmd cmd; 595 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 596 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 597 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 598 phys_addr_t iseg_base; 599 struct mlx5_init_seg __iomem *iseg; 600 enum mlx5_device_state state; 601 void (*event) (struct mlx5_core_dev *dev, 602 enum mlx5_dev_event event, 603 unsigned long param); 604 struct mlx5_priv priv; 605 struct mlx5_profile *profile; 606 atomic_t num_qps; 607 u32 issi; 608 struct mlx5_special_contexts special_contexts; 609 unsigned int module_status[MLX5_MAX_PORTS]; 610 struct mlx5_flow_root_namespace *root_ns; 611 struct mlx5_flow_root_namespace *fdb_root_ns; 612 struct mlx5_flow_root_namespace *esw_egress_root_ns; 613 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 614 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 615 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 616 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 617 }; 618 619 enum { 620 MLX5_WOL_DISABLE = 0, 621 MLX5_WOL_SECURED_MAGIC = 1 << 1, 622 MLX5_WOL_MAGIC = 1 << 2, 623 MLX5_WOL_ARP = 1 << 3, 624 MLX5_WOL_BROADCAST = 1 << 4, 625 MLX5_WOL_MULTICAST = 1 << 5, 626 MLX5_WOL_UNICAST = 1 << 6, 627 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 628 }; 629 630 struct mlx5_db { 631 __be32 *db; 632 union { 633 struct mlx5_db_pgdir *pgdir; 634 struct mlx5_ib_user_db_page *user_page; 635 } u; 636 dma_addr_t dma; 637 int index; 638 }; 639 640 struct mlx5_net_counters { 641 u64 packets; 642 u64 octets; 643 }; 644 645 struct mlx5_ptys_reg { 646 u8 an_dis_admin; 647 u8 an_dis_ap; 648 u8 local_port; 649 u8 proto_mask; 650 u32 eth_proto_cap; 651 u16 ib_link_width_cap; 652 u16 ib_proto_cap; 653 u32 eth_proto_admin; 654 u16 ib_link_width_admin; 655 u16 ib_proto_admin; 656 u32 eth_proto_oper; 657 u16 ib_link_width_oper; 658 u16 ib_proto_oper; 659 u32 eth_proto_lp_advertise; 660 }; 661 662 struct mlx5_pvlc_reg { 663 u8 local_port; 664 u8 vl_hw_cap; 665 u8 vl_admin; 666 u8 vl_operational; 667 }; 668 669 struct mlx5_pmtu_reg { 670 u8 local_port; 671 u16 max_mtu; 672 u16 admin_mtu; 673 u16 oper_mtu; 674 }; 675 676 struct mlx5_vport_counters { 677 struct mlx5_net_counters received_errors; 678 struct mlx5_net_counters transmit_errors; 679 struct mlx5_net_counters received_ib_unicast; 680 struct mlx5_net_counters transmitted_ib_unicast; 681 struct mlx5_net_counters received_ib_multicast; 682 struct mlx5_net_counters transmitted_ib_multicast; 683 struct mlx5_net_counters received_eth_broadcast; 684 struct mlx5_net_counters transmitted_eth_broadcast; 685 struct mlx5_net_counters received_eth_unicast; 686 struct mlx5_net_counters transmitted_eth_unicast; 687 struct mlx5_net_counters received_eth_multicast; 688 struct mlx5_net_counters transmitted_eth_multicast; 689 }; 690 691 enum { 692 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 693 }; 694 695 struct mlx5_core_dct { 696 struct mlx5_core_rsc_common common; /* must be first */ 697 void (*event)(struct mlx5_core_dct *, int); 698 int dctn; 699 struct completion drained; 700 struct mlx5_rsc_debug *dbg; 701 int pid; 702 }; 703 704 enum { 705 MLX5_COMP_EQ_SIZE = 1024, 706 }; 707 708 enum { 709 MLX5_PTYS_IB = 1 << 0, 710 MLX5_PTYS_EN = 1 << 2, 711 }; 712 713 struct mlx5_db_pgdir { 714 struct list_head list; 715 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 716 struct mlx5_fw_page *fw_page; 717 __be32 *db_page; 718 dma_addr_t db_dma; 719 }; 720 721 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 722 723 struct mlx5_cmd_work_ent { 724 struct mlx5_cmd_msg *in; 725 struct mlx5_cmd_msg *out; 726 int uin_size; 727 void *uout; 728 int uout_size; 729 mlx5_cmd_cbk_t callback; 730 void *context; 731 int idx; 732 struct completion done; 733 struct mlx5_cmd *cmd; 734 struct work_struct work; 735 struct mlx5_cmd_layout *lay; 736 int ret; 737 int page_queue; 738 u8 status; 739 u8 token; 740 u64 ts1; 741 u64 ts2; 742 u16 op; 743 u8 busy; 744 }; 745 746 struct mlx5_pas { 747 u64 pa; 748 u8 log_sz; 749 }; 750 751 enum port_state_policy { 752 MLX5_POLICY_DOWN = 0, 753 MLX5_POLICY_UP = 1, 754 MLX5_POLICY_FOLLOW = 2, 755 MLX5_POLICY_INVALID = 0xffffffff 756 }; 757 758 static inline void * 759 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 760 { 761 return ((char *)buf->direct.buf + offset); 762 } 763 764 765 extern struct workqueue_struct *mlx5_core_wq; 766 767 #define STRUCT_FIELD(header, field) \ 768 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 769 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 770 771 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 772 { 773 return pci_get_drvdata(pdev); 774 } 775 776 extern struct dentry *mlx5_debugfs_root; 777 778 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 779 { 780 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 781 } 782 783 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 784 { 785 return ioread32be(&dev->iseg->fw_rev) >> 16; 786 } 787 788 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 789 { 790 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 791 } 792 793 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 794 { 795 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 796 } 797 798 static inline int mlx5_get_gid_table_len(u16 param) 799 { 800 if (param > 4) { 801 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 802 return 0; 803 } 804 805 return 8 * (1 << param); 806 } 807 808 static inline void *mlx5_vzalloc(unsigned long size) 809 { 810 void *rtn; 811 812 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 813 return rtn; 814 } 815 816 static inline void *mlx5_vmalloc(unsigned long size) 817 { 818 void *rtn; 819 820 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 821 if (!rtn) 822 rtn = vmalloc(size); 823 return rtn; 824 } 825 826 static inline u32 mlx5_base_mkey(const u32 key) 827 { 828 return key & 0xffffff00u; 829 } 830 831 void mlx5_enter_error_state(struct mlx5_core_dev *dev); 832 int mlx5_cmd_init(struct mlx5_core_dev *dev); 833 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 834 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 835 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 836 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 837 int mlx5_cmd_status_to_err_v2(void *ptr); 838 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 839 enum mlx5_cap_mode cap_mode); 840 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 841 int out_size); 842 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 843 void *out, int out_size, mlx5_cmd_cbk_t callback, 844 void *context); 845 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 846 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 847 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 848 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 849 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 850 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 851 void mlx5_health_cleanup(void); 852 void __init mlx5_health_init(void); 853 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 854 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 855 856 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 857 mlx5_buf_alloc(dev, size, direct, buf) 858 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 859 struct mlx5_buf *buf); 860 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 861 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 862 struct mlx5_create_srq_mbox_in *in, int inlen, 863 int is_xrc); 864 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 865 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 866 struct mlx5_query_srq_mbox_out *out); 867 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 868 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 869 u16 lwm, int is_srq); 870 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 871 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 872 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 873 struct mlx5_create_mkey_mbox_in *in, int inlen, 874 mlx5_cmd_cbk_t callback, void *context, 875 struct mlx5_create_mkey_mbox_out *out); 876 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 877 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 878 struct mlx5_query_mkey_mbox_out *out, int outlen); 879 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 880 u32 *mkey); 881 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 882 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 883 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 884 u16 opmod, u8 port); 885 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 886 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 887 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 888 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 889 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 890 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 891 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 892 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 893 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 894 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 895 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 896 s32 npages); 897 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 898 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 899 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 900 void mlx5_register_debugfs(void); 901 void mlx5_unregister_debugfs(void); 902 int mlx5_eq_init(struct mlx5_core_dev *dev); 903 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 904 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 905 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 906 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 907 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 908 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 909 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector); 910 void mlx5_trigger_cmd_completions(struct mlx5_core_dev *dev); 911 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 912 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 913 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 914 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 915 int mlx5_start_eqs(struct mlx5_core_dev *dev); 916 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 917 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 918 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 919 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 920 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 921 u64 addr); 922 923 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 924 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 925 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 926 int size_in, void *data_out, int size_out, 927 u16 reg_num, int arg, int write); 928 929 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 930 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 931 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 932 int ptys_size, int proto_mask); 933 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 934 u32 *proto_cap, int proto_mask); 935 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, 936 u8 *an_disable_cap, u8 *an_disable_status); 937 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable, 938 u32 eth_proto_admin, int proto_mask); 939 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 940 u32 *proto_admin, int proto_mask); 941 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 942 int proto_mask); 943 int mlx5_set_port_status(struct mlx5_core_dev *dev, 944 enum mlx5_port_status status); 945 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 946 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 947 enum mlx5_port_status *status); 948 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port, 949 u32 rx_pause, u32 tx_pause); 950 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 951 u32 *rx_pause, u32 *tx_pause); 952 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); 953 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx); 954 955 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 956 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 957 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 958 959 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 960 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 961 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 962 int device_addr, int size, int module_num, u32 *data, 963 int *size_read); 964 965 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 966 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 967 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 968 struct mlx5_query_eq_mbox_out *out, int outlen); 969 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 970 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 971 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 972 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 973 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 974 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 975 int node); 976 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 977 978 const char *mlx5_command_str(int command); 979 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 980 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 981 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 982 int npsvs, u32 *sig_index); 983 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 984 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 985 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 986 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 987 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 988 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 989 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 990 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 991 struct mlx5_pvlc_reg *pvlc, int write); 992 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 993 struct mlx5_ptys_reg *ptys, int write); 994 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 995 struct mlx5_pmtu_reg *pmtu, int write); 996 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 997 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 998 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 999 int priority, int *is_enable); 1000 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1001 int priority, int enable); 1002 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1003 void *out, int out_size); 1004 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1005 void *in, int in_size); 1006 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1007 void *out, int out_size); 1008 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1009 int in_size); 1010 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1011 u8 num_of_samples, u16 sample_index, 1012 void *out, int out_size); 1013 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1014 { 1015 return mkey >> 8; 1016 } 1017 1018 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1019 { 1020 return mkey_idx << 8; 1021 } 1022 1023 static inline u8 mlx5_mkey_variant(u32 mkey) 1024 { 1025 return mkey & 0xff; 1026 } 1027 1028 enum { 1029 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1030 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1031 }; 1032 1033 enum { 1034 MAX_MR_CACHE_ENTRIES = 15, 1035 }; 1036 1037 struct mlx5_interface { 1038 void * (*add)(struct mlx5_core_dev *dev); 1039 void (*remove)(struct mlx5_core_dev *dev, void *context); 1040 void (*event)(struct mlx5_core_dev *dev, void *context, 1041 enum mlx5_dev_event event, unsigned long param); 1042 void * (*get_dev)(void *context); 1043 int protocol; 1044 struct list_head list; 1045 }; 1046 1047 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1048 int mlx5_register_interface(struct mlx5_interface *intf); 1049 void mlx5_unregister_interface(struct mlx5_interface *intf); 1050 1051 struct mlx5_profile { 1052 u64 mask; 1053 u8 log_max_qp; 1054 struct { 1055 int size; 1056 int limit; 1057 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1058 }; 1059 1060 enum { 1061 MLX5_PCI_DEV_IS_VF = 1 << 0, 1062 }; 1063 1064 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1065 { 1066 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1067 } 1068 1069 #define MLX5_EEPROM_MAX_BYTES 32 1070 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 1071 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 1072 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 1073 #endif /* MLX5_DRIVER_H */ 1074