xref: /freebsd/sys/dev/mlx5/driver.h (revision bcf5c7a8b1dcdcd5f27c1aa694f66208dc07a0dd) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 #include <linux/wait.h>
45 
46 #include <dev/mlx5/device.h>
47 #include <dev/mlx5/doorbell.h>
48 #include <dev/mlx5/srq.h>
49 
50 #define MLX5_QCOUNTER_SETS_NETDEV 64
51 #define MLX5_MAX_NUMBER_OF_VFS 128
52 
53 enum {
54 	MLX5_BOARD_ID_LEN = 64,
55 	MLX5_MAX_NAME_LEN = 16,
56 };
57 
58 enum {
59 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_ATOMIC_MODE_OFF		= 16,
89 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
90 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
91 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
98 };
99 
100 enum {
101 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
102 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
103 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
104 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
111 };
112 
113 enum {
114 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
115 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
116 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
117 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
118 };
119 
120 enum {
121 	MLX5_REG_QPTS		 = 0x4002,
122 	MLX5_REG_QETCR		 = 0x4005,
123 	MLX5_REG_QPDP		 = 0x4007,
124 	MLX5_REG_QTCT		 = 0x400A,
125 	MLX5_REG_QPDPM		 = 0x4013,
126 	MLX5_REG_QHLL		 = 0x4016,
127 	MLX5_REG_QCAM		 = 0x4019,
128 	MLX5_REG_DCBX_PARAM	 = 0x4020,
129 	MLX5_REG_DCBX_APP	 = 0x4021,
130 	MLX5_REG_FPGA_CAP	 = 0x4022,
131 	MLX5_REG_FPGA_CTRL	 = 0x4023,
132 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
133 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_PMLP		 = 0x5002,
136 	MLX5_REG_PMTU		 = 0x5003,
137 	MLX5_REG_PTYS		 = 0x5004,
138 	MLX5_REG_PAOS		 = 0x5006,
139 	MLX5_REG_PFCC		 = 0x5007,
140 	MLX5_REG_PPCNT		 = 0x5008,
141 	MLX5_REG_PUDE		 = 0x5009,
142 	MLX5_REG_PPTB		 = 0x500B,
143 	MLX5_REG_PBMC		 = 0x500C,
144 	MLX5_REG_PELC		 = 0x500E,
145 	MLX5_REG_PVLC		 = 0x500F,
146 	MLX5_REG_PMPE		 = 0x5010,
147 	MLX5_REG_PMAOS		 = 0x5012,
148 	MLX5_REG_PPLM		 = 0x5023,
149 	MLX5_REG_PDDR		 = 0x5031,
150 	MLX5_REG_PBSR		 = 0x5038,
151 	MLX5_REG_PCAM		 = 0x507f,
152 	MLX5_REG_NODE_DESC	 = 0x6001,
153 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
154 	MLX5_REG_MTMP		 = 0x900a,
155 	MLX5_REG_MCIA		 = 0x9014,
156 	MLX5_REG_MFRL		 = 0x9028,
157 	MLX5_REG_MPCNT		 = 0x9051,
158 	MLX5_REG_MCQI		 = 0x9061,
159 	MLX5_REG_MCC		 = 0x9062,
160 	MLX5_REG_MCDA		 = 0x9063,
161 	MLX5_REG_MCAM		 = 0x907f,
162 };
163 
164 enum dbg_rsc_type {
165 	MLX5_DBG_RSC_QP,
166 	MLX5_DBG_RSC_EQ,
167 	MLX5_DBG_RSC_CQ,
168 };
169 
170 enum {
171 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
172 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
173 	MLX5_INTERFACE_NUMBER       = 2,
174 };
175 
176 struct mlx5_field_desc {
177 	struct dentry	       *dent;
178 	int			i;
179 };
180 
181 struct mlx5_rsc_debug {
182 	struct mlx5_core_dev   *dev;
183 	void		       *object;
184 	enum dbg_rsc_type	type;
185 	struct dentry	       *root;
186 	struct mlx5_field_desc	fields[0];
187 };
188 
189 enum mlx5_dev_event {
190 	MLX5_DEV_EVENT_SYS_ERROR,
191 	MLX5_DEV_EVENT_PORT_UP,
192 	MLX5_DEV_EVENT_PORT_DOWN,
193 	MLX5_DEV_EVENT_PORT_INITIALIZED,
194 	MLX5_DEV_EVENT_LID_CHANGE,
195 	MLX5_DEV_EVENT_PKEY_CHANGE,
196 	MLX5_DEV_EVENT_GUID_CHANGE,
197 	MLX5_DEV_EVENT_CLIENT_REREG,
198 	MLX5_DEV_EVENT_VPORT_CHANGE,
199 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
200 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
201 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
202 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
203 };
204 
205 enum mlx5_port_status {
206 	MLX5_PORT_UP        = 1 << 0,
207 	MLX5_PORT_DOWN      = 1 << 1,
208 };
209 
210 enum {
211 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
212 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
213 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
214 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
215 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
216 	MLX5_VSC_DATA_OFFSET	 = 0x14,
217 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
218 };
219 
220 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
221 
222 struct mlx5_cmd_first {
223 	__be32		data[4];
224 };
225 
226 struct cache_ent;
227 struct mlx5_fw_page {
228 	union {
229 		struct rb_node rb_node;
230 		struct list_head list;
231 	};
232 	struct mlx5_cmd_first first;
233 	struct mlx5_core_dev *dev;
234 	bus_dmamap_t dma_map;
235 	bus_addr_t dma_addr;
236 	void *virt_addr;
237 	struct cache_ent *cache;
238 	u32 numpages;
239 	u16 load_done;
240 #define	MLX5_LOAD_ST_NONE 0
241 #define	MLX5_LOAD_ST_SUCCESS 1
242 #define	MLX5_LOAD_ST_FAILURE 2
243 	u16 func_id;
244 };
245 #define	mlx5_cmd_msg mlx5_fw_page
246 
247 struct mlx5_cmd_debug {
248 	struct dentry	       *dbg_root;
249 	struct dentry	       *dbg_in;
250 	struct dentry	       *dbg_out;
251 	struct dentry	       *dbg_outlen;
252 	struct dentry	       *dbg_status;
253 	struct dentry	       *dbg_run;
254 	void		       *in_msg;
255 	void		       *out_msg;
256 	u8			status;
257 	u16			inlen;
258 	u16			outlen;
259 };
260 
261 struct cache_ent {
262 	/* protect block chain allocations
263 	 */
264 	spinlock_t		lock;
265 	struct list_head	head;
266 };
267 
268 struct cmd_msg_cache {
269 	struct cache_ent	large;
270 	struct cache_ent	med;
271 
272 };
273 
274 struct mlx5_traffic_counter {
275 	u64         packets;
276 	u64         octets;
277 };
278 
279 enum mlx5_cmd_mode {
280 	MLX5_CMD_MODE_POLLING,
281 	MLX5_CMD_MODE_EVENTS
282 };
283 
284 struct mlx5_cmd_stats {
285 	u64		sum;
286 	u64		n;
287 	struct dentry  *root;
288 	struct dentry  *avg;
289 	struct dentry  *count;
290 	/* protect command average calculations */
291 	spinlock_t	lock;
292 };
293 
294 struct mlx5_cmd {
295 	struct mlx5_fw_page *cmd_page;
296 	bus_dma_tag_t dma_tag;
297 	struct sx dma_sx;
298 	struct mtx dma_mtx;
299 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
300 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
301 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
302 	struct cv dma_cv;
303 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
304 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
305 	void	       *cmd_buf;
306 	dma_addr_t	dma;
307 	u16		cmdif_rev;
308 	u8		log_sz;
309 	u8		log_stride;
310 	int		max_reg_cmds;
311 	int		events;
312 	u32 __iomem    *vector;
313 
314 	/* protect command queue allocations
315 	 */
316 	spinlock_t	alloc_lock;
317 
318 	/* protect token allocations
319 	 */
320 	spinlock_t	token_lock;
321 	u8		token;
322 	unsigned long	bitmask;
323 	struct semaphore sem;
324 	struct semaphore pages_sem;
325 	enum mlx5_cmd_mode mode;
326 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
327 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
328 	struct mlx5_cmd_debug dbg;
329 	struct cmd_msg_cache cache;
330 	int checksum_disabled;
331 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
332 };
333 
334 struct mlx5_port_caps {
335 	int	gid_table_len;
336 	int	pkey_table_len;
337 	u8	ext_port_cap;
338 };
339 
340 struct mlx5_buf {
341 	bus_dma_tag_t		dma_tag;
342 	bus_dmamap_t		dma_map;
343 	struct mlx5_core_dev   *dev;
344 	struct {
345 		void	       *buf;
346 	} direct;
347 	u64		       *page_list;
348 	int			npages;
349 	int			size;
350 	u8			page_shift;
351 	u8			load_done;
352 };
353 
354 struct mlx5_frag_buf {
355 	struct mlx5_buf_list	*frags;
356 	int			npages;
357 	int			size;
358 	u8			page_shift;
359 };
360 
361 struct mlx5_eq {
362 	struct mlx5_core_dev   *dev;
363 	__be32 __iomem	       *doorbell;
364 	u32			cons_index;
365 	struct mlx5_buf		buf;
366 	int			size;
367 	u8			irqn;
368 	u8			eqn;
369 	int			nent;
370 	u64			mask;
371 	struct list_head	list;
372 	int			index;
373 	struct mlx5_rsc_debug	*dbg;
374 };
375 
376 struct mlx5_core_psv {
377 	u32	psv_idx;
378 	struct psv_layout {
379 		u32	pd;
380 		u16	syndrome;
381 		u16	reserved;
382 		u16	bg;
383 		u16	app_tag;
384 		u32	ref_tag;
385 	} psv;
386 };
387 
388 struct mlx5_core_sig_ctx {
389 	struct mlx5_core_psv	psv_memory;
390 	struct mlx5_core_psv	psv_wire;
391 #if (__FreeBSD_version >= 1100000)
392 	struct ib_sig_err       err_item;
393 #endif
394 	bool			sig_status_checked;
395 	bool			sig_err_exists;
396 	u32			sigerr_count;
397 };
398 
399 enum {
400 	MLX5_MKEY_MR = 1,
401 	MLX5_MKEY_MW,
402 	MLX5_MKEY_INDIRECT_DEVX,
403 };
404 
405 struct mlx5_core_mkey {
406 	u64			iova;
407 	u64			size;
408 	u32			key;
409 	u32			pd;
410 	u32			type;
411 };
412 
413 enum mlx5_res_type {
414 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
415 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
416 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
417 	MLX5_RES_SRQ	= 3,
418 	MLX5_RES_XSRQ	= 4,
419 	MLX5_RES_XRQ	= 5,
420 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
421 };
422 
423 struct mlx5_core_rsc_common {
424 	enum mlx5_res_type	res;
425 	atomic_t		refcount;
426 	struct completion	free;
427 };
428 
429 struct mlx5_uars_page {
430 	void __iomem	       *map;
431 	bool			wc;
432 	u32			index;
433 	struct list_head	list;
434 	unsigned int		bfregs;
435 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
436 	unsigned long	       *fp_bitmap;
437 	unsigned int		reg_avail;
438 	unsigned int		fp_avail;
439 	struct kref		ref_count;
440 	struct mlx5_core_dev   *mdev;
441 };
442 
443 struct mlx5_bfreg_head {
444 	/* protect blue flame registers allocations */
445 	struct mutex		lock;
446 	struct list_head	list;
447 };
448 
449 struct mlx5_bfreg_data {
450 	struct mlx5_bfreg_head	reg_head;
451 	struct mlx5_bfreg_head	wc_head;
452 };
453 
454 struct mlx5_sq_bfreg {
455 	void __iomem	       *map;
456 	struct mlx5_uars_page  *up;
457 	bool			wc;
458 	u32			index;
459 	unsigned int		offset;
460 };
461 
462 struct mlx5_core_srq {
463 	struct mlx5_core_rsc_common	common; /* must be first */
464 	u32				srqn;
465 	int				max;
466 	size_t				max_gs;
467 	size_t				max_avail_gather;
468 	int				wqe_shift;
469 	void				(*event)(struct mlx5_core_srq *, int);
470 	atomic_t			refcount;
471 	struct completion		free;
472 };
473 
474 struct mlx5_ib_dev;
475 struct mlx5_eq_table {
476 	void __iomem	       *update_ci;
477 	void __iomem	       *update_arm_ci;
478 	struct list_head	comp_eqs_list;
479 	struct mlx5_eq		pages_eq;
480 	struct mlx5_eq		async_eq;
481 	struct mlx5_eq		cmd_eq;
482 	int			num_comp_vectors;
483 	spinlock_t		lock;	/* protect EQs list */
484 	struct mlx5_ib_dev	*dev;	/* for devx event notifier */
485 	bool (*cb)(struct mlx5_core_dev *mdev,
486 		   uint8_t event_type, void *data);
487 };
488 
489 struct mlx5_core_health {
490 	struct mlx5_health_buffer __iomem	*health;
491 	__be32 __iomem		       *health_counter;
492 	struct timer_list		timer;
493 	u32				prev;
494 	int				miss_counter;
495 	u32				fatal_error;
496 	struct workqueue_struct	       *wq_watchdog;
497 	struct work_struct		work_watchdog;
498 	/* wq spinlock to synchronize draining */
499 	spinlock_t			wq_lock;
500 	struct workqueue_struct	       *wq;
501 	unsigned long			flags;
502 	struct work_struct		work;
503 	struct delayed_work		recover_work;
504 	unsigned int			last_reset_req;
505 	struct work_struct		work_cmd_completion;
506 	struct workqueue_struct	       *wq_cmd;
507 };
508 
509 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
510 
511 struct mlx5_cq_linear_array_entry {
512 	struct mlx5_core_cq * volatile cq;
513 };
514 
515 struct mlx5_cq_table {
516 	/* protect radix tree
517 	 */
518 	spinlock_t		writerlock;
519 	atomic_t		writercount;
520 	struct radix_tree_root	tree;
521 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
522 };
523 
524 struct mlx5_qp_table {
525 	/* protect radix tree
526 	 */
527 	spinlock_t		lock;
528 	struct radix_tree_root	tree;
529 };
530 
531 struct mlx5_srq_table {
532 	/* protect radix tree
533 	 */
534 	spinlock_t		lock;
535 	struct radix_tree_root	tree;
536 };
537 
538 struct mlx5_mr_table {
539 	/* protect radix tree
540 	 */
541 	spinlock_t		lock;
542 	struct radix_tree_root	tree;
543 };
544 
545 #ifdef RATELIMIT
546 struct mlx5_rl_entry {
547 	u32			rate;
548 	u16			burst;
549 	u16			index;
550 	u32			refcount;
551 };
552 
553 struct mlx5_rl_table {
554 	struct mutex		rl_lock;
555 	u16			max_size;
556 	u32			max_rate;
557 	u32			min_rate;
558 	struct mlx5_rl_entry   *rl_entry;
559 };
560 #endif
561 
562 struct mlx5_pme_stats {
563 	u64			status_counters[MLX5_MODULE_STATUS_NUM];
564 	u64			error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
565 };
566 
567 struct mlx5_priv {
568 	char			name[MLX5_MAX_NAME_LEN];
569 	struct mlx5_eq_table	eq_table;
570 	struct msix_entry	*msix_arr;
571 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
572 	int			disable_irqs;
573 
574 	/* pages stuff */
575 	struct workqueue_struct *pg_wq;
576 	struct rb_root		page_root;
577 	s64			fw_pages;
578 	atomic_t		reg_pages;
579 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
580 	struct mlx5_core_health health;
581 
582 	struct mlx5_srq_table	srq_table;
583 
584 	/* start: qp staff */
585 	struct mlx5_qp_table	qp_table;
586 	struct dentry	       *qp_debugfs;
587 	struct dentry	       *eq_debugfs;
588 	struct dentry	       *cq_debugfs;
589 	struct dentry	       *cmdif_debugfs;
590 	/* end: qp staff */
591 
592 	/* start: cq staff */
593 	struct mlx5_cq_table	cq_table;
594 	/* end: cq staff */
595 
596 	/* start: mr staff */
597 	struct mlx5_mr_table	mr_table;
598 	/* end: mr staff */
599 
600 	/* start: alloc staff */
601 	int			numa_node;
602 
603 	struct mutex   pgdir_mutex;
604 	struct list_head        pgdir_list;
605 	/* end: alloc staff */
606 	struct dentry	       *dbg_root;
607 
608 	/* protect mkey key part */
609 	spinlock_t		mkey_lock;
610 	u8			mkey_key;
611 
612 	struct list_head        dev_list;
613 	struct list_head        ctx_list;
614 	spinlock_t              ctx_lock;
615 	unsigned long		pci_dev_data;
616 #ifdef RATELIMIT
617 	struct mlx5_rl_table	rl_table;
618 #endif
619 	struct mlx5_pme_stats pme_stats;
620 
621 	struct mlx5_eswitch	*eswitch;
622 
623 	struct mlx5_bfreg_data		bfregs;
624 	struct mlx5_uars_page	       *uar;
625 };
626 
627 enum mlx5_device_state {
628 	MLX5_DEVICE_STATE_UP,
629 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
630 };
631 
632 enum mlx5_interface_state {
633 	MLX5_INTERFACE_STATE_UP = 0x1,
634 	MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
635 };
636 
637 enum mlx5_pci_status {
638 	MLX5_PCI_STATUS_DISABLED,
639 	MLX5_PCI_STATUS_ENABLED,
640 };
641 
642 #define	MLX5_MAX_RESERVED_GIDS	8
643 
644 struct mlx5_rsvd_gids {
645 	unsigned int start;
646 	unsigned int count;
647 	struct ida ida;
648 };
649 
650 struct mlx5_special_contexts {
651 	int resd_lkey;
652 };
653 
654 struct mlx5_flow_root_namespace;
655 struct mlx5_core_dev {
656 	struct pci_dev	       *pdev;
657 	/* sync pci state */
658 	struct mutex		pci_status_mutex;
659 	enum mlx5_pci_status	pci_status;
660 	char			board_id[MLX5_BOARD_ID_LEN];
661 	struct mlx5_cmd		cmd;
662 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
663 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
664 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
665 	struct {
666 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
667 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
668 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
669 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
670 	} caps;
671 	phys_addr_t		iseg_base;
672 	struct mlx5_init_seg __iomem *iseg;
673 	enum mlx5_device_state	state;
674 	/* sync interface state */
675 	struct mutex		intf_state_mutex;
676 	unsigned long		intf_state;
677 	void			(*event) (struct mlx5_core_dev *dev,
678 					  enum mlx5_dev_event event,
679 					  unsigned long param);
680 	struct mlx5_priv	priv;
681 	struct mlx5_profile	*profile;
682 	atomic_t		num_qps;
683 	u32			vsc_addr;
684 	u32			issi;
685 	struct mlx5_special_contexts special_contexts;
686 	unsigned int module_status[MLX5_MAX_PORTS];
687 	struct mlx5_flow_root_namespace *root_ns;
688 	struct mlx5_flow_root_namespace *fdb_root_ns;
689 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
690 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
691 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
692 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
693 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
694 	struct mlx5_crspace_regmap *dump_rege;
695 	uint32_t *dump_data;
696 	unsigned dump_size;
697 	bool dump_valid;
698 	bool dump_copyout;
699 	struct mtx dump_lock;
700 
701 	struct sysctl_ctx_list	sysctl_ctx;
702 	int			msix_eqvec;
703 	int			pwr_status;
704 	int			pwr_value;
705 
706 	struct {
707 		struct mlx5_rsvd_gids	reserved_gids;
708 		atomic_t		roce_en;
709 	} roce;
710 
711 	struct {
712 		spinlock_t	spinlock;
713 #define	MLX5_MPFS_TABLE_MAX 32
714 		long		bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
715 	} mpfs;
716 #ifdef CONFIG_MLX5_FPGA
717 	struct mlx5_fpga_device	*fpga;
718 #endif
719 };
720 
721 enum {
722 	MLX5_WOL_DISABLE       = 0,
723 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
724 	MLX5_WOL_MAGIC         = 1 << 2,
725 	MLX5_WOL_ARP           = 1 << 3,
726 	MLX5_WOL_BROADCAST     = 1 << 4,
727 	MLX5_WOL_MULTICAST     = 1 << 5,
728 	MLX5_WOL_UNICAST       = 1 << 6,
729 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
730 };
731 
732 struct mlx5_db {
733 	__be32			*db;
734 	union {
735 		struct mlx5_db_pgdir		*pgdir;
736 		struct mlx5_ib_user_db_page	*user_page;
737 	}			u;
738 	dma_addr_t		dma;
739 	int			index;
740 };
741 
742 struct mlx5_net_counters {
743 	u64	packets;
744 	u64	octets;
745 };
746 
747 struct mlx5_ptys_reg {
748 	u8	an_dis_admin;
749 	u8	an_dis_ap;
750 	u8	local_port;
751 	u8	proto_mask;
752 	u32	eth_proto_cap;
753 	u16	ib_link_width_cap;
754 	u16	ib_proto_cap;
755 	u32	eth_proto_admin;
756 	u16	ib_link_width_admin;
757 	u16	ib_proto_admin;
758 	u32	eth_proto_oper;
759 	u16	ib_link_width_oper;
760 	u16	ib_proto_oper;
761 	u32	eth_proto_lp_advertise;
762 };
763 
764 struct mlx5_pvlc_reg {
765 	u8	local_port;
766 	u8	vl_hw_cap;
767 	u8	vl_admin;
768 	u8	vl_operational;
769 };
770 
771 struct mlx5_pmtu_reg {
772 	u8	local_port;
773 	u16	max_mtu;
774 	u16	admin_mtu;
775 	u16	oper_mtu;
776 };
777 
778 struct mlx5_vport_counters {
779 	struct mlx5_net_counters	received_errors;
780 	struct mlx5_net_counters	transmit_errors;
781 	struct mlx5_net_counters	received_ib_unicast;
782 	struct mlx5_net_counters	transmitted_ib_unicast;
783 	struct mlx5_net_counters	received_ib_multicast;
784 	struct mlx5_net_counters	transmitted_ib_multicast;
785 	struct mlx5_net_counters	received_eth_broadcast;
786 	struct mlx5_net_counters	transmitted_eth_broadcast;
787 	struct mlx5_net_counters	received_eth_unicast;
788 	struct mlx5_net_counters	transmitted_eth_unicast;
789 	struct mlx5_net_counters	received_eth_multicast;
790 	struct mlx5_net_counters	transmitted_eth_multicast;
791 };
792 
793 enum {
794 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
795 };
796 
797 struct mlx5_core_dct {
798 	struct mlx5_core_rsc_common	common; /* must be first */
799 	void (*event)(struct mlx5_core_dct *, int);
800 	int			dctn;
801 	struct completion	drained;
802 	struct mlx5_rsc_debug	*dbg;
803 	int			pid;
804 	u16			uid;
805 };
806 
807 enum {
808 	MLX5_COMP_EQ_SIZE = 1024,
809 };
810 
811 enum {
812 	MLX5_PTYS_IB = 1 << 0,
813 	MLX5_PTYS_EN = 1 << 2,
814 };
815 
816 struct mlx5_db_pgdir {
817 	struct list_head	list;
818 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
819 	struct mlx5_fw_page    *fw_page;
820 	__be32		       *db_page;
821 	dma_addr_t		db_dma;
822 };
823 
824 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
825 
826 struct mlx5_cmd_work_ent {
827 	struct mlx5_cmd_msg    *in;
828 	struct mlx5_cmd_msg    *out;
829 	int			uin_size;
830 	void		       *uout;
831 	int			uout_size;
832 	mlx5_cmd_cbk_t		callback;
833         struct delayed_work     cb_timeout_work;
834 	void		       *context;
835 	int			idx;
836 	struct completion	done;
837 	struct mlx5_cmd        *cmd;
838 	struct work_struct	work;
839 	struct mlx5_cmd_layout *lay;
840 	int			ret;
841 	int			page_queue;
842 	u8			status;
843 	u8			token;
844 	u64			ts1;
845 	u64			ts2;
846 	u16			op;
847 	u8			busy;
848 	bool			polling;
849 };
850 
851 struct mlx5_pas {
852 	u64	pa;
853 	u8	log_sz;
854 };
855 
856 enum port_state_policy {
857 	MLX5_POLICY_DOWN        = 0,
858 	MLX5_POLICY_UP          = 1,
859 	MLX5_POLICY_FOLLOW      = 2,
860 	MLX5_POLICY_INVALID     = 0xffffffff
861 };
862 
863 static inline void *
864 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
865 {
866 	return ((char *)buf->direct.buf + offset);
867 }
868 
869 
870 extern struct workqueue_struct *mlx5_core_wq;
871 
872 #define STRUCT_FIELD(header, field) \
873 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
874 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
875 
876 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
877 {
878 	return pci_get_drvdata(pdev);
879 }
880 
881 extern struct dentry *mlx5_debugfs_root;
882 
883 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
884 {
885 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
886 }
887 
888 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
889 {
890 	return ioread32be(&dev->iseg->fw_rev) >> 16;
891 }
892 
893 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
894 {
895 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
896 }
897 
898 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
899 {
900 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
901 }
902 
903 static inline int mlx5_get_gid_table_len(u16 param)
904 {
905 	if (param > 4) {
906 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
907 		return 0;
908 	}
909 
910 	return 8 * (1 << param);
911 }
912 
913 static inline void *mlx5_vzalloc(unsigned long size)
914 {
915 	void *rtn;
916 
917 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
918 	return rtn;
919 }
920 
921 static inline void *mlx5_vmalloc(unsigned long size)
922 {
923 	void *rtn;
924 
925 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
926 	if (!rtn)
927 		rtn = vmalloc(size);
928 	return rtn;
929 }
930 
931 static inline u32 mlx5_base_mkey(const u32 key)
932 {
933 	return key & 0xffffff00u;
934 }
935 
936 int mlx5_cmd_init(struct mlx5_core_dev *dev);
937 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
938 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
939 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
940 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
941 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
942 
943 struct mlx5_async_ctx {
944 	struct mlx5_core_dev *dev;
945 	atomic_t num_inflight;
946 	struct wait_queue_head wait;
947 };
948 
949 struct mlx5_async_work;
950 
951 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
952 
953 struct mlx5_async_work {
954 	struct mlx5_async_ctx *ctx;
955 	mlx5_async_cbk_t user_callback;
956 };
957 
958 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
959 			     struct mlx5_async_ctx *ctx);
960 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
961 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
962 		     void *out, int out_size, mlx5_async_cbk_t callback,
963 		     struct mlx5_async_work *work);
964 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
965 		  int out_size);
966 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
967 			  void *out, int out_size);
968 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
969 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
970 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
971 		     bool map_wc, bool fast_path);
972 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
973 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
974 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
975 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
976 int mlx5_health_init(struct mlx5_core_dev *dev);
977 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
978 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
979 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
980 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
981 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
982 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
983 
984 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
985 		   struct mlx5_buf *buf);
986 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
987 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
988 			 struct mlx5_srq_attr *in);
989 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
990 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
991 			struct mlx5_srq_attr *out);
992 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
993 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
994 		      u16 lwm, int is_srq);
995 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
996 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
997 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
998 			     struct mlx5_core_mkey *mkey,
999 			     struct mlx5_async_ctx *async_ctx, u32 *in,
1000 			     int inlen, u32 *out, int outlen,
1001 			     mlx5_async_cbk_t callback,
1002 			     struct mlx5_async_work *context);
1003 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1004 			  struct mlx5_core_mkey *mr,
1005 			  u32 *in, int inlen);
1006 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey);
1007 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1008 			 u32 *out, int outlen);
1009 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mr,
1010 			     u32 *mkey);
1011 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn, u16 uid);
1012 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid);
1013 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1014 		      u16 opmod, u8 port);
1015 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1016 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1017 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1018 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1019 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1020 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1021 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1022 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1023 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1024 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1025 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1026 				 s32 npages);
1027 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1028 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1029 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1030 void mlx5_register_debugfs(void);
1031 void mlx5_unregister_debugfs(void);
1032 int mlx5_eq_init(struct mlx5_core_dev *dev);
1033 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1034 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1035 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1036 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1037 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1038 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1039 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1040 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1041 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1042 		       int nent, u64 mask);
1043 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1044 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1045 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1046 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1047 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1048 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1049 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1050 				u64 addr);
1051 
1052 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1053 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1054 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1055 			 int size_in, void *data_out, int size_out,
1056 			 u16 reg_num, int arg, int write);
1057 
1058 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1059 
1060 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1061 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1062 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1063 		       u32 *out, int outlen);
1064 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1065 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1066 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1067 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1068 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1069 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1070 
1071 static inline struct domainset *
1072 mlx5_dev_domainset(struct mlx5_core_dev *mdev)
1073 {
1074 	return (linux_get_vm_domain_set(mdev->priv.numa_node));
1075 }
1076 
1077 const char *mlx5_command_str(int command);
1078 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1079 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1080 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1081 			 int npsvs, u32 *sig_index);
1082 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1083 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1084 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1085 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1086 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1087 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1088 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1089 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1090 			  struct mlx5_pvlc_reg *pvlc, int write);
1091 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1092 			  struct mlx5_ptys_reg *ptys, int write);
1093 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1094 			  struct mlx5_pmtu_reg *pmtu, int write);
1095 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1096 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1097 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1098 				int priority, int *is_enable);
1099 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1100 				 int priority, int enable);
1101 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1102 				void *out, int out_size);
1103 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1104 				 void *in, int in_size);
1105 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1106 				    void *out, int out_size);
1107 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1108 			       int in_size);
1109 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1110 				   u8 num_of_samples, u16 sample_index,
1111 				   void *out, int out_size);
1112 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1113 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1114 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1115 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1116 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1117 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1118 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1119 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1120 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1121 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1122 			       u16 *p_power, u8 *p_status);
1123 
1124 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1125 {
1126 	return mkey >> 8;
1127 }
1128 
1129 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1130 {
1131 	return mkey_idx << 8;
1132 }
1133 
1134 static inline u8 mlx5_mkey_variant(u32 mkey)
1135 {
1136 	return mkey & 0xff;
1137 }
1138 
1139 enum {
1140 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1141 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1142 };
1143 
1144 enum {
1145 	MAX_MR_CACHE_ENTRIES    = 15,
1146 };
1147 
1148 struct mlx5_interface {
1149 	void *			(*add)(struct mlx5_core_dev *dev);
1150 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1151 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1152 					 enum mlx5_dev_event event, unsigned long param);
1153 	void *                  (*get_dev)(void *context);
1154 	int			protocol;
1155 	struct list_head	list;
1156 };
1157 
1158 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1159 int mlx5_register_interface(struct mlx5_interface *intf);
1160 void mlx5_unregister_interface(struct mlx5_interface *intf);
1161 
1162 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1163 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1164     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1165     const u8 *mac, bool vlan, u16 vlan_id);
1166 
1167 struct mlx5_profile {
1168 	u64	mask;
1169 	u8	log_max_qp;
1170 	struct {
1171 		int	size;
1172 		int	limit;
1173 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1174 };
1175 
1176 enum {
1177 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1178 };
1179 
1180 enum {
1181 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1182 };
1183 
1184 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1185 {
1186 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1187 }
1188 #ifdef RATELIMIT
1189 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1190 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1191 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1192 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1193 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1194 
1195 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1196 {
1197 	return !!(dev->priv.rl_table.max_size);
1198 }
1199 #endif
1200 
1201 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1202 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1203 
1204 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
1205 {
1206         return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
1207                        MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
1208                        MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
1209 }
1210 
1211 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev)
1212 {
1213         return !MLX5_CAP_GEN(dev, rq_ts_format) ?
1214                        MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1215                        MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
1216 }
1217 
1218 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev)
1219 {
1220         return !MLX5_CAP_GEN(dev, sq_ts_format) ?
1221                        MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1222                        MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
1223 }
1224 
1225 #endif /* MLX5_DRIVER_H */
1226