xref: /freebsd/sys/dev/mlx5/driver.h (revision b3e7694832e81d7a904a10f525f8797b753bf0d3) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  * Copyright (c) 2022 NVIDIA corporation & affiliates.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #ifndef MLX5_DRIVER_H
28 #define MLX5_DRIVER_H
29 
30 #include "opt_ratelimit.h"
31 
32 #include <linux/kernel.h>
33 #include <linux/completion.h>
34 #include <linux/pci.h>
35 #include <linux/cache.h>
36 #include <linux/rbtree.h>
37 #include <linux/if_ether.h>
38 #include <linux/semaphore.h>
39 #include <linux/slab.h>
40 #include <linux/vmalloc.h>
41 #include <linux/radix-tree.h>
42 #include <linux/idr.h>
43 #include <linux/wait.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 #define MLX5_INVALID_QUEUE_HANDLE 0xffffffff
53 
54 enum {
55 	MLX5_BOARD_ID_LEN = 64,
56 	MLX5_MAX_NAME_LEN = 16,
57 };
58 
59 enum {
60 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
61 };
62 
63 enum {
64 	CMD_OWNER_SW		= 0x0,
65 	CMD_OWNER_HW		= 0x1,
66 	CMD_STATUS_SUCCESS	= 0,
67 };
68 
69 enum mlx5_sqp_t {
70 	MLX5_SQP_SMI		= 0,
71 	MLX5_SQP_GSI		= 1,
72 	MLX5_SQP_IEEE_1588	= 2,
73 	MLX5_SQP_SNIFFER	= 3,
74 	MLX5_SQP_SYNC_UMR	= 4,
75 };
76 
77 enum {
78 	MLX5_MAX_PORTS	= 2,
79 };
80 
81 enum {
82 	MLX5_EQ_VEC_PAGES	 = 0,
83 	MLX5_EQ_VEC_CMD		 = 1,
84 	MLX5_EQ_VEC_ASYNC	 = 2,
85 	MLX5_EQ_VEC_COMP_BASE,
86 };
87 
88 enum {
89 	MLX5_ATOMIC_MODE_OFF		= 16,
90 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
91 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
98 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
99 };
100 
101 enum {
102 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
103 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
104 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
111 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
112 };
113 
114 enum {
115 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
116 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
117 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
118 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
119 };
120 
121 enum {
122 	MLX5_REG_QPTS		 = 0x4002,
123 	MLX5_REG_QETCR		 = 0x4005,
124 	MLX5_REG_QPDP		 = 0x4007,
125 	MLX5_REG_QTCT		 = 0x400A,
126 	MLX5_REG_QPDPM		 = 0x4013,
127 	MLX5_REG_QHLL		 = 0x4016,
128 	MLX5_REG_QCAM		 = 0x4019,
129 	MLX5_REG_DCBX_PARAM	 = 0x4020,
130 	MLX5_REG_DCBX_APP	 = 0x4021,
131 	MLX5_REG_FPGA_CAP	 = 0x4022,
132 	MLX5_REG_FPGA_CTRL	 = 0x4023,
133 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
134 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
135 	MLX5_REG_PCAP		 = 0x5001,
136 	MLX5_REG_PMLP		 = 0x5002,
137 	MLX5_REG_PMTU		 = 0x5003,
138 	MLX5_REG_PTYS		 = 0x5004,
139 	MLX5_REG_PAOS		 = 0x5006,
140 	MLX5_REG_PFCC		 = 0x5007,
141 	MLX5_REG_PPCNT		 = 0x5008,
142 	MLX5_REG_PUDE		 = 0x5009,
143 	MLX5_REG_PPTB		 = 0x500B,
144 	MLX5_REG_PBMC		 = 0x500C,
145 	MLX5_REG_PELC		 = 0x500E,
146 	MLX5_REG_PVLC		 = 0x500F,
147 	MLX5_REG_PMPE		 = 0x5010,
148 	MLX5_REG_PMAOS		 = 0x5012,
149 	MLX5_REG_PPLM		 = 0x5023,
150 	MLX5_REG_PDDR		 = 0x5031,
151 	MLX5_REG_PBSR		 = 0x5038,
152 	MLX5_REG_PCAM		 = 0x507f,
153 	MLX5_REG_NODE_DESC	 = 0x6001,
154 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
155 	MLX5_REG_MTMP		 = 0x900a,
156 	MLX5_REG_MCIA		 = 0x9014,
157 	MLX5_REG_MFRL		 = 0x9028,
158 	MLX5_REG_MPCNT		 = 0x9051,
159 	MLX5_REG_MCQI		 = 0x9061,
160 	MLX5_REG_MCC		 = 0x9062,
161 	MLX5_REG_MCDA		 = 0x9063,
162 	MLX5_REG_MCAM		 = 0x907f,
163 };
164 
165 enum dbg_rsc_type {
166 	MLX5_DBG_RSC_QP,
167 	MLX5_DBG_RSC_EQ,
168 	MLX5_DBG_RSC_CQ,
169 };
170 
171 enum {
172 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
173 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
174 	MLX5_INTERFACE_NUMBER       = 2,
175 };
176 
177 struct mlx5_field_desc {
178 	int			i;
179 };
180 
181 struct mlx5_rsc_debug {
182 	struct mlx5_core_dev   *dev;
183 	void		       *object;
184 	enum dbg_rsc_type	type;
185 	struct mlx5_field_desc	fields[0];
186 };
187 
188 enum mlx5_dev_event {
189 	MLX5_DEV_EVENT_SYS_ERROR,
190 	MLX5_DEV_EVENT_PORT_UP,
191 	MLX5_DEV_EVENT_PORT_DOWN,
192 	MLX5_DEV_EVENT_PORT_INITIALIZED,
193 	MLX5_DEV_EVENT_LID_CHANGE,
194 	MLX5_DEV_EVENT_PKEY_CHANGE,
195 	MLX5_DEV_EVENT_GUID_CHANGE,
196 	MLX5_DEV_EVENT_CLIENT_REREG,
197 	MLX5_DEV_EVENT_VPORT_CHANGE,
198 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
199 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
200 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
201 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
202 };
203 
204 enum mlx5_port_status {
205 	MLX5_PORT_UP        = 1 << 0,
206 	MLX5_PORT_DOWN      = 1 << 1,
207 };
208 
209 enum {
210 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
211 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
212 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
213 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
214 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
215 	MLX5_VSC_DATA_OFFSET	 = 0x14,
216 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
217 };
218 
219 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
220 
221 struct mlx5_cmd_first {
222 	__be32		data[4];
223 };
224 
225 struct cache_ent;
226 struct mlx5_fw_page {
227 	union {
228 		struct rb_node rb_node;
229 		struct list_head list;
230 	};
231 	struct mlx5_cmd_first first;
232 	struct mlx5_core_dev *dev;
233 	bus_dmamap_t dma_map;
234 	bus_addr_t dma_addr;
235 	void *virt_addr;
236 	struct cache_ent *cache;
237 	u32 numpages;
238 	u16 load_done;
239 #define	MLX5_LOAD_ST_NONE 0
240 #define	MLX5_LOAD_ST_SUCCESS 1
241 #define	MLX5_LOAD_ST_FAILURE 2
242 	u16 func_id;
243 };
244 #define	mlx5_cmd_msg mlx5_fw_page
245 
246 struct mlx5_cmd_debug {
247 	void		       *in_msg;
248 	void		       *out_msg;
249 	u8			status;
250 	u16			inlen;
251 	u16			outlen;
252 };
253 
254 struct cache_ent {
255 	/* protect block chain allocations
256 	 */
257 	spinlock_t		lock;
258 	struct list_head	head;
259 };
260 
261 struct cmd_msg_cache {
262 	struct cache_ent	large;
263 	struct cache_ent	med;
264 
265 };
266 
267 struct mlx5_traffic_counter {
268 	u64         packets;
269 	u64         octets;
270 };
271 
272 enum mlx5_cmd_mode {
273 	MLX5_CMD_MODE_POLLING,
274 	MLX5_CMD_MODE_EVENTS
275 };
276 
277 struct mlx5_cmd_stats {
278 	u64		sum;
279 	u64		n;
280 	/* protect command average calculations */
281 	spinlock_t	lock;
282 };
283 
284 struct mlx5_cmd {
285 	struct mlx5_fw_page *cmd_page;
286 	bus_dma_tag_t dma_tag;
287 	struct sx dma_sx;
288 	struct mtx dma_mtx;
289 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
290 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
291 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
292 	struct cv dma_cv;
293 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
294 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
295 	void	       *cmd_buf;
296 	dma_addr_t	dma;
297 	u16		cmdif_rev;
298 	u8		log_sz;
299 	u8		log_stride;
300 	int		max_reg_cmds;
301 	int		events;
302 	u32 __iomem    *vector;
303 
304 	/* protect command queue allocations
305 	 */
306 	spinlock_t	alloc_lock;
307 
308 	/* protect token allocations
309 	 */
310 	spinlock_t	token_lock;
311 	u8		token;
312 	unsigned long	bitmask;
313 	struct semaphore sem;
314 	struct semaphore pages_sem;
315 	enum mlx5_cmd_mode mode;
316 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
317 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
318 	struct mlx5_cmd_debug dbg;
319 	struct cmd_msg_cache cache;
320 	int checksum_disabled;
321 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
322 };
323 
324 struct mlx5_port_caps {
325 	int	gid_table_len;
326 	int	pkey_table_len;
327 	u8	ext_port_cap;
328 };
329 
330 struct mlx5_buf {
331 	bus_dma_tag_t		dma_tag;
332 	bus_dmamap_t		dma_map;
333 	struct mlx5_core_dev   *dev;
334 	struct {
335 		void	       *buf;
336 	} direct;
337 	u64		       *page_list;
338 	int			npages;
339 	int			size;
340 	u8			page_shift;
341 	u8			load_done;
342 };
343 
344 struct mlx5_frag_buf {
345 	struct mlx5_buf_list	*frags;
346 	int			npages;
347 	int			size;
348 	u8			page_shift;
349 };
350 
351 struct mlx5_eq {
352 	struct mlx5_core_dev   *dev;
353 	__be32 __iomem	       *doorbell;
354 	u32			cons_index;
355 	struct mlx5_buf		buf;
356 	int			size;
357 	u8			irqn;
358 	u8			eqn;
359 	int			nent;
360 	u64			mask;
361 	struct list_head	list;
362 	int			index;
363 	struct mlx5_rsc_debug	*dbg;
364 };
365 
366 struct mlx5_core_psv {
367 	u32	psv_idx;
368 	struct psv_layout {
369 		u32	pd;
370 		u16	syndrome;
371 		u16	reserved;
372 		u16	bg;
373 		u16	app_tag;
374 		u32	ref_tag;
375 	} psv;
376 };
377 
378 struct mlx5_core_sig_ctx {
379 	struct mlx5_core_psv	psv_memory;
380 	struct mlx5_core_psv	psv_wire;
381 	struct ib_sig_err       err_item;
382 	bool			sig_status_checked;
383 	bool			sig_err_exists;
384 	u32			sigerr_count;
385 };
386 
387 enum {
388 	MLX5_MKEY_MR = 1,
389 	MLX5_MKEY_MW,
390 	MLX5_MKEY_INDIRECT_DEVX,
391 };
392 
393 struct mlx5_core_mkey {
394 	u64			iova;
395 	u64			size;
396 	u32			key;
397 	u32			pd;
398 	u32			type;
399 };
400 
401 enum mlx5_res_type {
402 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
403 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
404 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
405 	MLX5_RES_SRQ	= 3,
406 	MLX5_RES_XSRQ	= 4,
407 	MLX5_RES_XRQ	= 5,
408 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
409 };
410 
411 struct mlx5_core_rsc_common {
412 	enum mlx5_res_type	res;
413 	atomic_t		refcount;
414 	struct completion	free;
415 };
416 
417 struct mlx5_uars_page {
418 	void __iomem	       *map;
419 	bool			wc;
420 	u32			index;
421 	struct list_head	list;
422 	unsigned int		bfregs;
423 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
424 	unsigned long	       *fp_bitmap;
425 	unsigned int		reg_avail;
426 	unsigned int		fp_avail;
427 	struct kref		ref_count;
428 	struct mlx5_core_dev   *mdev;
429 };
430 
431 struct mlx5_bfreg_head {
432 	/* protect blue flame registers allocations */
433 	struct mutex		lock;
434 	struct list_head	list;
435 };
436 
437 struct mlx5_bfreg_data {
438 	struct mlx5_bfreg_head	reg_head;
439 	struct mlx5_bfreg_head	wc_head;
440 };
441 
442 struct mlx5_sq_bfreg {
443 	void __iomem	       *map;
444 	struct mlx5_uars_page  *up;
445 	bool			wc;
446 	u32			index;
447 	unsigned int		offset;
448 };
449 
450 struct mlx5_core_srq {
451 	struct mlx5_core_rsc_common	common; /* must be first */
452 	u32				srqn;
453 	int				max;
454 	size_t				max_gs;
455 	size_t				max_avail_gather;
456 	int				wqe_shift;
457 	void				(*event)(struct mlx5_core_srq *, int);
458 	atomic_t			refcount;
459 	struct completion		free;
460 };
461 
462 struct mlx5_ib_dev;
463 struct mlx5_eq_table {
464 	void __iomem	       *update_ci;
465 	void __iomem	       *update_arm_ci;
466 	struct list_head	comp_eqs_list;
467 	struct mlx5_eq		pages_eq;
468 	struct mlx5_eq		async_eq;
469 	struct mlx5_eq		cmd_eq;
470 	int			num_comp_vectors;
471 	spinlock_t		lock;	/* protect EQs list */
472 	struct mlx5_ib_dev	*dev;	/* for devx event notifier */
473 	bool (*cb)(struct mlx5_core_dev *mdev,
474 		   uint8_t event_type, void *data);
475 };
476 
477 struct mlx5_core_health {
478 	struct mlx5_health_buffer __iomem	*health;
479 	__be32 __iomem		       *health_counter;
480 	struct timer_list		timer;
481 	u32				prev;
482 	int				miss_counter;
483 	u32				fatal_error;
484 	struct workqueue_struct	       *wq_watchdog;
485 	struct work_struct		work_watchdog;
486 	/* wq spinlock to synchronize draining */
487 	spinlock_t			wq_lock;
488 	struct workqueue_struct	       *wq;
489 	unsigned long			flags;
490 	struct work_struct		work;
491 	struct delayed_work		recover_work;
492 	unsigned int			last_reset_req;
493 	struct work_struct		work_cmd_completion;
494 	struct workqueue_struct	       *wq_cmd;
495 };
496 
497 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
498 
499 struct mlx5_cq_linear_array_entry {
500 	struct mlx5_core_cq * volatile cq;
501 };
502 
503 struct mlx5_cq_table {
504 	/* protect radix tree
505 	 */
506 	spinlock_t		writerlock;
507 	atomic_t		writercount;
508 	struct radix_tree_root	tree;
509 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
510 };
511 
512 struct mlx5_qp_table {
513 	/* protect radix tree
514 	 */
515 	spinlock_t		lock;
516 	struct radix_tree_root	tree;
517 };
518 
519 struct mlx5_srq_table {
520 	/* protect radix tree
521 	 */
522 	spinlock_t		lock;
523 	struct radix_tree_root	tree;
524 };
525 
526 struct mlx5_mr_table {
527 	/* protect radix tree
528 	 */
529 	spinlock_t		lock;
530 	struct radix_tree_root	tree;
531 };
532 
533 #ifdef RATELIMIT
534 struct mlx5_rl_entry {
535 	u32			rate;
536 	u16			burst;
537 	u16			index;
538 	u32			qos_handle; /* schedule queue handle */
539 	u32			refcount;
540 };
541 
542 struct mlx5_rl_table {
543 	struct mutex		rl_lock;
544 	u16			max_size;
545 	u32			max_rate;
546 	u32			min_rate;
547 	struct mlx5_rl_entry   *rl_entry;
548 };
549 #endif
550 
551 struct mlx5_pme_stats {
552 	u64			status_counters[MLX5_MODULE_STATUS_NUM];
553 	u64			error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
554 };
555 
556 struct mlx5_priv {
557 	char			name[MLX5_MAX_NAME_LEN];
558 	struct mlx5_eq_table	eq_table;
559 	struct msix_entry	*msix_arr;
560 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
561 	int			disable_irqs;
562 
563 	/* pages stuff */
564 	struct workqueue_struct *pg_wq;
565 	struct rb_root		page_root;
566 	s64			fw_pages;
567 	atomic_t		reg_pages;
568 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
569 	struct mlx5_core_health health;
570 
571 	struct mlx5_srq_table	srq_table;
572 
573 	/* start: qp staff */
574 	struct mlx5_qp_table	qp_table;
575 
576 	/* end: qp staff */
577 
578 	/* start: cq staff */
579 	struct mlx5_cq_table	cq_table;
580 	/* end: cq staff */
581 
582 	/* start: mr staff */
583 	struct mlx5_mr_table	mr_table;
584 	/* end: mr staff */
585 
586 	/* start: alloc staff */
587 	int			numa_node;
588 
589 	struct mutex   pgdir_mutex;
590 	struct list_head        pgdir_list;
591 	/* end: alloc staff */
592 
593 	/* protect mkey key part */
594 	spinlock_t		mkey_lock;
595 	u8			mkey_key;
596 
597 	struct list_head        dev_list;
598 	struct list_head        ctx_list;
599 	spinlock_t              ctx_lock;
600 	unsigned long		pci_dev_data;
601 #ifdef RATELIMIT
602 	struct mlx5_rl_table	rl_table;
603 #endif
604 	struct mlx5_pme_stats pme_stats;
605 
606 	struct mlx5_eswitch	*eswitch;
607 
608 	struct mlx5_bfreg_data		bfregs;
609 	struct mlx5_uars_page	       *uar;
610 };
611 
612 enum mlx5_device_state {
613 	MLX5_DEVICE_STATE_UP,
614 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
615 };
616 
617 enum mlx5_interface_state {
618 	MLX5_INTERFACE_STATE_UP = 0x1,
619 	MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
620 };
621 
622 enum mlx5_pci_status {
623 	MLX5_PCI_STATUS_DISABLED,
624 	MLX5_PCI_STATUS_ENABLED,
625 };
626 
627 #define	MLX5_MAX_RESERVED_GIDS	8
628 
629 struct mlx5_rsvd_gids {
630 	unsigned int start;
631 	unsigned int count;
632 	struct ida ida;
633 };
634 
635 struct mlx5_special_contexts {
636 	int resd_lkey;
637 };
638 
639 struct mlx5_diag_cnt_id {
640 	u16	id;
641 	bool	enabled;
642 };
643 
644 struct mlx5_diag_cnt {
645 #define	DIAG_LOCK(dc) mutex_lock(&(dc)->lock)
646 #define	DIAG_UNLOCK(dc) mutex_unlock(&(dc)->lock)
647 	struct mutex lock;
648 	struct sysctl_ctx_list sysctl_ctx;
649 	struct mlx5_diag_cnt_id *cnt_id;
650 	u16	num_of_samples;
651 	u16	sample_index;
652 	u8	num_cnt_id;
653 	u8	log_num_of_samples;
654 	u8	log_sample_period;
655 	u8	flag;
656 	u8	ready;
657 };
658 
659 struct mlx5_flow_root_namespace;
660 struct mlx5_core_dev {
661 	struct pci_dev	       *pdev;
662 	/* sync pci state */
663 	struct mutex		pci_status_mutex;
664 	enum mlx5_pci_status	pci_status;
665 	char			board_id[MLX5_BOARD_ID_LEN];
666 	struct mlx5_cmd		cmd;
667 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
668 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
669 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
670 	struct {
671 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
672 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
673 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
674 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
675 	} caps;
676 	phys_addr_t		iseg_base;
677 	struct mlx5_init_seg __iomem *iseg;
678 	enum mlx5_device_state	state;
679 	/* sync interface state */
680 	struct mutex		intf_state_mutex;
681 	unsigned long		intf_state;
682 	void			(*event) (struct mlx5_core_dev *dev,
683 					  enum mlx5_dev_event event,
684 					  unsigned long param);
685 	struct mlx5_priv	priv;
686 	struct mlx5_profile	*profile;
687 	atomic_t		num_qps;
688 	struct mlx5_diag_cnt	diag_cnt;
689 	u32			vsc_addr;
690 	u32			issi;
691 	struct mlx5_special_contexts special_contexts;
692 	unsigned int module_status[MLX5_MAX_PORTS];
693 	struct mlx5_flow_root_namespace *root_ns;
694 	struct mlx5_flow_root_namespace *fdb_root_ns;
695 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
696 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
697 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
698 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
699 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
700 	struct mlx5_crspace_regmap *dump_rege;
701 	uint32_t *dump_data;
702 	unsigned dump_size;
703 	bool dump_valid;
704 	bool dump_copyout;
705 	struct mtx dump_lock;
706 
707 	struct sysctl_ctx_list	sysctl_ctx;
708 	int			msix_eqvec;
709 	int			pwr_status;
710 	int			pwr_value;
711 
712 	struct {
713 		struct mlx5_rsvd_gids	reserved_gids;
714 		atomic_t		roce_en;
715 	} roce;
716 
717 	struct {
718 		spinlock_t	spinlock;
719 #define	MLX5_MPFS_TABLE_MAX 32
720 		long		bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
721 	} mpfs;
722 #ifdef CONFIG_MLX5_FPGA
723 	struct mlx5_fpga_device	*fpga;
724 #endif
725 };
726 
727 enum {
728 	MLX5_WOL_DISABLE       = 0,
729 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
730 	MLX5_WOL_MAGIC         = 1 << 2,
731 	MLX5_WOL_ARP           = 1 << 3,
732 	MLX5_WOL_BROADCAST     = 1 << 4,
733 	MLX5_WOL_MULTICAST     = 1 << 5,
734 	MLX5_WOL_UNICAST       = 1 << 6,
735 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
736 };
737 
738 struct mlx5_db {
739 	__be32			*db;
740 	union {
741 		struct mlx5_db_pgdir		*pgdir;
742 		struct mlx5_ib_user_db_page	*user_page;
743 	}			u;
744 	dma_addr_t		dma;
745 	int			index;
746 };
747 
748 struct mlx5_net_counters {
749 	u64	packets;
750 	u64	octets;
751 };
752 
753 struct mlx5_ptys_reg {
754 	u8	an_dis_admin;
755 	u8	an_dis_ap;
756 	u8	local_port;
757 	u8	proto_mask;
758 	u32	eth_proto_cap;
759 	u16	ib_link_width_cap;
760 	u16	ib_proto_cap;
761 	u32	eth_proto_admin;
762 	u16	ib_link_width_admin;
763 	u16	ib_proto_admin;
764 	u32	eth_proto_oper;
765 	u16	ib_link_width_oper;
766 	u16	ib_proto_oper;
767 	u32	eth_proto_lp_advertise;
768 };
769 
770 struct mlx5_pvlc_reg {
771 	u8	local_port;
772 	u8	vl_hw_cap;
773 	u8	vl_admin;
774 	u8	vl_operational;
775 };
776 
777 struct mlx5_pmtu_reg {
778 	u8	local_port;
779 	u16	max_mtu;
780 	u16	admin_mtu;
781 	u16	oper_mtu;
782 };
783 
784 struct mlx5_vport_counters {
785 	struct mlx5_net_counters	received_errors;
786 	struct mlx5_net_counters	transmit_errors;
787 	struct mlx5_net_counters	received_ib_unicast;
788 	struct mlx5_net_counters	transmitted_ib_unicast;
789 	struct mlx5_net_counters	received_ib_multicast;
790 	struct mlx5_net_counters	transmitted_ib_multicast;
791 	struct mlx5_net_counters	received_eth_broadcast;
792 	struct mlx5_net_counters	transmitted_eth_broadcast;
793 	struct mlx5_net_counters	received_eth_unicast;
794 	struct mlx5_net_counters	transmitted_eth_unicast;
795 	struct mlx5_net_counters	received_eth_multicast;
796 	struct mlx5_net_counters	transmitted_eth_multicast;
797 };
798 
799 enum {
800 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
801 };
802 
803 struct mlx5_core_dct {
804 	struct mlx5_core_rsc_common	common; /* must be first */
805 	void (*event)(struct mlx5_core_dct *, int);
806 	int			dctn;
807 	struct completion	drained;
808 	struct mlx5_rsc_debug	*dbg;
809 	int			pid;
810 	u16			uid;
811 };
812 
813 enum {
814 	MLX5_PTYS_IB = 1 << 0,
815 	MLX5_PTYS_EN = 1 << 2,
816 };
817 
818 struct mlx5_db_pgdir {
819 	struct list_head	list;
820 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
821 	struct mlx5_fw_page    *fw_page;
822 	__be32		       *db_page;
823 	dma_addr_t		db_dma;
824 };
825 
826 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
827 
828 struct mlx5_cmd_work_ent {
829 	struct mlx5_cmd_msg    *in;
830 	struct mlx5_cmd_msg    *out;
831 	int			uin_size;
832 	void		       *uout;
833 	int			uout_size;
834 	mlx5_cmd_cbk_t		callback;
835         struct delayed_work     cb_timeout_work;
836 	void		       *context;
837 	int			idx;
838 	struct completion	done;
839 	struct mlx5_cmd        *cmd;
840 	struct work_struct	work;
841 	struct mlx5_cmd_layout *lay;
842 	int			ret;
843 	int			page_queue;
844 	u8			status;
845 	u8			token;
846 	u64			ts1;
847 	u64			ts2;
848 	u16			op;
849 	u8			busy;
850 	bool			polling;
851 };
852 
853 struct mlx5_pas {
854 	u64	pa;
855 	u8	log_sz;
856 };
857 
858 enum port_state_policy {
859 	MLX5_POLICY_DOWN        = 0,
860 	MLX5_POLICY_UP          = 1,
861 	MLX5_POLICY_FOLLOW      = 2,
862 	MLX5_POLICY_INVALID     = 0xffffffff
863 };
864 
865 static inline void *
866 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
867 {
868 	return ((char *)buf->direct.buf + offset);
869 }
870 
871 
872 extern struct workqueue_struct *mlx5_core_wq;
873 
874 #define STRUCT_FIELD(header, field) \
875 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
876 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
877 
878 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
879 {
880 	return pci_get_drvdata(pdev);
881 }
882 
883 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
884 {
885 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
886 }
887 
888 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
889 {
890 	return ioread32be(&dev->iseg->fw_rev) >> 16;
891 }
892 
893 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
894 {
895 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
896 }
897 
898 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
899 {
900 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
901 }
902 
903 static inline int mlx5_get_gid_table_len(u16 param)
904 {
905 	if (param > 4) {
906 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
907 		return 0;
908 	}
909 
910 	return 8 * (1 << param);
911 }
912 
913 static inline void *mlx5_vzalloc(unsigned long size)
914 {
915 	void *rtn;
916 
917 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
918 	return rtn;
919 }
920 
921 static inline void *mlx5_vmalloc(unsigned long size)
922 {
923 	void *rtn;
924 
925 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
926 	if (!rtn)
927 		rtn = vmalloc(size);
928 	return rtn;
929 }
930 
931 static inline u32 mlx5_base_mkey(const u32 key)
932 {
933 	return key & 0xffffff00u;
934 }
935 
936 int mlx5_cmd_init(struct mlx5_core_dev *dev);
937 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
938 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
939 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
940 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
941 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
942 
943 struct mlx5_async_ctx {
944 	struct mlx5_core_dev *dev;
945 	atomic_t num_inflight;
946 	struct wait_queue_head wait;
947 };
948 
949 struct mlx5_async_work;
950 
951 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
952 
953 struct mlx5_async_work {
954 	struct mlx5_async_ctx *ctx;
955 	mlx5_async_cbk_t user_callback;
956 };
957 
958 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
959 			     struct mlx5_async_ctx *ctx);
960 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
961 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
962 		     void *out, int out_size, mlx5_async_cbk_t callback,
963 		     struct mlx5_async_work *work);
964 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
965 		  int out_size);
966 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
967 			  void *out, int out_size);
968 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
969 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
970 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
971 		     bool map_wc, bool fast_path);
972 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
973 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
974 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
975 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
976 int mlx5_health_init(struct mlx5_core_dev *dev);
977 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
978 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
979 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
980 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
981 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
982 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
983 
984 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
985 		   struct mlx5_buf *buf);
986 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
987 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
988 			 struct mlx5_srq_attr *in);
989 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
990 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
991 			struct mlx5_srq_attr *out);
992 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
993 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
994 		      u16 lwm, int is_srq);
995 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
996 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
997 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
998 			     struct mlx5_core_mkey *mkey,
999 			     struct mlx5_async_ctx *async_ctx, u32 *in,
1000 			     int inlen, u32 *out, int outlen,
1001 			     mlx5_async_cbk_t callback,
1002 			     struct mlx5_async_work *context);
1003 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1004 			  struct mlx5_core_mkey *mr,
1005 			  u32 *in, int inlen);
1006 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey);
1007 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1008 			 u32 *out, int outlen);
1009 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mr,
1010 			     u32 *mkey);
1011 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn, u16 uid);
1012 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid);
1013 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1014 		      u16 opmod, u8 port);
1015 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1016 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1017 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1018 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1019 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1020 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1021 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1022 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1023 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1024 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1025 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1026 				 s32 npages);
1027 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1028 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1029 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1030 void mlx5_register_debugfs(void);
1031 void mlx5_unregister_debugfs(void);
1032 int mlx5_eq_init(struct mlx5_core_dev *dev);
1033 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1034 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1035 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1036 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1037 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1038 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1039 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1040 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1041 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1042 		       int nent, u64 mask);
1043 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1044 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1045 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1046 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1047 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1048 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1049 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1050 				u64 addr);
1051 
1052 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1053 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1054 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1055 			 int size_in, void *data_out, int size_out,
1056 			 u16 reg_num, int arg, int write);
1057 
1058 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1059 
1060 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1061 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1062 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1063 		       u32 *out, int outlen);
1064 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1065 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1066 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1067 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1068 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1069 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1070 
1071 static inline struct domainset *
1072 mlx5_dev_domainset(struct mlx5_core_dev *mdev)
1073 {
1074 	return (linux_get_vm_domain_set(mdev->priv.numa_node));
1075 }
1076 
1077 const char *mlx5_command_str(int command);
1078 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1079 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1080 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1081 			 int npsvs, u32 *sig_index);
1082 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1083 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1084 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1085 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1086 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1087 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1088 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1089 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1090 			  struct mlx5_pvlc_reg *pvlc, int write);
1091 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1092 			  struct mlx5_ptys_reg *ptys, int write);
1093 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1094 			  struct mlx5_pmtu_reg *pmtu, int write);
1095 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1096 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1097 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1098 				int priority, int *is_enable);
1099 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1100 				 int priority, int enable);
1101 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1102 				void *out, int out_size);
1103 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1104 				 void *in, int in_size);
1105 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1106 				    void *out, int out_size);
1107 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1108 			       int in_size);
1109 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1110 				   u8 num_of_samples, u16 sample_index,
1111 				   void *out, int out_size);
1112 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1113 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1114 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1115 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1116 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1117 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1118 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1119 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1120 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1121 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1122 			       u16 *p_power, u8 *p_status);
1123 
1124 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1125 {
1126 	return mkey >> 8;
1127 }
1128 
1129 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1130 {
1131 	return mkey_idx << 8;
1132 }
1133 
1134 static inline u8 mlx5_mkey_variant(u32 mkey)
1135 {
1136 	return mkey & 0xff;
1137 }
1138 
1139 enum {
1140 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1141 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1142 };
1143 
1144 enum {
1145 	MAX_MR_CACHE_ENTRIES    = 15,
1146 };
1147 
1148 struct mlx5_interface {
1149 	void *			(*add)(struct mlx5_core_dev *dev);
1150 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1151 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1152 					 enum mlx5_dev_event event, unsigned long param);
1153 	void *                  (*get_dev)(void *context);
1154 	int			protocol;
1155 	struct list_head	list;
1156 };
1157 
1158 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1159 int mlx5_register_interface(struct mlx5_interface *intf);
1160 void mlx5_unregister_interface(struct mlx5_interface *intf);
1161 
1162 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1163 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1164     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1165     const u8 *mac, bool vlan, u16 vlan_id);
1166 
1167 struct mlx5_profile {
1168 	u64	mask;
1169 	u8	log_max_qp;
1170 	struct {
1171 		int	size;
1172 		int	limit;
1173 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1174 };
1175 
1176 enum {
1177 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1178 };
1179 
1180 enum {
1181 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1182 };
1183 
1184 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1185 {
1186 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1187 }
1188 #ifdef RATELIMIT
1189 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1190 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1191 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1192 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1193 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1194 int mlx5e_query_rate_limit_cmd(struct mlx5_core_dev *dev, u16 index, u32 *scq_handle);
1195 
1196 static inline u32 mlx5_rl_get_scq_handle(struct mlx5_core_dev *dev, uint16_t index)
1197 {
1198 	KASSERT(index > 0,
1199 	    ("invalid rate index for sq remap, failed retrieving SCQ handle"));
1200 
1201         return (dev->priv.rl_table.rl_entry[index - 1].qos_handle);
1202 }
1203 
1204 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1205 {
1206 	return !!(dev->priv.rl_table.max_size);
1207 }
1208 #endif
1209 
1210 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1211 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1212 
1213 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
1214 {
1215         return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
1216                        MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
1217                        MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
1218 }
1219 
1220 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev)
1221 {
1222         return !MLX5_CAP_GEN(dev, rq_ts_format) ?
1223                        MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1224                        MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;
1225 }
1226 
1227 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev)
1228 {
1229         return !MLX5_CAP_GEN(dev, sq_ts_format) ?
1230                        MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :
1231                        MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;
1232 }
1233 
1234 #endif /* MLX5_DRIVER_H */
1235