1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include "opt_ratelimit.h" 32 33 #include <linux/kernel.h> 34 #include <linux/completion.h> 35 #include <linux/pci.h> 36 #include <linux/cache.h> 37 #include <linux/rbtree.h> 38 #include <linux/if_ether.h> 39 #include <linux/semaphore.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <linux/radix-tree.h> 43 44 #include <dev/mlx5/device.h> 45 #include <dev/mlx5/doorbell.h> 46 #include <dev/mlx5/srq.h> 47 48 #define MLX5_QCOUNTER_SETS_NETDEV 64 49 #define MLX5_MAX_NUMBER_OF_VFS 128 50 51 enum { 52 MLX5_BOARD_ID_LEN = 64, 53 MLX5_MAX_NAME_LEN = 16, 54 }; 55 56 enum { 57 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 58 MLX5_CMD_WQ_MAX_NAME = 32, 59 }; 60 61 enum { 62 CMD_OWNER_SW = 0x0, 63 CMD_OWNER_HW = 0x1, 64 CMD_STATUS_SUCCESS = 0, 65 }; 66 67 enum mlx5_sqp_t { 68 MLX5_SQP_SMI = 0, 69 MLX5_SQP_GSI = 1, 70 MLX5_SQP_IEEE_1588 = 2, 71 MLX5_SQP_SNIFFER = 3, 72 MLX5_SQP_SYNC_UMR = 4, 73 }; 74 75 enum { 76 MLX5_MAX_PORTS = 2, 77 }; 78 79 enum { 80 MLX5_EQ_VEC_PAGES = 0, 81 MLX5_EQ_VEC_CMD = 1, 82 MLX5_EQ_VEC_ASYNC = 2, 83 MLX5_EQ_VEC_COMP_BASE, 84 }; 85 86 enum { 87 MLX5_MAX_IRQ_NAME = 32 88 }; 89 90 enum { 91 MLX5_ATOMIC_MODE_OFF = 16, 92 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 99 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 100 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 101 }; 102 103 enum { 104 MLX5_ATOMIC_MODE_DCT_OFF = 20, 105 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 112 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 113 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 114 }; 115 116 enum { 117 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 118 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 119 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 120 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 121 }; 122 123 enum { 124 MLX5_REG_QETCR = 0x4005, 125 MLX5_REG_QPDP = 0x4007, 126 MLX5_REG_QTCT = 0x400A, 127 MLX5_REG_QHLL = 0x4016, 128 MLX5_REG_DCBX_PARAM = 0x4020, 129 MLX5_REG_DCBX_APP = 0x4021, 130 MLX5_REG_PCAP = 0x5001, 131 MLX5_REG_PMTU = 0x5003, 132 MLX5_REG_PTYS = 0x5004, 133 MLX5_REG_PAOS = 0x5006, 134 MLX5_REG_PFCC = 0x5007, 135 MLX5_REG_PPCNT = 0x5008, 136 MLX5_REG_PMAOS = 0x5012, 137 MLX5_REG_PUDE = 0x5009, 138 MLX5_REG_PPTB = 0x500B, 139 MLX5_REG_PBMC = 0x500C, 140 MLX5_REG_PMPE = 0x5010, 141 MLX5_REG_PELC = 0x500e, 142 MLX5_REG_PVLC = 0x500f, 143 MLX5_REG_PMLP = 0x5002, 144 MLX5_REG_NODE_DESC = 0x6001, 145 MLX5_REG_HOST_ENDIANNESS = 0x7004, 146 MLX5_REG_MCIA = 0x9014, 147 MLX5_REG_MPCNT = 0x9051, 148 }; 149 150 enum dbg_rsc_type { 151 MLX5_DBG_RSC_QP, 152 MLX5_DBG_RSC_EQ, 153 MLX5_DBG_RSC_CQ, 154 }; 155 156 enum { 157 MLX5_INTERFACE_PROTOCOL_IB = 0, 158 MLX5_INTERFACE_PROTOCOL_ETH = 1, 159 MLX5_INTERFACE_NUMBER = 2, 160 }; 161 162 struct mlx5_field_desc { 163 struct dentry *dent; 164 int i; 165 }; 166 167 struct mlx5_rsc_debug { 168 struct mlx5_core_dev *dev; 169 void *object; 170 enum dbg_rsc_type type; 171 struct dentry *root; 172 struct mlx5_field_desc fields[0]; 173 }; 174 175 enum mlx5_dev_event { 176 MLX5_DEV_EVENT_SYS_ERROR, 177 MLX5_DEV_EVENT_PORT_UP, 178 MLX5_DEV_EVENT_PORT_DOWN, 179 MLX5_DEV_EVENT_PORT_INITIALIZED, 180 MLX5_DEV_EVENT_LID_CHANGE, 181 MLX5_DEV_EVENT_PKEY_CHANGE, 182 MLX5_DEV_EVENT_GUID_CHANGE, 183 MLX5_DEV_EVENT_CLIENT_REREG, 184 MLX5_DEV_EVENT_VPORT_CHANGE, 185 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 186 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 187 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 188 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 189 }; 190 191 enum mlx5_port_status { 192 MLX5_PORT_UP = 1 << 0, 193 MLX5_PORT_DOWN = 1 << 1, 194 }; 195 196 enum mlx5_link_mode { 197 MLX5_1000BASE_CX_SGMII = 0, 198 MLX5_1000BASE_KX = 1, 199 MLX5_10GBASE_CX4 = 2, 200 MLX5_10GBASE_KX4 = 3, 201 MLX5_10GBASE_KR = 4, 202 MLX5_20GBASE_KR2 = 5, 203 MLX5_40GBASE_CR4 = 6, 204 MLX5_40GBASE_KR4 = 7, 205 MLX5_56GBASE_R4 = 8, 206 MLX5_10GBASE_CR = 12, 207 MLX5_10GBASE_SR = 13, 208 MLX5_10GBASE_ER = 14, 209 MLX5_40GBASE_SR4 = 15, 210 MLX5_40GBASE_LR4 = 16, 211 MLX5_100GBASE_CR4 = 20, 212 MLX5_100GBASE_SR4 = 21, 213 MLX5_100GBASE_KR4 = 22, 214 MLX5_100GBASE_LR4 = 23, 215 MLX5_100BASE_TX = 24, 216 MLX5_1000BASE_T = 25, 217 MLX5_10GBASE_T = 26, 218 MLX5_25GBASE_CR = 27, 219 MLX5_25GBASE_KR = 28, 220 MLX5_25GBASE_SR = 29, 221 MLX5_50GBASE_CR2 = 30, 222 MLX5_50GBASE_KR2 = 31, 223 MLX5_LINK_MODES_NUMBER, 224 }; 225 226 enum { 227 MLX5_VSC_SPACE_SUPPORTED = 0x1, 228 MLX5_VSC_SPACE_OFFSET = 0x4, 229 MLX5_VSC_COUNTER_OFFSET = 0x8, 230 MLX5_VSC_SEMA_OFFSET = 0xC, 231 MLX5_VSC_ADDR_OFFSET = 0x10, 232 MLX5_VSC_DATA_OFFSET = 0x14, 233 MLX5_VSC_MAX_RETRIES = 0x1000, 234 }; 235 236 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 237 238 struct mlx5_uuar_info { 239 struct mlx5_uar *uars; 240 int num_uars; 241 int num_low_latency_uuars; 242 unsigned long *bitmap; 243 unsigned int *count; 244 struct mlx5_bf *bfs; 245 246 /* 247 * protect uuar allocation data structs 248 */ 249 struct mutex lock; 250 u32 ver; 251 }; 252 253 struct mlx5_bf { 254 void __iomem *reg; 255 void __iomem *regreg; 256 int buf_size; 257 struct mlx5_uar *uar; 258 unsigned long offset; 259 int need_lock; 260 /* protect blue flame buffer selection when needed 261 */ 262 spinlock_t lock; 263 264 /* serialize 64 bit writes when done as two 32 bit accesses 265 */ 266 spinlock_t lock32; 267 int uuarn; 268 }; 269 270 struct mlx5_cmd_first { 271 __be32 data[4]; 272 }; 273 274 struct cache_ent; 275 struct mlx5_fw_page { 276 union { 277 struct rb_node rb_node; 278 struct list_head list; 279 }; 280 struct mlx5_cmd_first first; 281 struct mlx5_core_dev *dev; 282 bus_dmamap_t dma_map; 283 bus_addr_t dma_addr; 284 void *virt_addr; 285 struct cache_ent *cache; 286 u32 numpages; 287 u16 load_done; 288 #define MLX5_LOAD_ST_NONE 0 289 #define MLX5_LOAD_ST_SUCCESS 1 290 #define MLX5_LOAD_ST_FAILURE 2 291 u16 func_id; 292 }; 293 #define mlx5_cmd_msg mlx5_fw_page 294 295 struct mlx5_cmd_debug { 296 struct dentry *dbg_root; 297 struct dentry *dbg_in; 298 struct dentry *dbg_out; 299 struct dentry *dbg_outlen; 300 struct dentry *dbg_status; 301 struct dentry *dbg_run; 302 void *in_msg; 303 void *out_msg; 304 u8 status; 305 u16 inlen; 306 u16 outlen; 307 }; 308 309 struct cache_ent { 310 /* protect block chain allocations 311 */ 312 spinlock_t lock; 313 struct list_head head; 314 }; 315 316 struct cmd_msg_cache { 317 struct cache_ent large; 318 struct cache_ent med; 319 320 }; 321 322 struct mlx5_traffic_counter { 323 u64 packets; 324 u64 octets; 325 }; 326 327 struct mlx5_cmd_stats { 328 u64 sum; 329 u64 n; 330 struct dentry *root; 331 struct dentry *avg; 332 struct dentry *count; 333 /* protect command average calculations */ 334 spinlock_t lock; 335 }; 336 337 struct mlx5_cmd { 338 struct mlx5_fw_page *cmd_page; 339 bus_dma_tag_t dma_tag; 340 struct sx dma_sx; 341 struct mtx dma_mtx; 342 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 343 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 344 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 345 struct cv dma_cv; 346 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 347 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 348 void *cmd_buf; 349 dma_addr_t dma; 350 u16 cmdif_rev; 351 u8 log_sz; 352 u8 log_stride; 353 int max_reg_cmds; 354 int events; 355 u32 __iomem *vector; 356 357 /* protect command queue allocations 358 */ 359 spinlock_t alloc_lock; 360 361 /* protect token allocations 362 */ 363 spinlock_t token_lock; 364 u8 token; 365 unsigned long bitmask; 366 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 367 struct workqueue_struct *wq; 368 struct semaphore sem; 369 struct semaphore pages_sem; 370 int mode; 371 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 372 struct mlx5_cmd_debug dbg; 373 struct cmd_msg_cache cache; 374 int checksum_disabled; 375 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 376 }; 377 378 struct mlx5_port_caps { 379 int gid_table_len; 380 int pkey_table_len; 381 u8 ext_port_cap; 382 }; 383 384 struct mlx5_buf { 385 bus_dma_tag_t dma_tag; 386 bus_dmamap_t dma_map; 387 struct mlx5_core_dev *dev; 388 struct { 389 void *buf; 390 } direct; 391 u64 *page_list; 392 int npages; 393 int size; 394 u8 page_shift; 395 u8 load_done; 396 }; 397 398 struct mlx5_eq { 399 struct mlx5_core_dev *dev; 400 __be32 __iomem *doorbell; 401 u32 cons_index; 402 struct mlx5_buf buf; 403 int size; 404 u8 irqn; 405 u8 eqn; 406 int nent; 407 u64 mask; 408 struct list_head list; 409 int index; 410 struct mlx5_rsc_debug *dbg; 411 }; 412 413 struct mlx5_core_psv { 414 u32 psv_idx; 415 struct psv_layout { 416 u32 pd; 417 u16 syndrome; 418 u16 reserved; 419 u16 bg; 420 u16 app_tag; 421 u32 ref_tag; 422 } psv; 423 }; 424 425 struct mlx5_core_sig_ctx { 426 struct mlx5_core_psv psv_memory; 427 struct mlx5_core_psv psv_wire; 428 #if (__FreeBSD_version >= 1100000) 429 struct ib_sig_err err_item; 430 #endif 431 bool sig_status_checked; 432 bool sig_err_exists; 433 u32 sigerr_count; 434 }; 435 436 struct mlx5_core_mr { 437 u64 iova; 438 u64 size; 439 u32 key; 440 u32 pd; 441 }; 442 443 enum mlx5_res_type { 444 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 445 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 446 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 447 MLX5_RES_SRQ = 3, 448 MLX5_RES_XSRQ = 4, 449 MLX5_RES_DCT = 5, 450 }; 451 452 struct mlx5_core_rsc_common { 453 enum mlx5_res_type res; 454 atomic_t refcount; 455 struct completion free; 456 }; 457 458 struct mlx5_core_srq { 459 struct mlx5_core_rsc_common common; /* must be first */ 460 u32 srqn; 461 int max; 462 int max_gs; 463 int max_avail_gather; 464 int wqe_shift; 465 void (*event)(struct mlx5_core_srq *, int); 466 atomic_t refcount; 467 struct completion free; 468 }; 469 470 struct mlx5_eq_table { 471 void __iomem *update_ci; 472 void __iomem *update_arm_ci; 473 struct list_head comp_eqs_list; 474 struct mlx5_eq pages_eq; 475 struct mlx5_eq async_eq; 476 struct mlx5_eq cmd_eq; 477 int num_comp_vectors; 478 /* protect EQs list 479 */ 480 spinlock_t lock; 481 }; 482 483 struct mlx5_uar { 484 u32 index; 485 void __iomem *bf_map; 486 void __iomem *map; 487 }; 488 489 490 struct mlx5_core_health { 491 struct mlx5_health_buffer __iomem *health; 492 __be32 __iomem *health_counter; 493 struct timer_list timer; 494 u32 prev; 495 int miss_counter; 496 u32 fatal_error; 497 /* wq spinlock to synchronize draining */ 498 spinlock_t wq_lock; 499 struct workqueue_struct *wq; 500 unsigned long flags; 501 struct work_struct work; 502 struct delayed_work recover_work; 503 }; 504 505 #ifdef RATELIMIT 506 #define MLX5_CQ_LINEAR_ARRAY_SIZE (128 * 1024) 507 #else 508 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 509 #endif 510 511 struct mlx5_cq_linear_array_entry { 512 spinlock_t lock; 513 struct mlx5_core_cq * volatile cq; 514 }; 515 516 struct mlx5_cq_table { 517 /* protect radix tree 518 */ 519 spinlock_t lock; 520 struct radix_tree_root tree; 521 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 522 }; 523 524 struct mlx5_qp_table { 525 /* protect radix tree 526 */ 527 spinlock_t lock; 528 struct radix_tree_root tree; 529 }; 530 531 struct mlx5_srq_table { 532 /* protect radix tree 533 */ 534 spinlock_t lock; 535 struct radix_tree_root tree; 536 }; 537 538 struct mlx5_mr_table { 539 /* protect radix tree 540 */ 541 spinlock_t lock; 542 struct radix_tree_root tree; 543 }; 544 545 struct mlx5_irq_info { 546 char name[MLX5_MAX_IRQ_NAME]; 547 }; 548 549 #ifdef RATELIMIT 550 struct mlx5_rl_entry { 551 u32 rate; 552 u16 burst; 553 u16 index; 554 u32 refcount; 555 }; 556 557 struct mlx5_rl_table { 558 struct mutex rl_lock; 559 u16 max_size; 560 u32 max_rate; 561 u32 min_rate; 562 struct mlx5_rl_entry *rl_entry; 563 }; 564 #endif 565 566 struct mlx5_priv { 567 char name[MLX5_MAX_NAME_LEN]; 568 struct mlx5_eq_table eq_table; 569 struct msix_entry *msix_arr; 570 struct mlx5_irq_info *irq_info; 571 struct mlx5_uuar_info uuari; 572 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 573 574 struct io_mapping *bf_mapping; 575 576 /* pages stuff */ 577 struct workqueue_struct *pg_wq; 578 struct rb_root page_root; 579 s64 fw_pages; 580 atomic_t reg_pages; 581 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 582 struct mlx5_core_health health; 583 584 struct mlx5_srq_table srq_table; 585 586 /* start: qp staff */ 587 struct mlx5_qp_table qp_table; 588 struct dentry *qp_debugfs; 589 struct dentry *eq_debugfs; 590 struct dentry *cq_debugfs; 591 struct dentry *cmdif_debugfs; 592 /* end: qp staff */ 593 594 /* start: cq staff */ 595 struct mlx5_cq_table cq_table; 596 /* end: cq staff */ 597 598 /* start: mr staff */ 599 struct mlx5_mr_table mr_table; 600 /* end: mr staff */ 601 602 /* start: alloc staff */ 603 int numa_node; 604 605 struct mutex pgdir_mutex; 606 struct list_head pgdir_list; 607 /* end: alloc staff */ 608 struct dentry *dbg_root; 609 610 /* protect mkey key part */ 611 spinlock_t mkey_lock; 612 u8 mkey_key; 613 614 struct list_head dev_list; 615 struct list_head ctx_list; 616 spinlock_t ctx_lock; 617 unsigned long pci_dev_data; 618 #ifdef RATELIMIT 619 struct mlx5_rl_table rl_table; 620 #endif 621 }; 622 623 enum mlx5_device_state { 624 MLX5_DEVICE_STATE_UP, 625 MLX5_DEVICE_STATE_INTERNAL_ERROR, 626 }; 627 628 enum mlx5_interface_state { 629 MLX5_INTERFACE_STATE_DOWN = BIT(0), 630 MLX5_INTERFACE_STATE_UP = BIT(1), 631 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), 632 }; 633 634 enum mlx5_pci_status { 635 MLX5_PCI_STATUS_DISABLED, 636 MLX5_PCI_STATUS_ENABLED, 637 }; 638 639 struct mlx5_special_contexts { 640 int resd_lkey; 641 }; 642 643 struct mlx5_flow_root_namespace; 644 struct mlx5_dump_data; 645 struct mlx5_core_dev { 646 struct pci_dev *pdev; 647 /* sync pci state */ 648 struct mutex pci_status_mutex; 649 enum mlx5_pci_status pci_status; 650 char board_id[MLX5_BOARD_ID_LEN]; 651 struct mlx5_cmd cmd; 652 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 653 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 654 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 655 phys_addr_t iseg_base; 656 struct mlx5_init_seg __iomem *iseg; 657 enum mlx5_device_state state; 658 /* sync interface state */ 659 struct mutex intf_state_mutex; 660 unsigned long intf_state; 661 void (*event) (struct mlx5_core_dev *dev, 662 enum mlx5_dev_event event, 663 unsigned long param); 664 struct mlx5_priv priv; 665 struct mlx5_profile *profile; 666 atomic_t num_qps; 667 u32 vsc_addr; 668 u32 issi; 669 struct mlx5_special_contexts special_contexts; 670 unsigned int module_status[MLX5_MAX_PORTS]; 671 struct mlx5_flow_root_namespace *root_ns; 672 struct mlx5_flow_root_namespace *fdb_root_ns; 673 struct mlx5_flow_root_namespace *esw_egress_root_ns; 674 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 675 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 676 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 677 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 678 struct mlx5_dump_data *dump_data; 679 u32 vsec_addr; 680 }; 681 682 enum { 683 MLX5_WOL_DISABLE = 0, 684 MLX5_WOL_SECURED_MAGIC = 1 << 1, 685 MLX5_WOL_MAGIC = 1 << 2, 686 MLX5_WOL_ARP = 1 << 3, 687 MLX5_WOL_BROADCAST = 1 << 4, 688 MLX5_WOL_MULTICAST = 1 << 5, 689 MLX5_WOL_UNICAST = 1 << 6, 690 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 691 }; 692 693 struct mlx5_db { 694 __be32 *db; 695 union { 696 struct mlx5_db_pgdir *pgdir; 697 struct mlx5_ib_user_db_page *user_page; 698 } u; 699 dma_addr_t dma; 700 int index; 701 }; 702 703 struct mlx5_net_counters { 704 u64 packets; 705 u64 octets; 706 }; 707 708 struct mlx5_ptys_reg { 709 u8 an_dis_admin; 710 u8 an_dis_ap; 711 u8 local_port; 712 u8 proto_mask; 713 u32 eth_proto_cap; 714 u16 ib_link_width_cap; 715 u16 ib_proto_cap; 716 u32 eth_proto_admin; 717 u16 ib_link_width_admin; 718 u16 ib_proto_admin; 719 u32 eth_proto_oper; 720 u16 ib_link_width_oper; 721 u16 ib_proto_oper; 722 u32 eth_proto_lp_advertise; 723 }; 724 725 struct mlx5_pvlc_reg { 726 u8 local_port; 727 u8 vl_hw_cap; 728 u8 vl_admin; 729 u8 vl_operational; 730 }; 731 732 struct mlx5_pmtu_reg { 733 u8 local_port; 734 u16 max_mtu; 735 u16 admin_mtu; 736 u16 oper_mtu; 737 }; 738 739 struct mlx5_vport_counters { 740 struct mlx5_net_counters received_errors; 741 struct mlx5_net_counters transmit_errors; 742 struct mlx5_net_counters received_ib_unicast; 743 struct mlx5_net_counters transmitted_ib_unicast; 744 struct mlx5_net_counters received_ib_multicast; 745 struct mlx5_net_counters transmitted_ib_multicast; 746 struct mlx5_net_counters received_eth_broadcast; 747 struct mlx5_net_counters transmitted_eth_broadcast; 748 struct mlx5_net_counters received_eth_unicast; 749 struct mlx5_net_counters transmitted_eth_unicast; 750 struct mlx5_net_counters received_eth_multicast; 751 struct mlx5_net_counters transmitted_eth_multicast; 752 }; 753 754 enum { 755 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 756 }; 757 758 struct mlx5_core_dct { 759 struct mlx5_core_rsc_common common; /* must be first */ 760 void (*event)(struct mlx5_core_dct *, int); 761 int dctn; 762 struct completion drained; 763 struct mlx5_rsc_debug *dbg; 764 int pid; 765 }; 766 767 enum { 768 MLX5_COMP_EQ_SIZE = 1024, 769 }; 770 771 enum { 772 MLX5_PTYS_IB = 1 << 0, 773 MLX5_PTYS_EN = 1 << 2, 774 }; 775 776 struct mlx5_db_pgdir { 777 struct list_head list; 778 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 779 struct mlx5_fw_page *fw_page; 780 __be32 *db_page; 781 dma_addr_t db_dma; 782 }; 783 784 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 785 786 struct mlx5_cmd_work_ent { 787 struct mlx5_cmd_msg *in; 788 struct mlx5_cmd_msg *out; 789 int uin_size; 790 void *uout; 791 int uout_size; 792 mlx5_cmd_cbk_t callback; 793 struct delayed_work cb_timeout_work; 794 void *context; 795 int idx; 796 struct completion done; 797 struct mlx5_cmd *cmd; 798 struct work_struct work; 799 struct mlx5_cmd_layout *lay; 800 int ret; 801 int page_queue; 802 u8 status; 803 u8 token; 804 u64 ts1; 805 u64 ts2; 806 u16 op; 807 u8 busy; 808 bool polling; 809 }; 810 811 struct mlx5_pas { 812 u64 pa; 813 u8 log_sz; 814 }; 815 816 enum port_state_policy { 817 MLX5_POLICY_DOWN = 0, 818 MLX5_POLICY_UP = 1, 819 MLX5_POLICY_FOLLOW = 2, 820 MLX5_POLICY_INVALID = 0xffffffff 821 }; 822 823 static inline void * 824 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 825 { 826 return ((char *)buf->direct.buf + offset); 827 } 828 829 830 extern struct workqueue_struct *mlx5_core_wq; 831 832 #define STRUCT_FIELD(header, field) \ 833 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 834 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 835 836 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 837 { 838 return pci_get_drvdata(pdev); 839 } 840 841 extern struct dentry *mlx5_debugfs_root; 842 843 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 844 { 845 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 846 } 847 848 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 849 { 850 return ioread32be(&dev->iseg->fw_rev) >> 16; 851 } 852 853 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 854 { 855 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 856 } 857 858 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 859 { 860 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 861 } 862 863 static inline int mlx5_get_gid_table_len(u16 param) 864 { 865 if (param > 4) { 866 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 867 return 0; 868 } 869 870 return 8 * (1 << param); 871 } 872 873 static inline void *mlx5_vzalloc(unsigned long size) 874 { 875 void *rtn; 876 877 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 878 return rtn; 879 } 880 881 static inline void *mlx5_vmalloc(unsigned long size) 882 { 883 void *rtn; 884 885 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 886 if (!rtn) 887 rtn = vmalloc(size); 888 return rtn; 889 } 890 891 static inline u32 mlx5_base_mkey(const u32 key) 892 { 893 return key & 0xffffff00u; 894 } 895 896 int mlx5_cmd_init(struct mlx5_core_dev *dev); 897 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 898 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 899 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 900 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 901 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 902 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 903 int out_size); 904 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 905 void *out, int out_size, mlx5_cmd_cbk_t callback, 906 void *context); 907 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 908 void *out, int out_size); 909 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 910 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 911 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 912 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 913 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 914 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 915 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 916 int mlx5_health_init(struct mlx5_core_dev *dev); 917 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 918 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 919 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 920 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 921 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 922 923 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 924 mlx5_buf_alloc(dev, size, direct, buf) 925 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 926 struct mlx5_buf *buf); 927 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 928 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 929 struct mlx5_srq_attr *in); 930 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 931 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 932 struct mlx5_srq_attr *out); 933 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 934 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 935 u16 lwm, int is_srq); 936 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 937 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 938 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 939 struct mlx5_core_mr *mkey, 940 u32 *in, int inlen, 941 u32 *out, int outlen, 942 mlx5_cmd_cbk_t callback, void *context); 943 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 944 struct mlx5_core_mr *mr, 945 u32 *in, int inlen); 946 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 947 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 948 u32 *out, int outlen); 949 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 950 u32 *mkey); 951 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 952 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 953 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 954 u16 opmod, u8 port); 955 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 956 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 957 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 958 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 959 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 960 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 961 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 962 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 963 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 964 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 965 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 966 s32 npages); 967 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 968 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 969 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 970 void mlx5_register_debugfs(void); 971 void mlx5_unregister_debugfs(void); 972 int mlx5_eq_init(struct mlx5_core_dev *dev); 973 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 974 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 975 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 976 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 977 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 978 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 979 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector); 980 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 981 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 982 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 983 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 984 int mlx5_start_eqs(struct mlx5_core_dev *dev); 985 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 986 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 987 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 988 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 989 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 990 u64 addr); 991 992 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 993 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 994 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 995 int size_in, void *data_out, int size_out, 996 u16 reg_num, int arg, int write); 997 998 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 999 1000 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1001 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1002 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1003 u32 *out, int outlen); 1004 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1005 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1006 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1007 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1008 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1009 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1010 int node); 1011 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1012 1013 const char *mlx5_command_str(int command); 1014 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1015 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1016 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1017 int npsvs, u32 *sig_index); 1018 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1019 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1020 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1021 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1022 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1023 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1024 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1025 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1026 struct mlx5_pvlc_reg *pvlc, int write); 1027 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1028 struct mlx5_ptys_reg *ptys, int write); 1029 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1030 struct mlx5_pmtu_reg *pmtu, int write); 1031 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1032 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1033 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1034 int priority, int *is_enable); 1035 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1036 int priority, int enable); 1037 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1038 void *out, int out_size); 1039 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1040 void *in, int in_size); 1041 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1042 void *out, int out_size); 1043 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1044 int in_size); 1045 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1046 u8 num_of_samples, u16 sample_index, 1047 void *out, int out_size); 1048 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1049 int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1050 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1051 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1052 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1053 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1054 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1055 { 1056 return mkey >> 8; 1057 } 1058 1059 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1060 { 1061 return mkey_idx << 8; 1062 } 1063 1064 static inline u8 mlx5_mkey_variant(u32 mkey) 1065 { 1066 return mkey & 0xff; 1067 } 1068 1069 enum { 1070 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1071 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1072 }; 1073 1074 enum { 1075 MAX_MR_CACHE_ENTRIES = 15, 1076 }; 1077 1078 struct mlx5_interface { 1079 void * (*add)(struct mlx5_core_dev *dev); 1080 void (*remove)(struct mlx5_core_dev *dev, void *context); 1081 void (*event)(struct mlx5_core_dev *dev, void *context, 1082 enum mlx5_dev_event event, unsigned long param); 1083 void * (*get_dev)(void *context); 1084 int protocol; 1085 struct list_head list; 1086 }; 1087 1088 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1089 int mlx5_register_interface(struct mlx5_interface *intf); 1090 void mlx5_unregister_interface(struct mlx5_interface *intf); 1091 1092 struct mlx5_profile { 1093 u64 mask; 1094 u8 log_max_qp; 1095 struct { 1096 int size; 1097 int limit; 1098 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1099 }; 1100 1101 enum { 1102 MLX5_PCI_DEV_IS_VF = 1 << 0, 1103 }; 1104 1105 enum { 1106 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1107 }; 1108 1109 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1110 { 1111 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1112 } 1113 #ifdef RATELIMIT 1114 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1115 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1116 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index); 1117 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst); 1118 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst); 1119 1120 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1121 { 1122 return !!(dev->priv.rl_table.max_size); 1123 } 1124 #endif 1125 1126 #endif /* MLX5_DRIVER_H */ 1127