xref: /freebsd/sys/dev/mlx5/driver.h (revision a0b9e2e854027e6ff61fb075a1309dbc71c42b54) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 #include <linux/wait.h>
45 
46 #include <dev/mlx5/device.h>
47 #include <dev/mlx5/doorbell.h>
48 #include <dev/mlx5/srq.h>
49 
50 #define MLX5_QCOUNTER_SETS_NETDEV 64
51 #define MLX5_MAX_NUMBER_OF_VFS 128
52 
53 enum {
54 	MLX5_BOARD_ID_LEN = 64,
55 	MLX5_MAX_NAME_LEN = 16,
56 };
57 
58 enum {
59 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_ATOMIC_MODE_OFF		= 16,
89 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
90 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
91 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
98 };
99 
100 enum {
101 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
102 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
103 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
104 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
111 };
112 
113 enum {
114 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
115 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
116 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
117 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
118 };
119 
120 enum {
121 	MLX5_REG_QPTS		 = 0x4002,
122 	MLX5_REG_QETCR		 = 0x4005,
123 	MLX5_REG_QPDP		 = 0x4007,
124 	MLX5_REG_QTCT		 = 0x400A,
125 	MLX5_REG_QPDPM		 = 0x4013,
126 	MLX5_REG_QHLL		 = 0x4016,
127 	MLX5_REG_QCAM		 = 0x4019,
128 	MLX5_REG_DCBX_PARAM	 = 0x4020,
129 	MLX5_REG_DCBX_APP	 = 0x4021,
130 	MLX5_REG_FPGA_CAP	 = 0x4022,
131 	MLX5_REG_FPGA_CTRL	 = 0x4023,
132 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
133 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_PMLP		 = 0x5002,
136 	MLX5_REG_PMTU		 = 0x5003,
137 	MLX5_REG_PTYS		 = 0x5004,
138 	MLX5_REG_PAOS		 = 0x5006,
139 	MLX5_REG_PFCC		 = 0x5007,
140 	MLX5_REG_PPCNT		 = 0x5008,
141 	MLX5_REG_PUDE		 = 0x5009,
142 	MLX5_REG_PPTB		 = 0x500B,
143 	MLX5_REG_PBMC		 = 0x500C,
144 	MLX5_REG_PELC		 = 0x500E,
145 	MLX5_REG_PVLC		 = 0x500F,
146 	MLX5_REG_PMPE		 = 0x5010,
147 	MLX5_REG_PMAOS		 = 0x5012,
148 	MLX5_REG_PPLM		 = 0x5023,
149 	MLX5_REG_PDDR		 = 0x5031,
150 	MLX5_REG_PBSR		 = 0x5038,
151 	MLX5_REG_PCAM		 = 0x507f,
152 	MLX5_REG_NODE_DESC	 = 0x6001,
153 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
154 	MLX5_REG_MTMP		 = 0x900a,
155 	MLX5_REG_MCIA		 = 0x9014,
156 	MLX5_REG_MFRL		 = 0x9028,
157 	MLX5_REG_MPCNT		 = 0x9051,
158 	MLX5_REG_MCQI		 = 0x9061,
159 	MLX5_REG_MCC		 = 0x9062,
160 	MLX5_REG_MCDA		 = 0x9063,
161 	MLX5_REG_MCAM		 = 0x907f,
162 };
163 
164 enum dbg_rsc_type {
165 	MLX5_DBG_RSC_QP,
166 	MLX5_DBG_RSC_EQ,
167 	MLX5_DBG_RSC_CQ,
168 };
169 
170 enum {
171 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
172 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
173 	MLX5_INTERFACE_NUMBER       = 2,
174 };
175 
176 struct mlx5_field_desc {
177 	struct dentry	       *dent;
178 	int			i;
179 };
180 
181 struct mlx5_rsc_debug {
182 	struct mlx5_core_dev   *dev;
183 	void		       *object;
184 	enum dbg_rsc_type	type;
185 	struct dentry	       *root;
186 	struct mlx5_field_desc	fields[0];
187 };
188 
189 enum mlx5_dev_event {
190 	MLX5_DEV_EVENT_SYS_ERROR,
191 	MLX5_DEV_EVENT_PORT_UP,
192 	MLX5_DEV_EVENT_PORT_DOWN,
193 	MLX5_DEV_EVENT_PORT_INITIALIZED,
194 	MLX5_DEV_EVENT_LID_CHANGE,
195 	MLX5_DEV_EVENT_PKEY_CHANGE,
196 	MLX5_DEV_EVENT_GUID_CHANGE,
197 	MLX5_DEV_EVENT_CLIENT_REREG,
198 	MLX5_DEV_EVENT_VPORT_CHANGE,
199 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
200 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
201 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
202 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
203 };
204 
205 enum mlx5_port_status {
206 	MLX5_PORT_UP        = 1 << 0,
207 	MLX5_PORT_DOWN      = 1 << 1,
208 };
209 
210 enum {
211 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
212 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
213 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
214 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
215 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
216 	MLX5_VSC_DATA_OFFSET	 = 0x14,
217 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
218 };
219 
220 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
221 
222 struct mlx5_uuar_info {
223 	struct mlx5_uar	       *uars;
224 	int			num_uars;
225 	int			num_low_latency_uuars;
226 	unsigned long	       *bitmap;
227 	unsigned int	       *count;
228 	struct mlx5_bf	       *bfs;
229 
230 	/*
231 	 * protect uuar allocation data structs
232 	 */
233 	struct mutex		lock;
234 	u32			ver;
235 };
236 
237 struct mlx5_bf {
238 	void __iomem	       *reg;
239 	void __iomem	       *regreg;
240 	int			buf_size;
241 	struct mlx5_uar	       *uar;
242 	unsigned long		offset;
243 	int			need_lock;
244 	/* protect blue flame buffer selection when needed
245 	 */
246 	spinlock_t		lock;
247 
248 	/* serialize 64 bit writes when done as two 32 bit accesses
249 	 */
250 	spinlock_t		lock32;
251 	int			uuarn;
252 };
253 
254 struct mlx5_cmd_first {
255 	__be32		data[4];
256 };
257 
258 struct cache_ent;
259 struct mlx5_fw_page {
260 	union {
261 		struct rb_node rb_node;
262 		struct list_head list;
263 	};
264 	struct mlx5_cmd_first first;
265 	struct mlx5_core_dev *dev;
266 	bus_dmamap_t dma_map;
267 	bus_addr_t dma_addr;
268 	void *virt_addr;
269 	struct cache_ent *cache;
270 	u32 numpages;
271 	u16 load_done;
272 #define	MLX5_LOAD_ST_NONE 0
273 #define	MLX5_LOAD_ST_SUCCESS 1
274 #define	MLX5_LOAD_ST_FAILURE 2
275 	u16 func_id;
276 };
277 #define	mlx5_cmd_msg mlx5_fw_page
278 
279 struct mlx5_cmd_debug {
280 	struct dentry	       *dbg_root;
281 	struct dentry	       *dbg_in;
282 	struct dentry	       *dbg_out;
283 	struct dentry	       *dbg_outlen;
284 	struct dentry	       *dbg_status;
285 	struct dentry	       *dbg_run;
286 	void		       *in_msg;
287 	void		       *out_msg;
288 	u8			status;
289 	u16			inlen;
290 	u16			outlen;
291 };
292 
293 struct cache_ent {
294 	/* protect block chain allocations
295 	 */
296 	spinlock_t		lock;
297 	struct list_head	head;
298 };
299 
300 struct cmd_msg_cache {
301 	struct cache_ent	large;
302 	struct cache_ent	med;
303 
304 };
305 
306 struct mlx5_traffic_counter {
307 	u64         packets;
308 	u64         octets;
309 };
310 
311 enum mlx5_cmd_mode {
312 	MLX5_CMD_MODE_POLLING,
313 	MLX5_CMD_MODE_EVENTS
314 };
315 
316 struct mlx5_cmd_stats {
317 	u64		sum;
318 	u64		n;
319 	struct dentry  *root;
320 	struct dentry  *avg;
321 	struct dentry  *count;
322 	/* protect command average calculations */
323 	spinlock_t	lock;
324 };
325 
326 struct mlx5_cmd {
327 	struct mlx5_fw_page *cmd_page;
328 	bus_dma_tag_t dma_tag;
329 	struct sx dma_sx;
330 	struct mtx dma_mtx;
331 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
332 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
333 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
334 	struct cv dma_cv;
335 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
336 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
337 	void	       *cmd_buf;
338 	dma_addr_t	dma;
339 	u16		cmdif_rev;
340 	u8		log_sz;
341 	u8		log_stride;
342 	int		max_reg_cmds;
343 	int		events;
344 	u32 __iomem    *vector;
345 
346 	/* protect command queue allocations
347 	 */
348 	spinlock_t	alloc_lock;
349 
350 	/* protect token allocations
351 	 */
352 	spinlock_t	token_lock;
353 	u8		token;
354 	unsigned long	bitmask;
355 	struct semaphore sem;
356 	struct semaphore pages_sem;
357 	enum mlx5_cmd_mode mode;
358 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
359 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
360 	struct mlx5_cmd_debug dbg;
361 	struct cmd_msg_cache cache;
362 	int checksum_disabled;
363 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
364 };
365 
366 struct mlx5_port_caps {
367 	int	gid_table_len;
368 	int	pkey_table_len;
369 	u8	ext_port_cap;
370 };
371 
372 struct mlx5_buf {
373 	bus_dma_tag_t		dma_tag;
374 	bus_dmamap_t		dma_map;
375 	struct mlx5_core_dev   *dev;
376 	struct {
377 		void	       *buf;
378 	} direct;
379 	u64		       *page_list;
380 	int			npages;
381 	int			size;
382 	u8			page_shift;
383 	u8			load_done;
384 };
385 
386 struct mlx5_frag_buf {
387 	struct mlx5_buf_list	*frags;
388 	int			npages;
389 	int			size;
390 	u8			page_shift;
391 };
392 
393 struct mlx5_eq {
394 	struct mlx5_core_dev   *dev;
395 	__be32 __iomem	       *doorbell;
396 	u32			cons_index;
397 	struct mlx5_buf		buf;
398 	int			size;
399 	u8			irqn;
400 	u8			eqn;
401 	int			nent;
402 	u64			mask;
403 	struct list_head	list;
404 	int			index;
405 	struct mlx5_rsc_debug	*dbg;
406 };
407 
408 struct mlx5_core_psv {
409 	u32	psv_idx;
410 	struct psv_layout {
411 		u32	pd;
412 		u16	syndrome;
413 		u16	reserved;
414 		u16	bg;
415 		u16	app_tag;
416 		u32	ref_tag;
417 	} psv;
418 };
419 
420 struct mlx5_core_sig_ctx {
421 	struct mlx5_core_psv	psv_memory;
422 	struct mlx5_core_psv	psv_wire;
423 #if (__FreeBSD_version >= 1100000)
424 	struct ib_sig_err       err_item;
425 #endif
426 	bool			sig_status_checked;
427 	bool			sig_err_exists;
428 	u32			sigerr_count;
429 };
430 
431 enum {
432 	MLX5_MKEY_MR = 1,
433 	MLX5_MKEY_MW,
434 	MLX5_MKEY_MR_USER,
435 };
436 
437 struct mlx5_core_mkey {
438 	u64			iova;
439 	u64			size;
440 	u32			key;
441 	u32			pd;
442 	u32			type;
443 };
444 
445 struct mlx5_core_mr {
446 	u64			iova;
447 	u64			size;
448 	u32			key;
449 	u32			pd;
450 };
451 
452 enum mlx5_res_type {
453 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
454 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
455 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
456 	MLX5_RES_SRQ	= 3,
457 	MLX5_RES_XSRQ	= 4,
458 	MLX5_RES_DCT	= 5,
459 };
460 
461 struct mlx5_core_rsc_common {
462 	enum mlx5_res_type	res;
463 	atomic_t		refcount;
464 	struct completion	free;
465 };
466 
467 struct mlx5_core_srq {
468 	struct mlx5_core_rsc_common	common; /* must be first */
469 	u32				srqn;
470 	int				max;
471 	size_t				max_gs;
472 	size_t				max_avail_gather;
473 	int				wqe_shift;
474 	void				(*event)(struct mlx5_core_srq *, int);
475 	atomic_t			refcount;
476 	struct completion		free;
477 };
478 
479 struct mlx5_eq_table {
480 	void __iomem	       *update_ci;
481 	void __iomem	       *update_arm_ci;
482 	struct list_head	comp_eqs_list;
483 	struct mlx5_eq		pages_eq;
484 	struct mlx5_eq		async_eq;
485 	struct mlx5_eq		cmd_eq;
486 	int			num_comp_vectors;
487 	/* protect EQs list
488 	 */
489 	spinlock_t		lock;
490 };
491 
492 struct mlx5_uar {
493 	u32			index;
494 	void __iomem	       *bf_map;
495 	void __iomem	       *map;
496 };
497 
498 
499 struct mlx5_core_health {
500 	struct mlx5_health_buffer __iomem	*health;
501 	__be32 __iomem		       *health_counter;
502 	struct timer_list		timer;
503 	u32				prev;
504 	int				miss_counter;
505 	u32				fatal_error;
506 	struct workqueue_struct	       *wq_watchdog;
507 	struct work_struct		work_watchdog;
508 	/* wq spinlock to synchronize draining */
509 	spinlock_t			wq_lock;
510 	struct workqueue_struct	       *wq;
511 	unsigned long			flags;
512 	struct work_struct		work;
513 	struct delayed_work		recover_work;
514 	unsigned int			last_reset_req;
515 	struct work_struct		work_cmd_completion;
516 	struct workqueue_struct	       *wq_cmd;
517 };
518 
519 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
520 
521 struct mlx5_cq_linear_array_entry {
522 	struct mlx5_core_cq * volatile cq;
523 };
524 
525 struct mlx5_cq_table {
526 	/* protect radix tree
527 	 */
528 	spinlock_t		writerlock;
529 	atomic_t		writercount;
530 	struct radix_tree_root	tree;
531 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
532 };
533 
534 struct mlx5_qp_table {
535 	/* protect radix tree
536 	 */
537 	spinlock_t		lock;
538 	struct radix_tree_root	tree;
539 };
540 
541 struct mlx5_srq_table {
542 	/* protect radix tree
543 	 */
544 	spinlock_t		lock;
545 	struct radix_tree_root	tree;
546 };
547 
548 struct mlx5_mr_table {
549 	/* protect radix tree
550 	 */
551 	spinlock_t		lock;
552 	struct radix_tree_root	tree;
553 };
554 
555 #ifdef RATELIMIT
556 struct mlx5_rl_entry {
557 	u32			rate;
558 	u16			burst;
559 	u16			index;
560 	u32			refcount;
561 };
562 
563 struct mlx5_rl_table {
564 	struct mutex		rl_lock;
565 	u16			max_size;
566 	u32			max_rate;
567 	u32			min_rate;
568 	struct mlx5_rl_entry   *rl_entry;
569 };
570 #endif
571 
572 struct mlx5_pme_stats {
573 	u64			status_counters[MLX5_MODULE_STATUS_NUM];
574 	u64			error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
575 };
576 
577 struct mlx5_priv {
578 	char			name[MLX5_MAX_NAME_LEN];
579 	struct mlx5_eq_table	eq_table;
580 	struct msix_entry	*msix_arr;
581 	struct mlx5_uuar_info	uuari;
582 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
583 	int			disable_irqs;
584 
585 	struct io_mapping	*bf_mapping;
586 
587 	/* pages stuff */
588 	struct workqueue_struct *pg_wq;
589 	struct rb_root		page_root;
590 	s64			fw_pages;
591 	atomic_t		reg_pages;
592 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
593 	struct mlx5_core_health health;
594 
595 	struct mlx5_srq_table	srq_table;
596 
597 	/* start: qp staff */
598 	struct mlx5_qp_table	qp_table;
599 	struct dentry	       *qp_debugfs;
600 	struct dentry	       *eq_debugfs;
601 	struct dentry	       *cq_debugfs;
602 	struct dentry	       *cmdif_debugfs;
603 	/* end: qp staff */
604 
605 	/* start: cq staff */
606 	struct mlx5_cq_table	cq_table;
607 	/* end: cq staff */
608 
609 	/* start: mr staff */
610 	struct mlx5_mr_table	mr_table;
611 	/* end: mr staff */
612 
613 	/* start: alloc staff */
614 	int			numa_node;
615 
616 	struct mutex   pgdir_mutex;
617 	struct list_head        pgdir_list;
618 	/* end: alloc staff */
619 	struct dentry	       *dbg_root;
620 
621 	/* protect mkey key part */
622 	spinlock_t		mkey_lock;
623 	u8			mkey_key;
624 
625 	struct list_head        dev_list;
626 	struct list_head        ctx_list;
627 	spinlock_t              ctx_lock;
628 	unsigned long		pci_dev_data;
629 #ifdef RATELIMIT
630 	struct mlx5_rl_table	rl_table;
631 #endif
632 	struct mlx5_pme_stats pme_stats;
633 
634 	struct mlx5_eswitch	*eswitch;
635 };
636 
637 enum mlx5_device_state {
638 	MLX5_DEVICE_STATE_UP,
639 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
640 };
641 
642 enum mlx5_interface_state {
643 	MLX5_INTERFACE_STATE_UP = 0x1,
644 	MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
645 };
646 
647 enum mlx5_pci_status {
648 	MLX5_PCI_STATUS_DISABLED,
649 	MLX5_PCI_STATUS_ENABLED,
650 };
651 
652 #define	MLX5_MAX_RESERVED_GIDS	8
653 
654 struct mlx5_rsvd_gids {
655 	unsigned int start;
656 	unsigned int count;
657 	struct ida ida;
658 };
659 
660 struct mlx5_special_contexts {
661 	int resd_lkey;
662 };
663 
664 struct mlx5_flow_root_namespace;
665 struct mlx5_core_dev {
666 	struct pci_dev	       *pdev;
667 	/* sync pci state */
668 	struct mutex		pci_status_mutex;
669 	enum mlx5_pci_status	pci_status;
670 	char			board_id[MLX5_BOARD_ID_LEN];
671 	struct mlx5_cmd		cmd;
672 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
673 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
674 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
675 	struct {
676 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
677 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
678 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
679 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
680 	} caps;
681 	phys_addr_t		iseg_base;
682 	struct mlx5_init_seg __iomem *iseg;
683 	enum mlx5_device_state	state;
684 	/* sync interface state */
685 	struct mutex		intf_state_mutex;
686 	unsigned long		intf_state;
687 	void			(*event) (struct mlx5_core_dev *dev,
688 					  enum mlx5_dev_event event,
689 					  unsigned long param);
690 	struct mlx5_priv	priv;
691 	struct mlx5_profile	*profile;
692 	atomic_t		num_qps;
693 	u32			vsc_addr;
694 	u32			issi;
695 	struct mlx5_special_contexts special_contexts;
696 	unsigned int module_status[MLX5_MAX_PORTS];
697 	struct mlx5_flow_root_namespace *root_ns;
698 	struct mlx5_flow_root_namespace *fdb_root_ns;
699 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
700 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
701 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
702 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
703 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
704 	struct mlx5_crspace_regmap *dump_rege;
705 	uint32_t *dump_data;
706 	unsigned dump_size;
707 	bool dump_valid;
708 	bool dump_copyout;
709 	struct mtx dump_lock;
710 
711 	struct sysctl_ctx_list	sysctl_ctx;
712 	int			msix_eqvec;
713 	int			pwr_status;
714 	int			pwr_value;
715 
716 	struct {
717 		struct mlx5_rsvd_gids	reserved_gids;
718 		atomic_t		roce_en;
719 	} roce;
720 
721 	struct {
722 		spinlock_t	spinlock;
723 #define	MLX5_MPFS_TABLE_MAX 32
724 		long		bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
725 	} mpfs;
726 #ifdef CONFIG_MLX5_FPGA
727 	struct mlx5_fpga_device	*fpga;
728 #endif
729 };
730 
731 enum {
732 	MLX5_WOL_DISABLE       = 0,
733 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
734 	MLX5_WOL_MAGIC         = 1 << 2,
735 	MLX5_WOL_ARP           = 1 << 3,
736 	MLX5_WOL_BROADCAST     = 1 << 4,
737 	MLX5_WOL_MULTICAST     = 1 << 5,
738 	MLX5_WOL_UNICAST       = 1 << 6,
739 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
740 };
741 
742 struct mlx5_db {
743 	__be32			*db;
744 	union {
745 		struct mlx5_db_pgdir		*pgdir;
746 		struct mlx5_ib_user_db_page	*user_page;
747 	}			u;
748 	dma_addr_t		dma;
749 	int			index;
750 };
751 
752 struct mlx5_net_counters {
753 	u64	packets;
754 	u64	octets;
755 };
756 
757 struct mlx5_ptys_reg {
758 	u8	an_dis_admin;
759 	u8	an_dis_ap;
760 	u8	local_port;
761 	u8	proto_mask;
762 	u32	eth_proto_cap;
763 	u16	ib_link_width_cap;
764 	u16	ib_proto_cap;
765 	u32	eth_proto_admin;
766 	u16	ib_link_width_admin;
767 	u16	ib_proto_admin;
768 	u32	eth_proto_oper;
769 	u16	ib_link_width_oper;
770 	u16	ib_proto_oper;
771 	u32	eth_proto_lp_advertise;
772 };
773 
774 struct mlx5_pvlc_reg {
775 	u8	local_port;
776 	u8	vl_hw_cap;
777 	u8	vl_admin;
778 	u8	vl_operational;
779 };
780 
781 struct mlx5_pmtu_reg {
782 	u8	local_port;
783 	u16	max_mtu;
784 	u16	admin_mtu;
785 	u16	oper_mtu;
786 };
787 
788 struct mlx5_vport_counters {
789 	struct mlx5_net_counters	received_errors;
790 	struct mlx5_net_counters	transmit_errors;
791 	struct mlx5_net_counters	received_ib_unicast;
792 	struct mlx5_net_counters	transmitted_ib_unicast;
793 	struct mlx5_net_counters	received_ib_multicast;
794 	struct mlx5_net_counters	transmitted_ib_multicast;
795 	struct mlx5_net_counters	received_eth_broadcast;
796 	struct mlx5_net_counters	transmitted_eth_broadcast;
797 	struct mlx5_net_counters	received_eth_unicast;
798 	struct mlx5_net_counters	transmitted_eth_unicast;
799 	struct mlx5_net_counters	received_eth_multicast;
800 	struct mlx5_net_counters	transmitted_eth_multicast;
801 };
802 
803 enum {
804 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
805 };
806 
807 struct mlx5_core_dct {
808 	struct mlx5_core_rsc_common	common; /* must be first */
809 	void (*event)(struct mlx5_core_dct *, int);
810 	int			dctn;
811 	struct completion	drained;
812 	struct mlx5_rsc_debug	*dbg;
813 	int			pid;
814 };
815 
816 enum {
817 	MLX5_COMP_EQ_SIZE = 1024,
818 };
819 
820 enum {
821 	MLX5_PTYS_IB = 1 << 0,
822 	MLX5_PTYS_EN = 1 << 2,
823 };
824 
825 struct mlx5_db_pgdir {
826 	struct list_head	list;
827 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
828 	struct mlx5_fw_page    *fw_page;
829 	__be32		       *db_page;
830 	dma_addr_t		db_dma;
831 };
832 
833 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
834 
835 struct mlx5_cmd_work_ent {
836 	struct mlx5_cmd_msg    *in;
837 	struct mlx5_cmd_msg    *out;
838 	int			uin_size;
839 	void		       *uout;
840 	int			uout_size;
841 	mlx5_cmd_cbk_t		callback;
842         struct delayed_work     cb_timeout_work;
843 	void		       *context;
844 	int			idx;
845 	struct completion	done;
846 	struct mlx5_cmd        *cmd;
847 	struct work_struct	work;
848 	struct mlx5_cmd_layout *lay;
849 	int			ret;
850 	int			page_queue;
851 	u8			status;
852 	u8			token;
853 	u64			ts1;
854 	u64			ts2;
855 	u16			op;
856 	u8			busy;
857 	bool			polling;
858 };
859 
860 struct mlx5_pas {
861 	u64	pa;
862 	u8	log_sz;
863 };
864 
865 enum port_state_policy {
866 	MLX5_POLICY_DOWN        = 0,
867 	MLX5_POLICY_UP          = 1,
868 	MLX5_POLICY_FOLLOW      = 2,
869 	MLX5_POLICY_INVALID     = 0xffffffff
870 };
871 
872 static inline void *
873 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
874 {
875 	return ((char *)buf->direct.buf + offset);
876 }
877 
878 
879 extern struct workqueue_struct *mlx5_core_wq;
880 
881 #define STRUCT_FIELD(header, field) \
882 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
883 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
884 
885 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
886 {
887 	return pci_get_drvdata(pdev);
888 }
889 
890 extern struct dentry *mlx5_debugfs_root;
891 
892 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
893 {
894 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
895 }
896 
897 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
898 {
899 	return ioread32be(&dev->iseg->fw_rev) >> 16;
900 }
901 
902 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
903 {
904 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
905 }
906 
907 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
908 {
909 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
910 }
911 
912 static inline int mlx5_get_gid_table_len(u16 param)
913 {
914 	if (param > 4) {
915 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
916 		return 0;
917 	}
918 
919 	return 8 * (1 << param);
920 }
921 
922 static inline void *mlx5_vzalloc(unsigned long size)
923 {
924 	void *rtn;
925 
926 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
927 	return rtn;
928 }
929 
930 static inline void *mlx5_vmalloc(unsigned long size)
931 {
932 	void *rtn;
933 
934 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
935 	if (!rtn)
936 		rtn = vmalloc(size);
937 	return rtn;
938 }
939 
940 static inline u32 mlx5_base_mkey(const u32 key)
941 {
942 	return key & 0xffffff00u;
943 }
944 
945 int mlx5_cmd_init(struct mlx5_core_dev *dev);
946 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
947 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
948 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
949 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
950 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
951 
952 struct mlx5_async_ctx {
953 	struct mlx5_core_dev *dev;
954 	atomic_t num_inflight;
955 	struct wait_queue_head wait;
956 };
957 
958 struct mlx5_async_work;
959 
960 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
961 
962 struct mlx5_async_work {
963 	struct mlx5_async_ctx *ctx;
964 	mlx5_async_cbk_t user_callback;
965 };
966 
967 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
968 			     struct mlx5_async_ctx *ctx);
969 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
970 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
971 		     void *out, int out_size, mlx5_async_cbk_t callback,
972 		     struct mlx5_async_work *work);
973 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
974 		  int out_size);
975 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
976 			  void *out, int out_size);
977 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
978 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
979 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
980 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
981 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
982 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
983 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
984 int mlx5_health_init(struct mlx5_core_dev *dev);
985 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
986 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
987 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
988 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
989 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
990 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
991 
992 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
993 	mlx5_buf_alloc(dev, size, direct, buf)
994 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
995 		   struct mlx5_buf *buf);
996 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
997 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
998 			 struct mlx5_srq_attr *in);
999 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1000 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1001 			struct mlx5_srq_attr *out);
1002 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1003 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1004 		      u16 lwm, int is_srq);
1005 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
1006 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
1007 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1008 			     struct mlx5_core_mr *mkey,
1009 			     struct mlx5_async_ctx *async_ctx, u32 *in,
1010 			     int inlen, u32 *out, int outlen,
1011 			     mlx5_async_cbk_t callback,
1012 			     struct mlx5_async_work *context);
1013 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1014 			  struct mlx5_core_mr *mr,
1015 			  u32 *in, int inlen);
1016 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
1017 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
1018 			 u32 *out, int outlen);
1019 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
1020 			     u32 *mkey);
1021 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1022 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1023 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1024 		      u16 opmod, u8 port);
1025 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1026 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1027 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1028 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1029 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1030 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1031 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1032 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1033 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1034 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1035 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1036 				 s32 npages);
1037 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1038 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1039 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1040 void mlx5_register_debugfs(void);
1041 void mlx5_unregister_debugfs(void);
1042 int mlx5_eq_init(struct mlx5_core_dev *dev);
1043 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1044 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1045 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
1046 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1047 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1048 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1049 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1050 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1051 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1052 		       int nent, u64 mask, struct mlx5_uar *uar);
1053 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1054 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1055 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1056 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1057 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1058 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1059 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1060 				u64 addr);
1061 
1062 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1063 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1064 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1065 			 int size_in, void *data_out, int size_out,
1066 			 u16 reg_num, int arg, int write);
1067 
1068 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1069 
1070 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1071 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1072 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1073 		       u32 *out, int outlen);
1074 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1075 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1076 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1077 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1078 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1079 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1080 		       int node);
1081 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1082 
1083 const char *mlx5_command_str(int command);
1084 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1085 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1086 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1087 			 int npsvs, u32 *sig_index);
1088 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1089 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1090 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1091 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1092 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1093 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1094 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1095 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1096 			  struct mlx5_pvlc_reg *pvlc, int write);
1097 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1098 			  struct mlx5_ptys_reg *ptys, int write);
1099 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1100 			  struct mlx5_pmtu_reg *pmtu, int write);
1101 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1102 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1103 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1104 				int priority, int *is_enable);
1105 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1106 				 int priority, int enable);
1107 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1108 				void *out, int out_size);
1109 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1110 				 void *in, int in_size);
1111 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1112 				    void *out, int out_size);
1113 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1114 			       int in_size);
1115 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1116 				   u8 num_of_samples, u16 sample_index,
1117 				   void *out, int out_size);
1118 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1119 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1120 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1121 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1122 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1123 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1124 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1125 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1126 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1127 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1128 			       u16 *p_power, u8 *p_status);
1129 
1130 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1131 {
1132 	return mkey >> 8;
1133 }
1134 
1135 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1136 {
1137 	return mkey_idx << 8;
1138 }
1139 
1140 static inline u8 mlx5_mkey_variant(u32 mkey)
1141 {
1142 	return mkey & 0xff;
1143 }
1144 
1145 enum {
1146 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1147 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1148 };
1149 
1150 enum {
1151 	MAX_MR_CACHE_ENTRIES    = 15,
1152 };
1153 
1154 struct mlx5_interface {
1155 	void *			(*add)(struct mlx5_core_dev *dev);
1156 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1157 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1158 					 enum mlx5_dev_event event, unsigned long param);
1159 	void *                  (*get_dev)(void *context);
1160 	int			protocol;
1161 	struct list_head	list;
1162 };
1163 
1164 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1165 int mlx5_register_interface(struct mlx5_interface *intf);
1166 void mlx5_unregister_interface(struct mlx5_interface *intf);
1167 
1168 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1169 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1170     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1171     const u8 *mac, bool vlan, u16 vlan_id);
1172 
1173 struct mlx5_profile {
1174 	u64	mask;
1175 	u8	log_max_qp;
1176 	struct {
1177 		int	size;
1178 		int	limit;
1179 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1180 };
1181 
1182 enum {
1183 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1184 };
1185 
1186 enum {
1187 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1188 };
1189 
1190 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1191 {
1192 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1193 }
1194 #ifdef RATELIMIT
1195 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1196 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1197 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1198 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1199 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1200 
1201 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1202 {
1203 	return !!(dev->priv.rl_table.max_size);
1204 }
1205 #endif
1206 
1207 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1208 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1209 
1210 #endif /* MLX5_DRIVER_H */
1211