1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include <linux/kernel.h> 32 #include <linux/completion.h> 33 #include <linux/pci.h> 34 #include <linux/cache.h> 35 #include <linux/rbtree.h> 36 #include <linux/if_ether.h> 37 #include <linux/semaphore.h> 38 #include <linux/slab.h> 39 #include <linux/vmalloc.h> 40 #include <linux/radix-tree.h> 41 42 #include <dev/mlx5/device.h> 43 #include <dev/mlx5/doorbell.h> 44 45 enum { 46 MLX5_BOARD_ID_LEN = 64, 47 MLX5_MAX_NAME_LEN = 16, 48 }; 49 50 enum { 51 /* one minute for the sake of bringup. Generally, commands must always 52 * complete and we may need to increase this timeout value 53 */ 54 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, 55 MLX5_CMD_WQ_MAX_NAME = 32, 56 }; 57 58 enum { 59 CMD_OWNER_SW = 0x0, 60 CMD_OWNER_HW = 0x1, 61 CMD_STATUS_SUCCESS = 0, 62 }; 63 64 enum mlx5_sqp_t { 65 MLX5_SQP_SMI = 0, 66 MLX5_SQP_GSI = 1, 67 MLX5_SQP_IEEE_1588 = 2, 68 MLX5_SQP_SNIFFER = 3, 69 MLX5_SQP_SYNC_UMR = 4, 70 }; 71 72 enum { 73 MLX5_MAX_PORTS = 2, 74 }; 75 76 enum { 77 MLX5_EQ_VEC_PAGES = 0, 78 MLX5_EQ_VEC_CMD = 1, 79 MLX5_EQ_VEC_ASYNC = 2, 80 MLX5_EQ_VEC_COMP_BASE, 81 }; 82 83 enum { 84 MLX5_MAX_IRQ_NAME = 32 85 }; 86 87 enum { 88 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 89 MLX5_ATOMIC_MODE_CX = 2 << 16, 90 MLX5_ATOMIC_MODE_8B = 3 << 16, 91 MLX5_ATOMIC_MODE_16B = 4 << 16, 92 MLX5_ATOMIC_MODE_32B = 5 << 16, 93 MLX5_ATOMIC_MODE_64B = 6 << 16, 94 MLX5_ATOMIC_MODE_128B = 7 << 16, 95 MLX5_ATOMIC_MODE_256B = 8 << 16, 96 }; 97 98 enum { 99 MLX5_REG_QETCR = 0x4005, 100 MLX5_REG_QPDP = 0x4007, 101 MLX5_REG_QTCT = 0x400A, 102 MLX5_REG_PCAP = 0x5001, 103 MLX5_REG_PMTU = 0x5003, 104 MLX5_REG_PTYS = 0x5004, 105 MLX5_REG_PAOS = 0x5006, 106 MLX5_REG_PFCC = 0x5007, 107 MLX5_REG_PPCNT = 0x5008, 108 MLX5_REG_PMAOS = 0x5012, 109 MLX5_REG_PUDE = 0x5009, 110 MLX5_REG_PPTB = 0x500B, 111 MLX5_REG_PBMC = 0x500C, 112 MLX5_REG_PMPE = 0x5010, 113 MLX5_REG_PELC = 0x500e, 114 MLX5_REG_PVLC = 0x500f, 115 MLX5_REG_PMLP = 0x5002, 116 MLX5_REG_NODE_DESC = 0x6001, 117 MLX5_REG_HOST_ENDIANNESS = 0x7004, 118 MLX5_REG_MCIA = 0x9014, 119 }; 120 121 enum dbg_rsc_type { 122 MLX5_DBG_RSC_QP, 123 MLX5_DBG_RSC_EQ, 124 MLX5_DBG_RSC_CQ, 125 }; 126 127 struct mlx5_field_desc { 128 struct dentry *dent; 129 int i; 130 }; 131 132 struct mlx5_rsc_debug { 133 struct mlx5_core_dev *dev; 134 void *object; 135 enum dbg_rsc_type type; 136 struct dentry *root; 137 struct mlx5_field_desc fields[0]; 138 }; 139 140 enum mlx5_dev_event { 141 MLX5_DEV_EVENT_SYS_ERROR, 142 MLX5_DEV_EVENT_PORT_UP, 143 MLX5_DEV_EVENT_PORT_DOWN, 144 MLX5_DEV_EVENT_PORT_INITIALIZED, 145 MLX5_DEV_EVENT_LID_CHANGE, 146 MLX5_DEV_EVENT_PKEY_CHANGE, 147 MLX5_DEV_EVENT_GUID_CHANGE, 148 MLX5_DEV_EVENT_CLIENT_REREG, 149 MLX5_DEV_EVENT_VPORT_CHANGE, 150 }; 151 152 enum mlx5_port_status { 153 MLX5_PORT_UP = 1 << 0, 154 MLX5_PORT_DOWN = 1 << 1, 155 }; 156 157 enum mlx5_link_mode { 158 MLX5_1000BASE_CX_SGMII = 0, 159 MLX5_1000BASE_KX = 1, 160 MLX5_10GBASE_CX4 = 2, 161 MLX5_10GBASE_KX4 = 3, 162 MLX5_10GBASE_KR = 4, 163 MLX5_20GBASE_KR2 = 5, 164 MLX5_40GBASE_CR4 = 6, 165 MLX5_40GBASE_KR4 = 7, 166 MLX5_56GBASE_R4 = 8, 167 MLX5_10GBASE_CR = 12, 168 MLX5_10GBASE_SR = 13, 169 MLX5_10GBASE_ER = 14, 170 MLX5_40GBASE_SR4 = 15, 171 MLX5_40GBASE_LR4 = 16, 172 MLX5_100GBASE_CR4 = 20, 173 MLX5_100GBASE_SR4 = 21, 174 MLX5_100GBASE_KR4 = 22, 175 MLX5_100GBASE_LR4 = 23, 176 MLX5_100BASE_TX = 24, 177 MLX5_1000BASE_T = 25, 178 MLX5_10GBASE_T = 26, 179 MLX5_25GBASE_CR = 27, 180 MLX5_25GBASE_KR = 28, 181 MLX5_25GBASE_SR = 29, 182 MLX5_50GBASE_CR2 = 30, 183 MLX5_50GBASE_KR2 = 31, 184 MLX5_LINK_MODES_NUMBER, 185 }; 186 187 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 188 189 struct mlx5_uuar_info { 190 struct mlx5_uar *uars; 191 int num_uars; 192 int num_low_latency_uuars; 193 unsigned long *bitmap; 194 unsigned int *count; 195 struct mlx5_bf *bfs; 196 197 /* 198 * protect uuar allocation data structs 199 */ 200 struct mutex lock; 201 u32 ver; 202 }; 203 204 struct mlx5_bf { 205 void __iomem *reg; 206 void __iomem *regreg; 207 int buf_size; 208 struct mlx5_uar *uar; 209 unsigned long offset; 210 int need_lock; 211 /* protect blue flame buffer selection when needed 212 */ 213 spinlock_t lock; 214 215 /* serialize 64 bit writes when done as two 32 bit accesses 216 */ 217 spinlock_t lock32; 218 int uuarn; 219 }; 220 221 struct mlx5_cmd_first { 222 __be32 data[4]; 223 }; 224 225 struct mlx5_cmd_msg { 226 struct list_head list; 227 struct cache_ent *cache; 228 u32 len; 229 struct mlx5_cmd_first first; 230 struct mlx5_cmd_mailbox *next; 231 }; 232 233 struct mlx5_cmd_debug { 234 struct dentry *dbg_root; 235 struct dentry *dbg_in; 236 struct dentry *dbg_out; 237 struct dentry *dbg_outlen; 238 struct dentry *dbg_status; 239 struct dentry *dbg_run; 240 void *in_msg; 241 void *out_msg; 242 u8 status; 243 u16 inlen; 244 u16 outlen; 245 }; 246 247 struct cache_ent { 248 /* protect block chain allocations 249 */ 250 spinlock_t lock; 251 struct list_head head; 252 }; 253 254 struct cmd_msg_cache { 255 struct cache_ent large; 256 struct cache_ent med; 257 258 }; 259 260 struct mlx5_cmd_stats { 261 u64 sum; 262 u64 n; 263 struct dentry *root; 264 struct dentry *avg; 265 struct dentry *count; 266 /* protect command average calculations */ 267 spinlock_t lock; 268 }; 269 270 struct mlx5_cmd { 271 void *cmd_alloc_buf; 272 dma_addr_t alloc_dma; 273 int alloc_size; 274 void *cmd_buf; 275 dma_addr_t dma; 276 u16 cmdif_rev; 277 u8 log_sz; 278 u8 log_stride; 279 int max_reg_cmds; 280 int events; 281 u32 __iomem *vector; 282 283 /* protect command queue allocations 284 */ 285 spinlock_t alloc_lock; 286 287 /* protect token allocations 288 */ 289 spinlock_t token_lock; 290 u8 token; 291 unsigned long bitmask; 292 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 293 struct workqueue_struct *wq; 294 struct semaphore sem; 295 struct semaphore pages_sem; 296 int mode; 297 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 298 struct pci_pool *pool; 299 struct mlx5_cmd_debug dbg; 300 struct cmd_msg_cache cache; 301 int checksum_disabled; 302 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 303 int moving_to_polling; 304 }; 305 306 struct mlx5_port_caps { 307 int gid_table_len; 308 int pkey_table_len; 309 u8 ext_port_cap; 310 }; 311 312 struct mlx5_cmd_mailbox { 313 void *buf; 314 dma_addr_t dma; 315 struct mlx5_cmd_mailbox *next; 316 }; 317 318 struct mlx5_buf_list { 319 void *buf; 320 dma_addr_t map; 321 }; 322 323 struct mlx5_buf { 324 struct mlx5_buf_list direct; 325 struct mlx5_buf_list *page_list; 326 int nbufs; 327 int npages; 328 int size; 329 u8 page_shift; 330 }; 331 332 struct mlx5_eq { 333 struct mlx5_core_dev *dev; 334 __be32 __iomem *doorbell; 335 u32 cons_index; 336 struct mlx5_buf buf; 337 int size; 338 u8 irqn; 339 u8 eqn; 340 int nent; 341 u64 mask; 342 struct list_head list; 343 int index; 344 struct mlx5_rsc_debug *dbg; 345 }; 346 347 struct mlx5_core_psv { 348 u32 psv_idx; 349 struct psv_layout { 350 u32 pd; 351 u16 syndrome; 352 u16 reserved; 353 u16 bg; 354 u16 app_tag; 355 u32 ref_tag; 356 } psv; 357 }; 358 359 struct mlx5_core_sig_ctx { 360 struct mlx5_core_psv psv_memory; 361 struct mlx5_core_psv psv_wire; 362 #if (__FreeBSD_version >= 1100000) 363 struct ib_sig_err err_item; 364 #endif 365 bool sig_status_checked; 366 bool sig_err_exists; 367 u32 sigerr_count; 368 }; 369 370 struct mlx5_core_mr { 371 u64 iova; 372 u64 size; 373 u32 key; 374 u32 pd; 375 }; 376 377 enum mlx5_res_type { 378 MLX5_RES_QP, 379 MLX5_RES_SRQ, 380 MLX5_RES_XSRQ, 381 }; 382 383 struct mlx5_core_rsc_common { 384 enum mlx5_res_type res; 385 atomic_t refcount; 386 struct completion free; 387 }; 388 389 struct mlx5_core_srq { 390 struct mlx5_core_rsc_common common; /* must be first */ 391 u32 srqn; 392 int max; 393 int max_gs; 394 int max_avail_gather; 395 int wqe_shift; 396 void (*event)(struct mlx5_core_srq *, int); 397 atomic_t refcount; 398 struct completion free; 399 }; 400 401 struct mlx5_eq_table { 402 void __iomem *update_ci; 403 void __iomem *update_arm_ci; 404 struct list_head comp_eqs_list; 405 struct mlx5_eq pages_eq; 406 struct mlx5_eq async_eq; 407 struct mlx5_eq cmd_eq; 408 int num_comp_vectors; 409 /* protect EQs list 410 */ 411 spinlock_t lock; 412 }; 413 414 struct mlx5_uar { 415 u32 index; 416 struct list_head bf_list; 417 unsigned free_bf_bmap; 418 void __iomem *bf_map; 419 void __iomem *map; 420 }; 421 422 423 struct mlx5_core_health { 424 struct mlx5_health_buffer __iomem *health; 425 __be32 __iomem *health_counter; 426 struct timer_list timer; 427 struct list_head list; 428 u32 prev; 429 int miss_counter; 430 }; 431 432 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 433 434 struct mlx5_cq_linear_array_entry { 435 spinlock_t lock; 436 struct mlx5_core_cq * volatile cq; 437 }; 438 439 struct mlx5_cq_table { 440 /* protect radix tree 441 */ 442 spinlock_t lock; 443 struct radix_tree_root tree; 444 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 445 }; 446 447 struct mlx5_qp_table { 448 /* protect radix tree 449 */ 450 spinlock_t lock; 451 struct radix_tree_root tree; 452 }; 453 454 struct mlx5_srq_table { 455 /* protect radix tree 456 */ 457 spinlock_t lock; 458 struct radix_tree_root tree; 459 }; 460 461 struct mlx5_mr_table { 462 /* protect radix tree 463 */ 464 rwlock_t lock; 465 struct radix_tree_root tree; 466 }; 467 468 struct mlx5_irq_info { 469 char name[MLX5_MAX_IRQ_NAME]; 470 }; 471 472 struct mlx5_priv { 473 char name[MLX5_MAX_NAME_LEN]; 474 struct mlx5_eq_table eq_table; 475 struct msix_entry *msix_arr; 476 struct mlx5_irq_info *irq_info; 477 struct mlx5_uuar_info uuari; 478 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 479 480 struct io_mapping *bf_mapping; 481 482 /* pages stuff */ 483 struct workqueue_struct *pg_wq; 484 struct rb_root page_root; 485 int fw_pages; 486 int reg_pages; 487 struct list_head free_list; 488 489 struct mlx5_core_health health; 490 491 struct mlx5_srq_table srq_table; 492 493 /* start: qp staff */ 494 struct mlx5_qp_table qp_table; 495 struct dentry *qp_debugfs; 496 struct dentry *eq_debugfs; 497 struct dentry *cq_debugfs; 498 struct dentry *cmdif_debugfs; 499 /* end: qp staff */ 500 501 /* start: cq staff */ 502 struct mlx5_cq_table cq_table; 503 /* end: cq staff */ 504 505 /* start: mr staff */ 506 struct mlx5_mr_table mr_table; 507 /* end: mr staff */ 508 509 /* start: alloc staff */ 510 int numa_node; 511 512 struct mutex pgdir_mutex; 513 struct list_head pgdir_list; 514 /* end: alloc staff */ 515 struct dentry *dbg_root; 516 517 /* protect mkey key part */ 518 spinlock_t mkey_lock; 519 u8 mkey_key; 520 521 struct list_head dev_list; 522 struct list_head ctx_list; 523 spinlock_t ctx_lock; 524 }; 525 526 struct mlx5_special_contexts { 527 int resd_lkey; 528 }; 529 530 struct mlx5_core_dev { 531 struct pci_dev *pdev; 532 char board_id[MLX5_BOARD_ID_LEN]; 533 struct mlx5_cmd cmd; 534 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 535 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 536 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 537 struct mlx5_init_seg __iomem *iseg; 538 void (*event) (struct mlx5_core_dev *dev, 539 enum mlx5_dev_event event, 540 unsigned long param); 541 struct mlx5_priv priv; 542 struct mlx5_profile *profile; 543 atomic_t num_qps; 544 u32 issi; 545 struct mlx5_special_contexts special_contexts; 546 unsigned int module_status[MLX5_MAX_PORTS]; 547 }; 548 549 enum { 550 MLX5_WOL_DISABLE = 0, 551 MLX5_WOL_SECURED_MAGIC = 1 << 1, 552 MLX5_WOL_MAGIC = 1 << 2, 553 MLX5_WOL_ARP = 1 << 3, 554 MLX5_WOL_BROADCAST = 1 << 4, 555 MLX5_WOL_MULTICAST = 1 << 5, 556 MLX5_WOL_UNICAST = 1 << 6, 557 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 558 }; 559 560 struct mlx5_db { 561 __be32 *db; 562 union { 563 struct mlx5_db_pgdir *pgdir; 564 struct mlx5_ib_user_db_page *user_page; 565 } u; 566 dma_addr_t dma; 567 int index; 568 }; 569 570 struct mlx5_net_counters { 571 u64 packets; 572 u64 octets; 573 }; 574 575 struct mlx5_ptys_reg { 576 u8 local_port; 577 u8 proto_mask; 578 u32 eth_proto_cap; 579 u16 ib_link_width_cap; 580 u16 ib_proto_cap; 581 u32 eth_proto_admin; 582 u16 ib_link_width_admin; 583 u16 ib_proto_admin; 584 u32 eth_proto_oper; 585 u16 ib_link_width_oper; 586 u16 ib_proto_oper; 587 u32 eth_proto_lp_advertise; 588 }; 589 590 struct mlx5_pvlc_reg { 591 u8 local_port; 592 u8 vl_hw_cap; 593 u8 vl_admin; 594 u8 vl_operational; 595 }; 596 597 struct mlx5_pmtu_reg { 598 u8 local_port; 599 u16 max_mtu; 600 u16 admin_mtu; 601 u16 oper_mtu; 602 }; 603 604 struct mlx5_vport_counters { 605 struct mlx5_net_counters received_errors; 606 struct mlx5_net_counters transmit_errors; 607 struct mlx5_net_counters received_ib_unicast; 608 struct mlx5_net_counters transmitted_ib_unicast; 609 struct mlx5_net_counters received_ib_multicast; 610 struct mlx5_net_counters transmitted_ib_multicast; 611 struct mlx5_net_counters received_eth_broadcast; 612 struct mlx5_net_counters transmitted_eth_broadcast; 613 struct mlx5_net_counters received_eth_unicast; 614 struct mlx5_net_counters transmitted_eth_unicast; 615 struct mlx5_net_counters received_eth_multicast; 616 struct mlx5_net_counters transmitted_eth_multicast; 617 }; 618 619 enum { 620 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 621 }; 622 623 enum { 624 MLX5_COMP_EQ_SIZE = 1024, 625 }; 626 627 enum { 628 MLX5_PTYS_IB = 1 << 0, 629 MLX5_PTYS_EN = 1 << 2, 630 }; 631 632 struct mlx5_db_pgdir { 633 struct list_head list; 634 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 635 __be32 *db_page; 636 dma_addr_t db_dma; 637 }; 638 639 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 640 641 struct mlx5_cmd_work_ent { 642 struct mlx5_cmd_msg *in; 643 struct mlx5_cmd_msg *out; 644 void *uout; 645 int uout_size; 646 mlx5_cmd_cbk_t callback; 647 void *context; 648 int idx; 649 struct completion done; 650 struct mlx5_cmd *cmd; 651 struct work_struct work; 652 struct mlx5_cmd_layout *lay; 653 int ret; 654 int page_queue; 655 u8 status; 656 u8 token; 657 u64 ts1; 658 u64 ts2; 659 u16 op; 660 }; 661 662 struct mlx5_pas { 663 u64 pa; 664 u8 log_sz; 665 }; 666 667 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 668 { 669 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1)) 670 return buf->direct.buf + offset; 671 else 672 return buf->page_list[offset >> PAGE_SHIFT].buf + 673 (offset & (PAGE_SIZE - 1)); 674 } 675 676 677 extern struct workqueue_struct *mlx5_core_wq; 678 679 #define STRUCT_FIELD(header, field) \ 680 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 681 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 682 683 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 684 { 685 return pci_get_drvdata(pdev); 686 } 687 688 extern struct dentry *mlx5_debugfs_root; 689 690 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 691 { 692 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 693 } 694 695 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 696 { 697 return ioread32be(&dev->iseg->fw_rev) >> 16; 698 } 699 700 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 701 { 702 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 703 } 704 705 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 706 { 707 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 708 } 709 710 static inline int mlx5_get_gid_table_len(u16 param) 711 { 712 if (param > 4) { 713 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 714 return 0; 715 } 716 717 return 8 * (1 << param); 718 } 719 720 static inline void *mlx5_vzalloc(unsigned long size) 721 { 722 void *rtn; 723 724 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 725 return rtn; 726 } 727 728 static inline u32 mlx5_base_mkey(const u32 key) 729 { 730 return key & 0xffffff00u; 731 } 732 733 int mlx5_cmd_init(struct mlx5_core_dev *dev); 734 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 735 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 736 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 737 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 738 int mlx5_cmd_status_to_err_v2(void *ptr); 739 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 740 enum mlx5_cap_mode cap_mode); 741 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 742 int out_size); 743 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 744 void *out, int out_size, mlx5_cmd_cbk_t callback, 745 void *context); 746 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 747 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 748 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 749 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 750 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 751 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 752 void mlx5_health_cleanup(void); 753 void __init mlx5_health_init(void); 754 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 755 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 756 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, int max_direct, 757 struct mlx5_buf *buf, int node); 758 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 759 struct mlx5_buf *buf); 760 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 761 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 762 struct mlx5_create_srq_mbox_in *in, int inlen, 763 int is_xrc); 764 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 765 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 766 struct mlx5_query_srq_mbox_out *out); 767 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 768 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 769 u16 lwm, int is_srq); 770 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 771 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 772 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 773 struct mlx5_create_mkey_mbox_in *in, int inlen, 774 mlx5_cmd_cbk_t callback, void *context, 775 struct mlx5_create_mkey_mbox_out *out); 776 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 777 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 778 struct mlx5_query_mkey_mbox_out *out, int outlen); 779 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 780 u32 *mkey); 781 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 782 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 783 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, 784 u16 opmod, u8 port); 785 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 786 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 787 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 788 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 789 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 790 s32 npages); 791 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 792 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 793 void mlx5_register_debugfs(void); 794 void mlx5_unregister_debugfs(void); 795 int mlx5_eq_init(struct mlx5_core_dev *dev); 796 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 797 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 798 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 799 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 800 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 801 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 802 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); 803 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 804 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 805 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 806 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 807 int mlx5_start_eqs(struct mlx5_core_dev *dev); 808 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 809 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 810 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 811 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 812 813 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 814 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 815 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 816 int size_in, void *data_out, int size_out, 817 u16 reg_num, int arg, int write); 818 819 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 820 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 821 int ptys_size, int proto_mask); 822 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 823 u32 *proto_cap, int proto_mask); 824 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 825 u32 *proto_admin, int proto_mask); 826 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 827 int proto_mask); 828 int mlx5_set_port_status(struct mlx5_core_dev *dev, 829 enum mlx5_port_status status); 830 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 831 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port, 832 u32 rx_pause, u32 tx_pause); 833 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 834 u32 *rx_pause, u32 *tx_pause); 835 836 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 837 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 838 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 839 840 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 841 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 842 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 843 int device_addr, int size, int module_num, u32 *data, 844 int *size_read); 845 846 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 847 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 848 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 849 struct mlx5_query_eq_mbox_out *out, int outlen); 850 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 851 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 852 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 853 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 854 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 855 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 856 int node); 857 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 858 859 const char *mlx5_command_str(int command); 860 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 861 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 862 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 863 int npsvs, u32 *sig_index); 864 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 865 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 866 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 867 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 868 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 869 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 870 struct mlx5_pvlc_reg *pvlc, int write); 871 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 872 struct mlx5_ptys_reg *ptys, int write); 873 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 874 struct mlx5_pmtu_reg *pmtu, int write); 875 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 876 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 877 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 878 int priority, int *is_enable); 879 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 880 int priority, int enable); 881 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 882 void *out, int out_size); 883 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 884 void *in, int in_size); 885 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 886 void *out, int out_size); 887 static inline u32 mlx5_mkey_to_idx(u32 mkey) 888 { 889 return mkey >> 8; 890 } 891 892 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 893 { 894 return mkey_idx << 8; 895 } 896 897 static inline u8 mlx5_mkey_variant(u32 mkey) 898 { 899 return mkey & 0xff; 900 } 901 902 enum { 903 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 904 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 905 }; 906 907 enum { 908 MAX_MR_CACHE_ENTRIES = 16, 909 }; 910 911 enum { 912 MLX5_INTERFACE_PROTOCOL_IB = 0, 913 MLX5_INTERFACE_PROTOCOL_ETH = 1, 914 }; 915 916 struct mlx5_interface { 917 void * (*add)(struct mlx5_core_dev *dev); 918 void (*remove)(struct mlx5_core_dev *dev, void *context); 919 void (*event)(struct mlx5_core_dev *dev, void *context, 920 enum mlx5_dev_event event, unsigned long param); 921 void * (*get_dev)(void *context); 922 int protocol; 923 struct list_head list; 924 }; 925 926 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 927 int mlx5_register_interface(struct mlx5_interface *intf); 928 void mlx5_unregister_interface(struct mlx5_interface *intf); 929 930 struct mlx5_profile { 931 u64 mask; 932 u8 log_max_qp; 933 struct { 934 int size; 935 int limit; 936 } mr_cache[MAX_MR_CACHE_ENTRIES]; 937 }; 938 939 940 #define MLX5_EEPROM_MAX_BYTES 32 941 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 942 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 943 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 944 #endif /* MLX5_DRIVER_H */ 945