xref: /freebsd/sys/dev/mlx5/driver.h (revision 792bbaba989533a1fc93823df1720c8c4aaf0442)
1 /*-
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include <linux/kernel.h>
32 #include <linux/completion.h>
33 #include <linux/pci.h>
34 #include <linux/cache.h>
35 #include <linux/rbtree.h>
36 #include <linux/if_ether.h>
37 #include <linux/semaphore.h>
38 #include <linux/slab.h>
39 #include <linux/vmalloc.h>
40 #include <linux/radix-tree.h>
41 
42 #include <dev/mlx5/device.h>
43 #include <dev/mlx5/doorbell.h>
44 
45 #define MLX5_QCOUNTER_SETS_NETDEV 64
46 
47 enum {
48 	MLX5_BOARD_ID_LEN = 64,
49 	MLX5_MAX_NAME_LEN = 16,
50 };
51 
52 enum {
53 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
54 	MLX5_CMD_WQ_MAX_NAME	= 32,
55 };
56 
57 enum {
58 	CMD_OWNER_SW		= 0x0,
59 	CMD_OWNER_HW		= 0x1,
60 	CMD_STATUS_SUCCESS	= 0,
61 };
62 
63 enum mlx5_sqp_t {
64 	MLX5_SQP_SMI		= 0,
65 	MLX5_SQP_GSI		= 1,
66 	MLX5_SQP_IEEE_1588	= 2,
67 	MLX5_SQP_SNIFFER	= 3,
68 	MLX5_SQP_SYNC_UMR	= 4,
69 };
70 
71 enum {
72 	MLX5_MAX_PORTS	= 2,
73 };
74 
75 enum {
76 	MLX5_EQ_VEC_PAGES	 = 0,
77 	MLX5_EQ_VEC_CMD		 = 1,
78 	MLX5_EQ_VEC_ASYNC	 = 2,
79 	MLX5_EQ_VEC_COMP_BASE,
80 };
81 
82 enum {
83 	MLX5_MAX_IRQ_NAME	= 32
84 };
85 
86 enum {
87 	MLX5_ATOMIC_MODE_OFF		= 16,
88 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
89 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
90 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
91 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
97 };
98 
99 enum {
100 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
101 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
102 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
103 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
104 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
110 };
111 
112 enum {
113 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
114 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
115 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
116 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
117 };
118 
119 enum {
120 	MLX5_REG_QETCR		 = 0x4005,
121 	MLX5_REG_QPDP		 = 0x4007,
122 	MLX5_REG_QTCT		 = 0x400A,
123 	MLX5_REG_QHLL		 = 0x4016,
124 	MLX5_REG_DCBX_PARAM	 = 0x4020,
125 	MLX5_REG_DCBX_APP	 = 0x4021,
126 	MLX5_REG_PCAP		 = 0x5001,
127 	MLX5_REG_PMTU		 = 0x5003,
128 	MLX5_REG_PTYS		 = 0x5004,
129 	MLX5_REG_PAOS		 = 0x5006,
130 	MLX5_REG_PFCC		 = 0x5007,
131 	MLX5_REG_PPCNT		 = 0x5008,
132 	MLX5_REG_PMAOS		 = 0x5012,
133 	MLX5_REG_PUDE		 = 0x5009,
134 	MLX5_REG_PPTB		 = 0x500B,
135 	MLX5_REG_PBMC		 = 0x500C,
136 	MLX5_REG_PMPE		 = 0x5010,
137 	MLX5_REG_PELC		 = 0x500e,
138 	MLX5_REG_PVLC		 = 0x500f,
139 	MLX5_REG_PMLP		 = 0x5002,
140 	MLX5_REG_NODE_DESC	 = 0x6001,
141 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
142 	MLX5_REG_MCIA		 = 0x9014,
143 	MLX5_REG_MPCNT		 = 0x9051,
144 };
145 
146 enum dbg_rsc_type {
147 	MLX5_DBG_RSC_QP,
148 	MLX5_DBG_RSC_EQ,
149 	MLX5_DBG_RSC_CQ,
150 };
151 
152 enum {
153 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
154 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
155 	MLX5_INTERFACE_NUMBER       = 2,
156 };
157 
158 struct mlx5_field_desc {
159 	struct dentry	       *dent;
160 	int			i;
161 };
162 
163 struct mlx5_rsc_debug {
164 	struct mlx5_core_dev   *dev;
165 	void		       *object;
166 	enum dbg_rsc_type	type;
167 	struct dentry	       *root;
168 	struct mlx5_field_desc	fields[0];
169 };
170 
171 enum mlx5_dev_event {
172 	MLX5_DEV_EVENT_SYS_ERROR,
173 	MLX5_DEV_EVENT_PORT_UP,
174 	MLX5_DEV_EVENT_PORT_DOWN,
175 	MLX5_DEV_EVENT_PORT_INITIALIZED,
176 	MLX5_DEV_EVENT_LID_CHANGE,
177 	MLX5_DEV_EVENT_PKEY_CHANGE,
178 	MLX5_DEV_EVENT_GUID_CHANGE,
179 	MLX5_DEV_EVENT_CLIENT_REREG,
180 	MLX5_DEV_EVENT_VPORT_CHANGE,
181 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
182 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
183 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
184 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
185 };
186 
187 enum mlx5_port_status {
188 	MLX5_PORT_UP        = 1 << 0,
189 	MLX5_PORT_DOWN      = 1 << 1,
190 };
191 
192 enum mlx5_link_mode {
193 	MLX5_1000BASE_CX_SGMII	= 0,
194 	MLX5_1000BASE_KX	= 1,
195 	MLX5_10GBASE_CX4	= 2,
196 	MLX5_10GBASE_KX4	= 3,
197 	MLX5_10GBASE_KR		= 4,
198 	MLX5_20GBASE_KR2	= 5,
199 	MLX5_40GBASE_CR4	= 6,
200 	MLX5_40GBASE_KR4	= 7,
201 	MLX5_56GBASE_R4		= 8,
202 	MLX5_10GBASE_CR		= 12,
203 	MLX5_10GBASE_SR		= 13,
204 	MLX5_10GBASE_ER		= 14,
205 	MLX5_40GBASE_SR4	= 15,
206 	MLX5_40GBASE_LR4	= 16,
207 	MLX5_100GBASE_CR4	= 20,
208 	MLX5_100GBASE_SR4	= 21,
209 	MLX5_100GBASE_KR4	= 22,
210 	MLX5_100GBASE_LR4	= 23,
211 	MLX5_100BASE_TX		= 24,
212 	MLX5_1000BASE_T		= 25,
213 	MLX5_10GBASE_T		= 26,
214 	MLX5_25GBASE_CR		= 27,
215 	MLX5_25GBASE_KR		= 28,
216 	MLX5_25GBASE_SR		= 29,
217 	MLX5_50GBASE_CR2	= 30,
218 	MLX5_50GBASE_KR2	= 31,
219 	MLX5_LINK_MODES_NUMBER,
220 };
221 
222 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
223 
224 struct mlx5_uuar_info {
225 	struct mlx5_uar	       *uars;
226 	int			num_uars;
227 	int			num_low_latency_uuars;
228 	unsigned long	       *bitmap;
229 	unsigned int	       *count;
230 	struct mlx5_bf	       *bfs;
231 
232 	/*
233 	 * protect uuar allocation data structs
234 	 */
235 	struct mutex		lock;
236 	u32			ver;
237 };
238 
239 struct mlx5_bf {
240 	void __iomem	       *reg;
241 	void __iomem	       *regreg;
242 	int			buf_size;
243 	struct mlx5_uar	       *uar;
244 	unsigned long		offset;
245 	int			need_lock;
246 	/* protect blue flame buffer selection when needed
247 	 */
248 	spinlock_t		lock;
249 
250 	/* serialize 64 bit writes when done as two 32 bit accesses
251 	 */
252 	spinlock_t		lock32;
253 	int			uuarn;
254 };
255 
256 struct mlx5_cmd_first {
257 	__be32		data[4];
258 };
259 
260 struct mlx5_cmd_msg {
261 	struct list_head		list;
262 	struct cache_ent	       *cache;
263 	u32				len;
264 	struct mlx5_cmd_first		first;
265 	struct mlx5_cmd_mailbox	       *next;
266 };
267 
268 struct mlx5_cmd_debug {
269 	struct dentry	       *dbg_root;
270 	struct dentry	       *dbg_in;
271 	struct dentry	       *dbg_out;
272 	struct dentry	       *dbg_outlen;
273 	struct dentry	       *dbg_status;
274 	struct dentry	       *dbg_run;
275 	void		       *in_msg;
276 	void		       *out_msg;
277 	u8			status;
278 	u16			inlen;
279 	u16			outlen;
280 };
281 
282 struct cache_ent {
283 	/* protect block chain allocations
284 	 */
285 	spinlock_t		lock;
286 	struct list_head	head;
287 };
288 
289 struct cmd_msg_cache {
290 	struct cache_ent	large;
291 	struct cache_ent	med;
292 
293 };
294 
295 struct mlx5_cmd_stats {
296 	u64		sum;
297 	u64		n;
298 	struct dentry  *root;
299 	struct dentry  *avg;
300 	struct dentry  *count;
301 	/* protect command average calculations */
302 	spinlock_t	lock;
303 };
304 
305 struct mlx5_cmd {
306 	void	       *cmd_alloc_buf;
307 	dma_addr_t	alloc_dma;
308 	int		alloc_size;
309 	void	       *cmd_buf;
310 	dma_addr_t	dma;
311 	u16		cmdif_rev;
312 	u8		log_sz;
313 	u8		log_stride;
314 	int		max_reg_cmds;
315 	int		events;
316 	u32 __iomem    *vector;
317 
318 	/* protect command queue allocations
319 	 */
320 	spinlock_t	alloc_lock;
321 
322 	/* protect token allocations
323 	 */
324 	spinlock_t	token_lock;
325 	u8		token;
326 	unsigned long	bitmask;
327 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
328 	struct workqueue_struct *wq;
329 	struct semaphore sem;
330 	struct semaphore pages_sem;
331 	int	mode;
332 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
333 	struct pci_pool *pool;
334 	struct mlx5_cmd_debug dbg;
335 	struct cmd_msg_cache cache;
336 	int checksum_disabled;
337 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
338 	int moving_to_polling;
339 };
340 
341 struct mlx5_port_caps {
342 	int	gid_table_len;
343 	int	pkey_table_len;
344 	u8	ext_port_cap;
345 };
346 
347 struct mlx5_cmd_mailbox {
348 	void	       *buf;
349 	dma_addr_t	dma;
350 	struct mlx5_cmd_mailbox *next;
351 };
352 
353 struct mlx5_buf_list {
354 	void		       *buf;
355 	dma_addr_t		map;
356 };
357 
358 struct mlx5_buf {
359 	struct mlx5_buf_list	direct;
360 	struct mlx5_buf_list   *page_list;
361 	int			nbufs;
362 	int			npages;
363 	int			size;
364 	u8			page_shift;
365 };
366 
367 struct mlx5_eq {
368 	struct mlx5_core_dev   *dev;
369 	__be32 __iomem	       *doorbell;
370 	u32			cons_index;
371 	struct mlx5_buf		buf;
372 	int			size;
373 	u8			irqn;
374 	u8			eqn;
375 	int			nent;
376 	u64			mask;
377 	struct list_head	list;
378 	int			index;
379 	struct mlx5_rsc_debug	*dbg;
380 };
381 
382 struct mlx5_core_psv {
383 	u32	psv_idx;
384 	struct psv_layout {
385 		u32	pd;
386 		u16	syndrome;
387 		u16	reserved;
388 		u16	bg;
389 		u16	app_tag;
390 		u32	ref_tag;
391 	} psv;
392 };
393 
394 struct mlx5_core_sig_ctx {
395 	struct mlx5_core_psv	psv_memory;
396 	struct mlx5_core_psv	psv_wire;
397 #if (__FreeBSD_version >= 1100000)
398 	struct ib_sig_err       err_item;
399 #endif
400 	bool			sig_status_checked;
401 	bool			sig_err_exists;
402 	u32			sigerr_count;
403 };
404 
405 struct mlx5_core_mr {
406 	u64			iova;
407 	u64			size;
408 	u32			key;
409 	u32			pd;
410 };
411 
412 enum mlx5_res_type {
413 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
414 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
415 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
416 	MLX5_RES_SRQ	= 3,
417 	MLX5_RES_XSRQ	= 4,
418 	MLX5_RES_DCT	= 5,
419 };
420 
421 struct mlx5_core_rsc_common {
422 	enum mlx5_res_type	res;
423 	atomic_t		refcount;
424 	struct completion	free;
425 };
426 
427 struct mlx5_core_srq {
428 	struct mlx5_core_rsc_common	common; /* must be first */
429 	u32				srqn;
430 	int				max;
431 	int				max_gs;
432 	int				max_avail_gather;
433 	int				wqe_shift;
434 	void				(*event)(struct mlx5_core_srq *, int);
435 	atomic_t			refcount;
436 	struct completion		free;
437 };
438 
439 struct mlx5_eq_table {
440 	void __iomem	       *update_ci;
441 	void __iomem	       *update_arm_ci;
442 	struct list_head	comp_eqs_list;
443 	struct mlx5_eq		pages_eq;
444 	struct mlx5_eq		async_eq;
445 	struct mlx5_eq		cmd_eq;
446 	int			num_comp_vectors;
447 	/* protect EQs list
448 	 */
449 	spinlock_t		lock;
450 };
451 
452 struct mlx5_uar {
453 	u32			index;
454 	void __iomem	       *bf_map;
455 	void __iomem	       *map;
456 };
457 
458 
459 struct mlx5_core_health {
460 	struct mlx5_health_buffer __iomem	*health;
461 	__be32 __iomem		       *health_counter;
462 	struct timer_list		timer;
463 	struct list_head		list;
464 	u32				prev;
465 	int				miss_counter;
466 };
467 
468 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
469 
470 struct mlx5_cq_linear_array_entry {
471 	spinlock_t	lock;
472 	struct mlx5_core_cq * volatile cq;
473 };
474 
475 struct mlx5_cq_table {
476 	/* protect radix tree
477 	 */
478 	spinlock_t		lock;
479 	struct radix_tree_root	tree;
480 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
481 };
482 
483 struct mlx5_qp_table {
484 	/* protect radix tree
485 	 */
486 	spinlock_t		lock;
487 	struct radix_tree_root	tree;
488 };
489 
490 struct mlx5_srq_table {
491 	/* protect radix tree
492 	 */
493 	spinlock_t		lock;
494 	struct radix_tree_root	tree;
495 };
496 
497 struct mlx5_mr_table {
498 	/* protect radix tree
499 	 */
500 	spinlock_t		lock;
501 	struct radix_tree_root	tree;
502 };
503 
504 struct mlx5_irq_info {
505 	char name[MLX5_MAX_IRQ_NAME];
506 };
507 
508 struct mlx5_priv {
509 	char			name[MLX5_MAX_NAME_LEN];
510 	struct mlx5_eq_table	eq_table;
511 	struct msix_entry	*msix_arr;
512 	struct mlx5_irq_info	*irq_info;
513 	struct mlx5_uuar_info	uuari;
514 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
515 
516 	struct io_mapping	*bf_mapping;
517 
518 	/* pages stuff */
519 	struct workqueue_struct *pg_wq;
520 	struct rb_root		page_root;
521 	int			fw_pages;
522 	atomic_t		reg_pages;
523 	struct list_head	free_list;
524 
525 	struct mlx5_core_health health;
526 
527 	struct mlx5_srq_table	srq_table;
528 
529 	/* start: qp staff */
530 	struct mlx5_qp_table	qp_table;
531 	struct dentry	       *qp_debugfs;
532 	struct dentry	       *eq_debugfs;
533 	struct dentry	       *cq_debugfs;
534 	struct dentry	       *cmdif_debugfs;
535 	/* end: qp staff */
536 
537 	/* start: cq staff */
538 	struct mlx5_cq_table	cq_table;
539 	/* end: cq staff */
540 
541 	/* start: mr staff */
542 	struct mlx5_mr_table	mr_table;
543 	/* end: mr staff */
544 
545 	/* start: alloc staff */
546 	int			numa_node;
547 
548 	struct mutex   pgdir_mutex;
549 	struct list_head        pgdir_list;
550 	/* end: alloc staff */
551 	struct dentry	       *dbg_root;
552 
553 	/* protect mkey key part */
554 	spinlock_t		mkey_lock;
555 	u8			mkey_key;
556 
557 	struct list_head        dev_list;
558 	struct list_head        ctx_list;
559 	spinlock_t              ctx_lock;
560 	unsigned long		pci_dev_data;
561 };
562 
563 enum mlx5_device_state {
564 	MLX5_DEVICE_STATE_UP,
565 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
566 };
567 
568 struct mlx5_special_contexts {
569 	int resd_lkey;
570 };
571 
572 struct mlx5_core_dev {
573 	struct pci_dev	       *pdev;
574 	char			board_id[MLX5_BOARD_ID_LEN];
575 	struct mlx5_cmd		cmd;
576 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
577 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
578 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
579 	struct mlx5_init_seg __iomem *iseg;
580 	enum mlx5_device_state	state;
581 	void			(*event) (struct mlx5_core_dev *dev,
582 					  enum mlx5_dev_event event,
583 					  unsigned long param);
584 	struct mlx5_priv	priv;
585 	struct mlx5_profile	*profile;
586 	atomic_t		num_qps;
587 	u32			issi;
588 	struct mlx5_special_contexts special_contexts;
589 	unsigned int module_status[MLX5_MAX_PORTS];
590 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
591 };
592 
593 enum {
594 	MLX5_WOL_DISABLE       = 0,
595 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
596 	MLX5_WOL_MAGIC         = 1 << 2,
597 	MLX5_WOL_ARP           = 1 << 3,
598 	MLX5_WOL_BROADCAST     = 1 << 4,
599 	MLX5_WOL_MULTICAST     = 1 << 5,
600 	MLX5_WOL_UNICAST       = 1 << 6,
601 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
602 };
603 
604 struct mlx5_db {
605 	__be32			*db;
606 	union {
607 		struct mlx5_db_pgdir		*pgdir;
608 		struct mlx5_ib_user_db_page	*user_page;
609 	}			u;
610 	dma_addr_t		dma;
611 	int			index;
612 };
613 
614 struct mlx5_net_counters {
615 	u64	packets;
616 	u64	octets;
617 };
618 
619 struct mlx5_ptys_reg {
620 	u8	an_dis_admin;
621 	u8	an_dis_ap;
622 	u8	local_port;
623 	u8	proto_mask;
624 	u32	eth_proto_cap;
625 	u16	ib_link_width_cap;
626 	u16	ib_proto_cap;
627 	u32	eth_proto_admin;
628 	u16	ib_link_width_admin;
629 	u16	ib_proto_admin;
630 	u32	eth_proto_oper;
631 	u16	ib_link_width_oper;
632 	u16	ib_proto_oper;
633 	u32	eth_proto_lp_advertise;
634 };
635 
636 struct mlx5_pvlc_reg {
637 	u8	local_port;
638 	u8	vl_hw_cap;
639 	u8	vl_admin;
640 	u8	vl_operational;
641 };
642 
643 struct mlx5_pmtu_reg {
644 	u8	local_port;
645 	u16	max_mtu;
646 	u16	admin_mtu;
647 	u16	oper_mtu;
648 };
649 
650 struct mlx5_vport_counters {
651 	struct mlx5_net_counters	received_errors;
652 	struct mlx5_net_counters	transmit_errors;
653 	struct mlx5_net_counters	received_ib_unicast;
654 	struct mlx5_net_counters	transmitted_ib_unicast;
655 	struct mlx5_net_counters	received_ib_multicast;
656 	struct mlx5_net_counters	transmitted_ib_multicast;
657 	struct mlx5_net_counters	received_eth_broadcast;
658 	struct mlx5_net_counters	transmitted_eth_broadcast;
659 	struct mlx5_net_counters	received_eth_unicast;
660 	struct mlx5_net_counters	transmitted_eth_unicast;
661 	struct mlx5_net_counters	received_eth_multicast;
662 	struct mlx5_net_counters	transmitted_eth_multicast;
663 };
664 
665 enum {
666 	MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
667 };
668 
669 struct mlx5_core_dct {
670 	struct mlx5_core_rsc_common	common; /* must be first */
671 	void (*event)(struct mlx5_core_dct *, int);
672 	int			dctn;
673 	struct completion	drained;
674 	struct mlx5_rsc_debug	*dbg;
675 	int			pid;
676 };
677 
678 enum {
679 	MLX5_COMP_EQ_SIZE = 1024,
680 };
681 
682 enum {
683 	MLX5_PTYS_IB = 1 << 0,
684 	MLX5_PTYS_EN = 1 << 2,
685 };
686 
687 struct mlx5_db_pgdir {
688 	struct list_head	list;
689 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
690 	__be32		       *db_page;
691 	dma_addr_t		db_dma;
692 };
693 
694 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
695 
696 struct mlx5_cmd_work_ent {
697 	struct mlx5_cmd_msg    *in;
698 	struct mlx5_cmd_msg    *out;
699 	void		       *uout;
700 	int			uout_size;
701 	mlx5_cmd_cbk_t		callback;
702 	void		       *context;
703 	int			idx;
704 	struct completion	done;
705 	struct mlx5_cmd        *cmd;
706 	struct work_struct	work;
707 	struct mlx5_cmd_layout *lay;
708 	int			ret;
709 	int			page_queue;
710 	u8			status;
711 	u8			token;
712 	u64			ts1;
713 	u64			ts2;
714 	u16			op;
715 };
716 
717 struct mlx5_pas {
718 	u64	pa;
719 	u8	log_sz;
720 };
721 
722 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
723 {
724 	if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
725 		return buf->direct.buf + offset;
726 	else
727 		return buf->page_list[offset >> PAGE_SHIFT].buf +
728 			(offset & (PAGE_SIZE - 1));
729 }
730 
731 
732 extern struct workqueue_struct *mlx5_core_wq;
733 
734 #define STRUCT_FIELD(header, field) \
735 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
736 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
737 
738 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
739 {
740 	return pci_get_drvdata(pdev);
741 }
742 
743 extern struct dentry *mlx5_debugfs_root;
744 
745 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
746 {
747 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
748 }
749 
750 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
751 {
752 	return ioread32be(&dev->iseg->fw_rev) >> 16;
753 }
754 
755 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
756 {
757 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
758 }
759 
760 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
761 {
762 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
763 }
764 
765 static inline int mlx5_get_gid_table_len(u16 param)
766 {
767 	if (param > 4) {
768 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
769 		return 0;
770 	}
771 
772 	return 8 * (1 << param);
773 }
774 
775 static inline void *mlx5_vzalloc(unsigned long size)
776 {
777 	void *rtn;
778 
779 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
780 	return rtn;
781 }
782 
783 static inline void *mlx5_vmalloc(unsigned long size)
784 {
785 	void *rtn;
786 
787 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
788 	if (!rtn)
789 		rtn = vmalloc(size);
790 	return rtn;
791 }
792 
793 int mlx5_cmd_init(struct mlx5_core_dev *dev);
794 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
795 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
796 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
797 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
798 int mlx5_cmd_status_to_err_v2(void *ptr);
799 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
800 		       enum mlx5_cap_mode cap_mode);
801 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
802 		  int out_size);
803 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
804 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
805 		     void *context);
806 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
807 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
808 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
809 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
810 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
811 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
812 void mlx5_health_cleanup(void);
813 void  __init mlx5_health_init(void);
814 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
815 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
816 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, int max_direct,
817 			struct mlx5_buf *buf, int node);
818 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
819 		   struct mlx5_buf *buf);
820 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
821 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
822 			 struct mlx5_create_srq_mbox_in *in, int inlen,
823 			 int is_xrc);
824 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
825 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
826 			struct mlx5_query_srq_mbox_out *out);
827 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
828 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
829 		      u16 lwm, int is_srq);
830 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
831 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
832 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
833 			  struct mlx5_create_mkey_mbox_in *in, int inlen,
834 			  mlx5_cmd_cbk_t callback, void *context,
835 			  struct mlx5_create_mkey_mbox_out *out);
836 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
837 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
838 			 struct mlx5_query_mkey_mbox_out *out, int outlen);
839 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
840 			     u32 *mkey);
841 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
842 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
843 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
844 		      u16 opmod, u8 port);
845 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
846 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
847 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
848 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
849 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
850 				 s32 npages);
851 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
852 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
853 void mlx5_register_debugfs(void);
854 void mlx5_unregister_debugfs(void);
855 int mlx5_eq_init(struct mlx5_core_dev *dev);
856 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
857 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
858 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
859 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
860 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
861 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
862 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
863 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
864 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
865 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
866 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
867 int mlx5_start_eqs(struct mlx5_core_dev *dev);
868 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
869 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
870 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
871 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
872 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
873 				u64 addr);
874 
875 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
876 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
877 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
878 			 int size_in, void *data_out, int size_out,
879 			 u16 reg_num, int arg, int write);
880 
881 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
882 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
883 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
884 			 int ptys_size, int proto_mask);
885 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
886 			      u32 *proto_cap, int proto_mask);
887 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
888 			    u8 *an_disable_cap, u8 *an_disable_status);
889 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
890 			  u32 eth_proto_admin, int proto_mask);
891 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
892 				u32 *proto_admin, int proto_mask);
893 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
894 			int proto_mask);
895 int mlx5_set_port_status(struct mlx5_core_dev *dev,
896 			 enum mlx5_port_status status);
897 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
898 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
899 				 enum mlx5_port_status *status);
900 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port,
901 			u32 rx_pause, u32 tx_pause);
902 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
903 			  u32 *rx_pause, u32 *tx_pause);
904 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
905 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
906 
907 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
908 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
909 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
910 
911 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
912 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
913 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
914 		      int device_addr, int size, int module_num, u32 *data,
915 		      int *size_read);
916 
917 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
918 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
919 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
920 		       struct mlx5_query_eq_mbox_out *out, int outlen);
921 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
922 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
923 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
924 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
925 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
926 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
927 		       int node);
928 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
929 
930 const char *mlx5_command_str(int command);
931 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
932 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
933 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
934 			 int npsvs, u32 *sig_index);
935 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
936 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
937 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
938 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
939 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
940 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
941 			  struct mlx5_pvlc_reg *pvlc, int write);
942 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
943 			  struct mlx5_ptys_reg *ptys, int write);
944 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
945 			  struct mlx5_pmtu_reg *pmtu, int write);
946 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
947 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
948 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
949 				int priority, int *is_enable);
950 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
951 				 int priority, int enable);
952 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
953 				void *out, int out_size);
954 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
955 				 void *in, int in_size);
956 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
957 				    void *out, int out_size);
958 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
959 			       int in_size);
960 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
961 				   u8 num_of_samples, u16 sample_index,
962 				   void *out, int out_size);
963 static inline u32 mlx5_mkey_to_idx(u32 mkey)
964 {
965 	return mkey >> 8;
966 }
967 
968 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
969 {
970 	return mkey_idx << 8;
971 }
972 
973 static inline u8 mlx5_mkey_variant(u32 mkey)
974 {
975 	return mkey & 0xff;
976 }
977 
978 enum {
979 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
980 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
981 };
982 
983 enum {
984 	MAX_MR_CACHE_ENTRIES    = 15,
985 };
986 
987 struct mlx5_interface {
988 	void *			(*add)(struct mlx5_core_dev *dev);
989 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
990 	void			(*event)(struct mlx5_core_dev *dev, void *context,
991 					 enum mlx5_dev_event event, unsigned long param);
992 	void *                  (*get_dev)(void *context);
993 	int			protocol;
994 	struct list_head	list;
995 };
996 
997 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
998 int mlx5_register_interface(struct mlx5_interface *intf);
999 void mlx5_unregister_interface(struct mlx5_interface *intf);
1000 
1001 struct mlx5_profile {
1002 	u64	mask;
1003 	u8	log_max_qp;
1004 	struct {
1005 		int	size;
1006 		int	limit;
1007 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1008 };
1009 
1010 enum {
1011 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1012 };
1013 
1014 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1015 {
1016 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1017 }
1018 
1019 #define MLX5_EEPROM_MAX_BYTES			32
1020 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK	0x000000ff
1021 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK	0x0000ff00
1022 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK	0x00040000
1023 #endif /* MLX5_DRIVER_H */
1024