1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include "opt_ratelimit.h" 32 33 #include <linux/kernel.h> 34 #include <linux/completion.h> 35 #include <linux/pci.h> 36 #include <linux/cache.h> 37 #include <linux/rbtree.h> 38 #include <linux/if_ether.h> 39 #include <linux/semaphore.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <linux/radix-tree.h> 43 #include <linux/idr.h> 44 45 #include <dev/mlx5/device.h> 46 #include <dev/mlx5/doorbell.h> 47 #include <dev/mlx5/srq.h> 48 49 #define MLX5_QCOUNTER_SETS_NETDEV 64 50 #define MLX5_MAX_NUMBER_OF_VFS 128 51 52 enum { 53 MLX5_BOARD_ID_LEN = 64, 54 MLX5_MAX_NAME_LEN = 16, 55 }; 56 57 enum { 58 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 59 MLX5_CMD_WQ_MAX_NAME = 32, 60 }; 61 62 enum { 63 CMD_OWNER_SW = 0x0, 64 CMD_OWNER_HW = 0x1, 65 CMD_STATUS_SUCCESS = 0, 66 }; 67 68 enum mlx5_sqp_t { 69 MLX5_SQP_SMI = 0, 70 MLX5_SQP_GSI = 1, 71 MLX5_SQP_IEEE_1588 = 2, 72 MLX5_SQP_SNIFFER = 3, 73 MLX5_SQP_SYNC_UMR = 4, 74 }; 75 76 enum { 77 MLX5_MAX_PORTS = 2, 78 }; 79 80 enum { 81 MLX5_EQ_VEC_PAGES = 0, 82 MLX5_EQ_VEC_CMD = 1, 83 MLX5_EQ_VEC_ASYNC = 2, 84 MLX5_EQ_VEC_COMP_BASE, 85 }; 86 87 enum { 88 MLX5_MAX_IRQ_NAME = 32 89 }; 90 91 enum { 92 MLX5_ATOMIC_MODE_OFF = 16, 93 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 99 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 100 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 101 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 102 }; 103 104 enum { 105 MLX5_ATOMIC_MODE_DCT_OFF = 20, 106 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 112 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 113 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 114 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 115 }; 116 117 enum { 118 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 119 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 120 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 121 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 122 }; 123 124 enum { 125 MLX5_REG_QPTS = 0x4002, 126 MLX5_REG_QETCR = 0x4005, 127 MLX5_REG_QPDP = 0x4007, 128 MLX5_REG_QTCT = 0x400A, 129 MLX5_REG_QPDPM = 0x4013, 130 MLX5_REG_QHLL = 0x4016, 131 MLX5_REG_QCAM = 0x4019, 132 MLX5_REG_DCBX_PARAM = 0x4020, 133 MLX5_REG_DCBX_APP = 0x4021, 134 MLX5_REG_PCAP = 0x5001, 135 MLX5_REG_FPGA_CAP = 0x4022, 136 MLX5_REG_FPGA_CTRL = 0x4023, 137 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 138 MLX5_REG_FPGA_SHELL_CNTR = 0x4025, 139 MLX5_REG_PMTU = 0x5003, 140 MLX5_REG_PTYS = 0x5004, 141 MLX5_REG_PAOS = 0x5006, 142 MLX5_REG_PFCC = 0x5007, 143 MLX5_REG_PPCNT = 0x5008, 144 MLX5_REG_PMAOS = 0x5012, 145 MLX5_REG_PUDE = 0x5009, 146 MLX5_REG_PPTB = 0x500B, 147 MLX5_REG_PBMC = 0x500C, 148 MLX5_REG_PMPE = 0x5010, 149 MLX5_REG_PELC = 0x500e, 150 MLX5_REG_PVLC = 0x500f, 151 MLX5_REG_PMLP = 0x5002, 152 MLX5_REG_PCAM = 0x507f, 153 MLX5_REG_NODE_DESC = 0x6001, 154 MLX5_REG_HOST_ENDIANNESS = 0x7004, 155 MLX5_REG_MTMP = 0x900a, 156 MLX5_REG_MCIA = 0x9014, 157 MLX5_REG_MPCNT = 0x9051, 158 MLX5_REG_MCQI = 0x9061, 159 MLX5_REG_MCC = 0x9062, 160 MLX5_REG_MCDA = 0x9063, 161 MLX5_REG_MCAM = 0x907f, 162 }; 163 164 enum dbg_rsc_type { 165 MLX5_DBG_RSC_QP, 166 MLX5_DBG_RSC_EQ, 167 MLX5_DBG_RSC_CQ, 168 }; 169 170 enum { 171 MLX5_INTERFACE_PROTOCOL_IB = 0, 172 MLX5_INTERFACE_PROTOCOL_ETH = 1, 173 MLX5_INTERFACE_NUMBER = 2, 174 }; 175 176 struct mlx5_field_desc { 177 struct dentry *dent; 178 int i; 179 }; 180 181 struct mlx5_rsc_debug { 182 struct mlx5_core_dev *dev; 183 void *object; 184 enum dbg_rsc_type type; 185 struct dentry *root; 186 struct mlx5_field_desc fields[0]; 187 }; 188 189 enum mlx5_dev_event { 190 MLX5_DEV_EVENT_SYS_ERROR, 191 MLX5_DEV_EVENT_PORT_UP, 192 MLX5_DEV_EVENT_PORT_DOWN, 193 MLX5_DEV_EVENT_PORT_INITIALIZED, 194 MLX5_DEV_EVENT_LID_CHANGE, 195 MLX5_DEV_EVENT_PKEY_CHANGE, 196 MLX5_DEV_EVENT_GUID_CHANGE, 197 MLX5_DEV_EVENT_CLIENT_REREG, 198 MLX5_DEV_EVENT_VPORT_CHANGE, 199 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 200 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 201 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 202 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 203 }; 204 205 enum mlx5_port_status { 206 MLX5_PORT_UP = 1 << 0, 207 MLX5_PORT_DOWN = 1 << 1, 208 }; 209 210 enum mlx5_link_mode { 211 MLX5_1000BASE_CX_SGMII = 0, 212 MLX5_1000BASE_KX = 1, 213 MLX5_10GBASE_CX4 = 2, 214 MLX5_10GBASE_KX4 = 3, 215 MLX5_10GBASE_KR = 4, 216 MLX5_20GBASE_KR2 = 5, 217 MLX5_40GBASE_CR4 = 6, 218 MLX5_40GBASE_KR4 = 7, 219 MLX5_56GBASE_R4 = 8, 220 MLX5_10GBASE_CR = 12, 221 MLX5_10GBASE_SR = 13, 222 MLX5_10GBASE_ER = 14, 223 MLX5_40GBASE_SR4 = 15, 224 MLX5_40GBASE_LR4 = 16, 225 MLX5_100GBASE_CR4 = 20, 226 MLX5_100GBASE_SR4 = 21, 227 MLX5_100GBASE_KR4 = 22, 228 MLX5_100GBASE_LR4 = 23, 229 MLX5_100BASE_TX = 24, 230 MLX5_1000BASE_T = 25, 231 MLX5_10GBASE_T = 26, 232 MLX5_25GBASE_CR = 27, 233 MLX5_25GBASE_KR = 28, 234 MLX5_25GBASE_SR = 29, 235 MLX5_50GBASE_CR2 = 30, 236 MLX5_50GBASE_KR2 = 31, 237 MLX5_LINK_MODES_NUMBER, 238 }; 239 240 enum { 241 MLX5_VSC_SPACE_SUPPORTED = 0x1, 242 MLX5_VSC_SPACE_OFFSET = 0x4, 243 MLX5_VSC_COUNTER_OFFSET = 0x8, 244 MLX5_VSC_SEMA_OFFSET = 0xC, 245 MLX5_VSC_ADDR_OFFSET = 0x10, 246 MLX5_VSC_DATA_OFFSET = 0x14, 247 MLX5_VSC_MAX_RETRIES = 0x1000, 248 }; 249 250 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 251 252 struct mlx5_uuar_info { 253 struct mlx5_uar *uars; 254 int num_uars; 255 int num_low_latency_uuars; 256 unsigned long *bitmap; 257 unsigned int *count; 258 struct mlx5_bf *bfs; 259 260 /* 261 * protect uuar allocation data structs 262 */ 263 struct mutex lock; 264 u32 ver; 265 }; 266 267 struct mlx5_bf { 268 void __iomem *reg; 269 void __iomem *regreg; 270 int buf_size; 271 struct mlx5_uar *uar; 272 unsigned long offset; 273 int need_lock; 274 /* protect blue flame buffer selection when needed 275 */ 276 spinlock_t lock; 277 278 /* serialize 64 bit writes when done as two 32 bit accesses 279 */ 280 spinlock_t lock32; 281 int uuarn; 282 }; 283 284 struct mlx5_cmd_first { 285 __be32 data[4]; 286 }; 287 288 struct cache_ent; 289 struct mlx5_fw_page { 290 union { 291 struct rb_node rb_node; 292 struct list_head list; 293 }; 294 struct mlx5_cmd_first first; 295 struct mlx5_core_dev *dev; 296 bus_dmamap_t dma_map; 297 bus_addr_t dma_addr; 298 void *virt_addr; 299 struct cache_ent *cache; 300 u32 numpages; 301 u16 load_done; 302 #define MLX5_LOAD_ST_NONE 0 303 #define MLX5_LOAD_ST_SUCCESS 1 304 #define MLX5_LOAD_ST_FAILURE 2 305 u16 func_id; 306 }; 307 #define mlx5_cmd_msg mlx5_fw_page 308 309 struct mlx5_cmd_debug { 310 struct dentry *dbg_root; 311 struct dentry *dbg_in; 312 struct dentry *dbg_out; 313 struct dentry *dbg_outlen; 314 struct dentry *dbg_status; 315 struct dentry *dbg_run; 316 void *in_msg; 317 void *out_msg; 318 u8 status; 319 u16 inlen; 320 u16 outlen; 321 }; 322 323 struct cache_ent { 324 /* protect block chain allocations 325 */ 326 spinlock_t lock; 327 struct list_head head; 328 }; 329 330 struct cmd_msg_cache { 331 struct cache_ent large; 332 struct cache_ent med; 333 334 }; 335 336 struct mlx5_traffic_counter { 337 u64 packets; 338 u64 octets; 339 }; 340 341 enum mlx5_cmd_mode { 342 MLX5_CMD_MODE_POLLING, 343 MLX5_CMD_MODE_EVENTS 344 }; 345 346 struct mlx5_cmd_stats { 347 u64 sum; 348 u64 n; 349 struct dentry *root; 350 struct dentry *avg; 351 struct dentry *count; 352 /* protect command average calculations */ 353 spinlock_t lock; 354 }; 355 356 struct mlx5_cmd { 357 struct mlx5_fw_page *cmd_page; 358 bus_dma_tag_t dma_tag; 359 struct sx dma_sx; 360 struct mtx dma_mtx; 361 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 362 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 363 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 364 struct cv dma_cv; 365 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 366 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 367 void *cmd_buf; 368 dma_addr_t dma; 369 u16 cmdif_rev; 370 u8 log_sz; 371 u8 log_stride; 372 int max_reg_cmds; 373 int events; 374 u32 __iomem *vector; 375 376 /* protect command queue allocations 377 */ 378 spinlock_t alloc_lock; 379 380 /* protect token allocations 381 */ 382 spinlock_t token_lock; 383 u8 token; 384 unsigned long bitmask; 385 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 386 struct workqueue_struct *wq; 387 struct semaphore sem; 388 struct semaphore pages_sem; 389 enum mlx5_cmd_mode mode; 390 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS]; 391 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS]; 392 struct mlx5_cmd_debug dbg; 393 struct cmd_msg_cache cache; 394 int checksum_disabled; 395 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 396 }; 397 398 struct mlx5_port_caps { 399 int gid_table_len; 400 int pkey_table_len; 401 u8 ext_port_cap; 402 }; 403 404 struct mlx5_buf { 405 bus_dma_tag_t dma_tag; 406 bus_dmamap_t dma_map; 407 struct mlx5_core_dev *dev; 408 struct { 409 void *buf; 410 } direct; 411 u64 *page_list; 412 int npages; 413 int size; 414 u8 page_shift; 415 u8 load_done; 416 }; 417 418 struct mlx5_frag_buf { 419 struct mlx5_buf_list *frags; 420 int npages; 421 int size; 422 u8 page_shift; 423 }; 424 425 struct mlx5_eq { 426 struct mlx5_core_dev *dev; 427 __be32 __iomem *doorbell; 428 u32 cons_index; 429 struct mlx5_buf buf; 430 int size; 431 u8 irqn; 432 u8 eqn; 433 int nent; 434 u64 mask; 435 struct list_head list; 436 int index; 437 struct mlx5_rsc_debug *dbg; 438 }; 439 440 struct mlx5_core_psv { 441 u32 psv_idx; 442 struct psv_layout { 443 u32 pd; 444 u16 syndrome; 445 u16 reserved; 446 u16 bg; 447 u16 app_tag; 448 u32 ref_tag; 449 } psv; 450 }; 451 452 struct mlx5_core_sig_ctx { 453 struct mlx5_core_psv psv_memory; 454 struct mlx5_core_psv psv_wire; 455 #if (__FreeBSD_version >= 1100000) 456 struct ib_sig_err err_item; 457 #endif 458 bool sig_status_checked; 459 bool sig_err_exists; 460 u32 sigerr_count; 461 }; 462 463 enum { 464 MLX5_MKEY_MR = 1, 465 MLX5_MKEY_MW, 466 MLX5_MKEY_MR_USER, 467 }; 468 469 struct mlx5_core_mkey { 470 u64 iova; 471 u64 size; 472 u32 key; 473 u32 pd; 474 u32 type; 475 }; 476 477 struct mlx5_core_mr { 478 u64 iova; 479 u64 size; 480 u32 key; 481 u32 pd; 482 }; 483 484 enum mlx5_res_type { 485 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 486 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 487 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 488 MLX5_RES_SRQ = 3, 489 MLX5_RES_XSRQ = 4, 490 MLX5_RES_DCT = 5, 491 }; 492 493 struct mlx5_core_rsc_common { 494 enum mlx5_res_type res; 495 atomic_t refcount; 496 struct completion free; 497 }; 498 499 struct mlx5_core_srq { 500 struct mlx5_core_rsc_common common; /* must be first */ 501 u32 srqn; 502 int max; 503 size_t max_gs; 504 size_t max_avail_gather; 505 int wqe_shift; 506 void (*event)(struct mlx5_core_srq *, int); 507 atomic_t refcount; 508 struct completion free; 509 }; 510 511 struct mlx5_eq_table { 512 void __iomem *update_ci; 513 void __iomem *update_arm_ci; 514 struct list_head comp_eqs_list; 515 struct mlx5_eq pages_eq; 516 struct mlx5_eq async_eq; 517 struct mlx5_eq cmd_eq; 518 int num_comp_vectors; 519 /* protect EQs list 520 */ 521 spinlock_t lock; 522 }; 523 524 struct mlx5_uar { 525 u32 index; 526 void __iomem *bf_map; 527 void __iomem *map; 528 }; 529 530 531 struct mlx5_core_health { 532 struct mlx5_health_buffer __iomem *health; 533 __be32 __iomem *health_counter; 534 struct timer_list timer; 535 u32 prev; 536 int miss_counter; 537 u32 fatal_error; 538 /* wq spinlock to synchronize draining */ 539 spinlock_t wq_lock; 540 struct workqueue_struct *wq; 541 unsigned long flags; 542 struct work_struct work; 543 struct delayed_work recover_work; 544 unsigned int last_reset_req; 545 }; 546 547 #ifdef RATELIMIT 548 #define MLX5_CQ_LINEAR_ARRAY_SIZE (128 * 1024) 549 #else 550 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 551 #endif 552 553 struct mlx5_cq_linear_array_entry { 554 spinlock_t lock; 555 struct mlx5_core_cq * volatile cq; 556 }; 557 558 struct mlx5_cq_table { 559 /* protect radix tree 560 */ 561 spinlock_t lock; 562 struct radix_tree_root tree; 563 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 564 }; 565 566 struct mlx5_qp_table { 567 /* protect radix tree 568 */ 569 spinlock_t lock; 570 struct radix_tree_root tree; 571 }; 572 573 struct mlx5_srq_table { 574 /* protect radix tree 575 */ 576 spinlock_t lock; 577 struct radix_tree_root tree; 578 }; 579 580 struct mlx5_mr_table { 581 /* protect radix tree 582 */ 583 spinlock_t lock; 584 struct radix_tree_root tree; 585 }; 586 587 struct mlx5_irq_info { 588 char name[MLX5_MAX_IRQ_NAME]; 589 }; 590 591 #ifdef RATELIMIT 592 struct mlx5_rl_entry { 593 u32 rate; 594 u16 burst; 595 u16 index; 596 u32 refcount; 597 }; 598 599 struct mlx5_rl_table { 600 struct mutex rl_lock; 601 u16 max_size; 602 u32 max_rate; 603 u32 min_rate; 604 struct mlx5_rl_entry *rl_entry; 605 }; 606 #endif 607 608 struct mlx5_priv { 609 char name[MLX5_MAX_NAME_LEN]; 610 struct mlx5_eq_table eq_table; 611 struct msix_entry *msix_arr; 612 struct mlx5_irq_info *irq_info; 613 struct mlx5_uuar_info uuari; 614 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 615 int disable_irqs; 616 617 struct io_mapping *bf_mapping; 618 619 /* pages stuff */ 620 struct workqueue_struct *pg_wq; 621 struct rb_root page_root; 622 s64 fw_pages; 623 atomic_t reg_pages; 624 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 625 struct mlx5_core_health health; 626 627 struct mlx5_srq_table srq_table; 628 629 /* start: qp staff */ 630 struct mlx5_qp_table qp_table; 631 struct dentry *qp_debugfs; 632 struct dentry *eq_debugfs; 633 struct dentry *cq_debugfs; 634 struct dentry *cmdif_debugfs; 635 /* end: qp staff */ 636 637 /* start: cq staff */ 638 struct mlx5_cq_table cq_table; 639 /* end: cq staff */ 640 641 /* start: mr staff */ 642 struct mlx5_mr_table mr_table; 643 /* end: mr staff */ 644 645 /* start: alloc staff */ 646 int numa_node; 647 648 struct mutex pgdir_mutex; 649 struct list_head pgdir_list; 650 /* end: alloc staff */ 651 struct dentry *dbg_root; 652 653 /* protect mkey key part */ 654 spinlock_t mkey_lock; 655 u8 mkey_key; 656 657 struct list_head dev_list; 658 struct list_head ctx_list; 659 spinlock_t ctx_lock; 660 unsigned long pci_dev_data; 661 #ifdef RATELIMIT 662 struct mlx5_rl_table rl_table; 663 #endif 664 }; 665 666 enum mlx5_device_state { 667 MLX5_DEVICE_STATE_UP, 668 MLX5_DEVICE_STATE_INTERNAL_ERROR, 669 }; 670 671 enum mlx5_interface_state { 672 MLX5_INTERFACE_STATE_UP, 673 }; 674 675 enum mlx5_pci_status { 676 MLX5_PCI_STATUS_DISABLED, 677 MLX5_PCI_STATUS_ENABLED, 678 }; 679 680 #define MLX5_MAX_RESERVED_GIDS 8 681 682 struct mlx5_rsvd_gids { 683 unsigned int start; 684 unsigned int count; 685 struct ida ida; 686 }; 687 688 struct mlx5_special_contexts { 689 int resd_lkey; 690 }; 691 692 struct mlx5_flow_root_namespace; 693 struct mlx5_dump_data; 694 struct mlx5_core_dev { 695 struct pci_dev *pdev; 696 /* sync pci state */ 697 struct mutex pci_status_mutex; 698 enum mlx5_pci_status pci_status; 699 char board_id[MLX5_BOARD_ID_LEN]; 700 struct mlx5_cmd cmd; 701 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 702 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 703 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 704 struct { 705 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 706 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 707 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 708 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 709 } caps; 710 phys_addr_t iseg_base; 711 struct mlx5_init_seg __iomem *iseg; 712 enum mlx5_device_state state; 713 /* sync interface state */ 714 struct mutex intf_state_mutex; 715 unsigned long intf_state; 716 void (*event) (struct mlx5_core_dev *dev, 717 enum mlx5_dev_event event, 718 unsigned long param); 719 struct mlx5_priv priv; 720 struct mlx5_profile *profile; 721 atomic_t num_qps; 722 u32 vsc_addr; 723 u32 issi; 724 struct mlx5_special_contexts special_contexts; 725 unsigned int module_status[MLX5_MAX_PORTS]; 726 struct mlx5_flow_root_namespace *root_ns; 727 struct mlx5_flow_root_namespace *fdb_root_ns; 728 struct mlx5_flow_root_namespace *esw_egress_root_ns; 729 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 730 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 731 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 732 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 733 struct mlx5_dump_data *dump_data; 734 735 struct sysctl_ctx_list sysctl_ctx; 736 int msix_eqvec; 737 738 struct { 739 struct mlx5_rsvd_gids reserved_gids; 740 atomic_t roce_en; 741 } roce; 742 #ifdef CONFIG_MLX5_FPGA 743 struct mlx5_fpga_device *fpga; 744 #endif 745 }; 746 747 enum { 748 MLX5_WOL_DISABLE = 0, 749 MLX5_WOL_SECURED_MAGIC = 1 << 1, 750 MLX5_WOL_MAGIC = 1 << 2, 751 MLX5_WOL_ARP = 1 << 3, 752 MLX5_WOL_BROADCAST = 1 << 4, 753 MLX5_WOL_MULTICAST = 1 << 5, 754 MLX5_WOL_UNICAST = 1 << 6, 755 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 756 }; 757 758 struct mlx5_db { 759 __be32 *db; 760 union { 761 struct mlx5_db_pgdir *pgdir; 762 struct mlx5_ib_user_db_page *user_page; 763 } u; 764 dma_addr_t dma; 765 int index; 766 }; 767 768 struct mlx5_net_counters { 769 u64 packets; 770 u64 octets; 771 }; 772 773 struct mlx5_ptys_reg { 774 u8 an_dis_admin; 775 u8 an_dis_ap; 776 u8 local_port; 777 u8 proto_mask; 778 u32 eth_proto_cap; 779 u16 ib_link_width_cap; 780 u16 ib_proto_cap; 781 u32 eth_proto_admin; 782 u16 ib_link_width_admin; 783 u16 ib_proto_admin; 784 u32 eth_proto_oper; 785 u16 ib_link_width_oper; 786 u16 ib_proto_oper; 787 u32 eth_proto_lp_advertise; 788 }; 789 790 struct mlx5_pvlc_reg { 791 u8 local_port; 792 u8 vl_hw_cap; 793 u8 vl_admin; 794 u8 vl_operational; 795 }; 796 797 struct mlx5_pmtu_reg { 798 u8 local_port; 799 u16 max_mtu; 800 u16 admin_mtu; 801 u16 oper_mtu; 802 }; 803 804 struct mlx5_vport_counters { 805 struct mlx5_net_counters received_errors; 806 struct mlx5_net_counters transmit_errors; 807 struct mlx5_net_counters received_ib_unicast; 808 struct mlx5_net_counters transmitted_ib_unicast; 809 struct mlx5_net_counters received_ib_multicast; 810 struct mlx5_net_counters transmitted_ib_multicast; 811 struct mlx5_net_counters received_eth_broadcast; 812 struct mlx5_net_counters transmitted_eth_broadcast; 813 struct mlx5_net_counters received_eth_unicast; 814 struct mlx5_net_counters transmitted_eth_unicast; 815 struct mlx5_net_counters received_eth_multicast; 816 struct mlx5_net_counters transmitted_eth_multicast; 817 }; 818 819 enum { 820 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 821 }; 822 823 struct mlx5_core_dct { 824 struct mlx5_core_rsc_common common; /* must be first */ 825 void (*event)(struct mlx5_core_dct *, int); 826 int dctn; 827 struct completion drained; 828 struct mlx5_rsc_debug *dbg; 829 int pid; 830 }; 831 832 enum { 833 MLX5_COMP_EQ_SIZE = 1024, 834 }; 835 836 enum { 837 MLX5_PTYS_IB = 1 << 0, 838 MLX5_PTYS_EN = 1 << 2, 839 }; 840 841 struct mlx5_db_pgdir { 842 struct list_head list; 843 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 844 struct mlx5_fw_page *fw_page; 845 __be32 *db_page; 846 dma_addr_t db_dma; 847 }; 848 849 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 850 851 struct mlx5_cmd_work_ent { 852 struct mlx5_cmd_msg *in; 853 struct mlx5_cmd_msg *out; 854 int uin_size; 855 void *uout; 856 int uout_size; 857 mlx5_cmd_cbk_t callback; 858 struct delayed_work cb_timeout_work; 859 void *context; 860 int idx; 861 struct completion done; 862 struct mlx5_cmd *cmd; 863 struct work_struct work; 864 struct mlx5_cmd_layout *lay; 865 int ret; 866 int page_queue; 867 u8 status; 868 u8 token; 869 u64 ts1; 870 u64 ts2; 871 u16 op; 872 u8 busy; 873 bool polling; 874 }; 875 876 struct mlx5_pas { 877 u64 pa; 878 u8 log_sz; 879 }; 880 881 enum port_state_policy { 882 MLX5_POLICY_DOWN = 0, 883 MLX5_POLICY_UP = 1, 884 MLX5_POLICY_FOLLOW = 2, 885 MLX5_POLICY_INVALID = 0xffffffff 886 }; 887 888 static inline void * 889 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 890 { 891 return ((char *)buf->direct.buf + offset); 892 } 893 894 895 extern struct workqueue_struct *mlx5_core_wq; 896 897 #define STRUCT_FIELD(header, field) \ 898 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 899 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 900 901 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 902 { 903 return pci_get_drvdata(pdev); 904 } 905 906 extern struct dentry *mlx5_debugfs_root; 907 908 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 909 { 910 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 911 } 912 913 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 914 { 915 return ioread32be(&dev->iseg->fw_rev) >> 16; 916 } 917 918 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 919 { 920 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 921 } 922 923 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 924 { 925 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 926 } 927 928 static inline int mlx5_get_gid_table_len(u16 param) 929 { 930 if (param > 4) { 931 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 932 return 0; 933 } 934 935 return 8 * (1 << param); 936 } 937 938 static inline void *mlx5_vzalloc(unsigned long size) 939 { 940 void *rtn; 941 942 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 943 return rtn; 944 } 945 946 static inline void *mlx5_vmalloc(unsigned long size) 947 { 948 void *rtn; 949 950 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 951 if (!rtn) 952 rtn = vmalloc(size); 953 return rtn; 954 } 955 956 static inline u32 mlx5_base_mkey(const u32 key) 957 { 958 return key & 0xffffff00u; 959 } 960 961 int mlx5_cmd_init(struct mlx5_core_dev *dev); 962 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 963 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 964 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 965 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 966 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 967 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 968 int out_size); 969 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 970 void *out, int out_size, mlx5_cmd_cbk_t callback, 971 void *context); 972 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 973 void *out, int out_size); 974 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 975 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 976 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 977 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 978 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 979 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 980 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 981 int mlx5_health_init(struct mlx5_core_dev *dev); 982 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 983 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 984 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 985 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 986 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 987 988 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 989 mlx5_buf_alloc(dev, size, direct, buf) 990 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 991 struct mlx5_buf *buf); 992 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 993 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 994 struct mlx5_srq_attr *in); 995 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 996 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 997 struct mlx5_srq_attr *out); 998 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 999 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1000 u16 lwm, int is_srq); 1001 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 1002 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 1003 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 1004 struct mlx5_core_mr *mkey, 1005 u32 *in, int inlen, 1006 u32 *out, int outlen, 1007 mlx5_cmd_cbk_t callback, void *context); 1008 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 1009 struct mlx5_core_mr *mr, 1010 u32 *in, int inlen); 1011 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 1012 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 1013 u32 *out, int outlen); 1014 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 1015 u32 *mkey); 1016 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 1017 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 1018 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 1019 u16 opmod, u8 port); 1020 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 1021 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 1022 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 1023 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 1024 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 1025 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 1026 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 1027 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 1028 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 1029 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 1030 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 1031 s32 npages); 1032 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 1033 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 1034 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 1035 void mlx5_register_debugfs(void); 1036 void mlx5_unregister_debugfs(void); 1037 int mlx5_eq_init(struct mlx5_core_dev *dev); 1038 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 1039 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 1040 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 1041 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1042 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1043 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1044 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode); 1045 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 1046 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 1047 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 1048 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1049 int mlx5_start_eqs(struct mlx5_core_dev *dev); 1050 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 1051 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 1052 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1053 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1054 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 1055 u64 addr); 1056 1057 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1058 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1059 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1060 int size_in, void *data_out, int size_out, 1061 u16 reg_num, int arg, int write); 1062 1063 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1064 1065 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1066 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1067 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1068 u32 *out, int outlen); 1069 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1070 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1071 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1072 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1073 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1074 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1075 int node); 1076 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1077 1078 const char *mlx5_command_str(int command); 1079 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1080 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1081 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1082 int npsvs, u32 *sig_index); 1083 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1084 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1085 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1086 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1087 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1088 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1089 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1090 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1091 struct mlx5_pvlc_reg *pvlc, int write); 1092 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1093 struct mlx5_ptys_reg *ptys, int write); 1094 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1095 struct mlx5_pmtu_reg *pmtu, int write); 1096 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1097 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1098 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1099 int priority, int *is_enable); 1100 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1101 int priority, int enable); 1102 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1103 void *out, int out_size); 1104 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1105 void *in, int in_size); 1106 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1107 void *out, int out_size); 1108 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1109 int in_size); 1110 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1111 u8 num_of_samples, u16 sample_index, 1112 void *out, int out_size); 1113 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1114 int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1115 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1116 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1117 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1118 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1119 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1120 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1121 1122 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1123 { 1124 return mkey >> 8; 1125 } 1126 1127 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1128 { 1129 return mkey_idx << 8; 1130 } 1131 1132 static inline u8 mlx5_mkey_variant(u32 mkey) 1133 { 1134 return mkey & 0xff; 1135 } 1136 1137 enum { 1138 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1139 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1140 }; 1141 1142 enum { 1143 MAX_MR_CACHE_ENTRIES = 15, 1144 }; 1145 1146 struct mlx5_interface { 1147 void * (*add)(struct mlx5_core_dev *dev); 1148 void (*remove)(struct mlx5_core_dev *dev, void *context); 1149 void (*event)(struct mlx5_core_dev *dev, void *context, 1150 enum mlx5_dev_event event, unsigned long param); 1151 void * (*get_dev)(void *context); 1152 int protocol; 1153 struct list_head list; 1154 }; 1155 1156 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1157 int mlx5_register_interface(struct mlx5_interface *intf); 1158 void mlx5_unregister_interface(struct mlx5_interface *intf); 1159 1160 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1161 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1162 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1163 const u8 *mac, bool vlan, u16 vlan_id); 1164 1165 struct mlx5_profile { 1166 u64 mask; 1167 u8 log_max_qp; 1168 struct { 1169 int size; 1170 int limit; 1171 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1172 }; 1173 1174 enum { 1175 MLX5_PCI_DEV_IS_VF = 1 << 0, 1176 }; 1177 1178 enum { 1179 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1180 }; 1181 1182 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1183 { 1184 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1185 } 1186 #ifdef RATELIMIT 1187 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1188 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1189 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index); 1190 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst); 1191 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst); 1192 1193 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1194 { 1195 return !!(dev->priv.rl_table.max_size); 1196 } 1197 #endif 1198 1199 #endif /* MLX5_DRIVER_H */ 1200