1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include <linux/kernel.h> 32 #include <linux/completion.h> 33 #include <linux/pci.h> 34 #include <linux/cache.h> 35 #include <linux/rbtree.h> 36 #include <linux/if_ether.h> 37 #include <linux/semaphore.h> 38 #include <linux/slab.h> 39 #include <linux/vmalloc.h> 40 #include <linux/radix-tree.h> 41 42 #include <dev/mlx5/device.h> 43 #include <dev/mlx5/doorbell.h> 44 45 #define MLX5_QCOUNTER_SETS_NETDEV 64 46 47 enum { 48 MLX5_BOARD_ID_LEN = 64, 49 MLX5_MAX_NAME_LEN = 16, 50 }; 51 52 enum { 53 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 54 MLX5_CMD_WQ_MAX_NAME = 32, 55 }; 56 57 enum { 58 CMD_OWNER_SW = 0x0, 59 CMD_OWNER_HW = 0x1, 60 CMD_STATUS_SUCCESS = 0, 61 }; 62 63 enum mlx5_sqp_t { 64 MLX5_SQP_SMI = 0, 65 MLX5_SQP_GSI = 1, 66 MLX5_SQP_IEEE_1588 = 2, 67 MLX5_SQP_SNIFFER = 3, 68 MLX5_SQP_SYNC_UMR = 4, 69 }; 70 71 enum { 72 MLX5_MAX_PORTS = 2, 73 }; 74 75 enum { 76 MLX5_EQ_VEC_PAGES = 0, 77 MLX5_EQ_VEC_CMD = 1, 78 MLX5_EQ_VEC_ASYNC = 2, 79 MLX5_EQ_VEC_COMP_BASE, 80 }; 81 82 enum { 83 MLX5_MAX_IRQ_NAME = 32 84 }; 85 86 enum { 87 MLX5_ATOMIC_MODE_OFF = 16, 88 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 89 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 90 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 91 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 97 }; 98 99 enum { 100 MLX5_ATOMIC_MODE_DCT_OFF = 20, 101 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 102 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 103 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 104 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 110 }; 111 112 enum { 113 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 114 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 115 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 116 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 117 }; 118 119 enum { 120 MLX5_REG_QETCR = 0x4005, 121 MLX5_REG_QPDP = 0x4007, 122 MLX5_REG_QTCT = 0x400A, 123 MLX5_REG_DCBX_PARAM = 0x4020, 124 MLX5_REG_DCBX_APP = 0x4021, 125 MLX5_REG_PCAP = 0x5001, 126 MLX5_REG_PMTU = 0x5003, 127 MLX5_REG_PTYS = 0x5004, 128 MLX5_REG_PAOS = 0x5006, 129 MLX5_REG_PFCC = 0x5007, 130 MLX5_REG_PPCNT = 0x5008, 131 MLX5_REG_PMAOS = 0x5012, 132 MLX5_REG_PUDE = 0x5009, 133 MLX5_REG_PPTB = 0x500B, 134 MLX5_REG_PBMC = 0x500C, 135 MLX5_REG_PMPE = 0x5010, 136 MLX5_REG_PELC = 0x500e, 137 MLX5_REG_PVLC = 0x500f, 138 MLX5_REG_PMLP = 0x5002, 139 MLX5_REG_NODE_DESC = 0x6001, 140 MLX5_REG_HOST_ENDIANNESS = 0x7004, 141 MLX5_REG_MCIA = 0x9014, 142 MLX5_REG_MPCNT = 0x9051, 143 }; 144 145 enum dbg_rsc_type { 146 MLX5_DBG_RSC_QP, 147 MLX5_DBG_RSC_EQ, 148 MLX5_DBG_RSC_CQ, 149 }; 150 151 enum { 152 MLX5_INTERFACE_PROTOCOL_IB = 0, 153 MLX5_INTERFACE_PROTOCOL_ETH = 1, 154 MLX5_INTERFACE_NUMBER = 2, 155 }; 156 157 struct mlx5_field_desc { 158 struct dentry *dent; 159 int i; 160 }; 161 162 struct mlx5_rsc_debug { 163 struct mlx5_core_dev *dev; 164 void *object; 165 enum dbg_rsc_type type; 166 struct dentry *root; 167 struct mlx5_field_desc fields[0]; 168 }; 169 170 enum mlx5_dev_event { 171 MLX5_DEV_EVENT_SYS_ERROR, 172 MLX5_DEV_EVENT_PORT_UP, 173 MLX5_DEV_EVENT_PORT_DOWN, 174 MLX5_DEV_EVENT_PORT_INITIALIZED, 175 MLX5_DEV_EVENT_LID_CHANGE, 176 MLX5_DEV_EVENT_PKEY_CHANGE, 177 MLX5_DEV_EVENT_GUID_CHANGE, 178 MLX5_DEV_EVENT_CLIENT_REREG, 179 MLX5_DEV_EVENT_VPORT_CHANGE, 180 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 181 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 182 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 183 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 184 }; 185 186 enum mlx5_port_status { 187 MLX5_PORT_UP = 1 << 0, 188 MLX5_PORT_DOWN = 1 << 1, 189 }; 190 191 enum mlx5_link_mode { 192 MLX5_1000BASE_CX_SGMII = 0, 193 MLX5_1000BASE_KX = 1, 194 MLX5_10GBASE_CX4 = 2, 195 MLX5_10GBASE_KX4 = 3, 196 MLX5_10GBASE_KR = 4, 197 MLX5_20GBASE_KR2 = 5, 198 MLX5_40GBASE_CR4 = 6, 199 MLX5_40GBASE_KR4 = 7, 200 MLX5_56GBASE_R4 = 8, 201 MLX5_10GBASE_CR = 12, 202 MLX5_10GBASE_SR = 13, 203 MLX5_10GBASE_ER = 14, 204 MLX5_40GBASE_SR4 = 15, 205 MLX5_40GBASE_LR4 = 16, 206 MLX5_100GBASE_CR4 = 20, 207 MLX5_100GBASE_SR4 = 21, 208 MLX5_100GBASE_KR4 = 22, 209 MLX5_100GBASE_LR4 = 23, 210 MLX5_100BASE_TX = 24, 211 MLX5_1000BASE_T = 25, 212 MLX5_10GBASE_T = 26, 213 MLX5_25GBASE_CR = 27, 214 MLX5_25GBASE_KR = 28, 215 MLX5_25GBASE_SR = 29, 216 MLX5_50GBASE_CR2 = 30, 217 MLX5_50GBASE_KR2 = 31, 218 MLX5_LINK_MODES_NUMBER, 219 }; 220 221 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 222 223 struct mlx5_uuar_info { 224 struct mlx5_uar *uars; 225 int num_uars; 226 int num_low_latency_uuars; 227 unsigned long *bitmap; 228 unsigned int *count; 229 struct mlx5_bf *bfs; 230 231 /* 232 * protect uuar allocation data structs 233 */ 234 struct mutex lock; 235 u32 ver; 236 }; 237 238 struct mlx5_bf { 239 void __iomem *reg; 240 void __iomem *regreg; 241 int buf_size; 242 struct mlx5_uar *uar; 243 unsigned long offset; 244 int need_lock; 245 /* protect blue flame buffer selection when needed 246 */ 247 spinlock_t lock; 248 249 /* serialize 64 bit writes when done as two 32 bit accesses 250 */ 251 spinlock_t lock32; 252 int uuarn; 253 }; 254 255 struct mlx5_cmd_first { 256 __be32 data[4]; 257 }; 258 259 struct mlx5_cmd_msg { 260 struct list_head list; 261 struct cache_ent *cache; 262 u32 len; 263 struct mlx5_cmd_first first; 264 struct mlx5_cmd_mailbox *next; 265 }; 266 267 struct mlx5_cmd_debug { 268 struct dentry *dbg_root; 269 struct dentry *dbg_in; 270 struct dentry *dbg_out; 271 struct dentry *dbg_outlen; 272 struct dentry *dbg_status; 273 struct dentry *dbg_run; 274 void *in_msg; 275 void *out_msg; 276 u8 status; 277 u16 inlen; 278 u16 outlen; 279 }; 280 281 struct cache_ent { 282 /* protect block chain allocations 283 */ 284 spinlock_t lock; 285 struct list_head head; 286 }; 287 288 struct cmd_msg_cache { 289 struct cache_ent large; 290 struct cache_ent med; 291 292 }; 293 294 struct mlx5_cmd_stats { 295 u64 sum; 296 u64 n; 297 struct dentry *root; 298 struct dentry *avg; 299 struct dentry *count; 300 /* protect command average calculations */ 301 spinlock_t lock; 302 }; 303 304 struct mlx5_cmd { 305 void *cmd_alloc_buf; 306 dma_addr_t alloc_dma; 307 int alloc_size; 308 void *cmd_buf; 309 dma_addr_t dma; 310 u16 cmdif_rev; 311 u8 log_sz; 312 u8 log_stride; 313 int max_reg_cmds; 314 int events; 315 u32 __iomem *vector; 316 317 /* protect command queue allocations 318 */ 319 spinlock_t alloc_lock; 320 321 /* protect token allocations 322 */ 323 spinlock_t token_lock; 324 u8 token; 325 unsigned long bitmask; 326 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 327 struct workqueue_struct *wq; 328 struct semaphore sem; 329 struct semaphore pages_sem; 330 int mode; 331 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 332 struct pci_pool *pool; 333 struct mlx5_cmd_debug dbg; 334 struct cmd_msg_cache cache; 335 int checksum_disabled; 336 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 337 int moving_to_polling; 338 }; 339 340 struct mlx5_port_caps { 341 int gid_table_len; 342 int pkey_table_len; 343 u8 ext_port_cap; 344 }; 345 346 struct mlx5_cmd_mailbox { 347 void *buf; 348 dma_addr_t dma; 349 struct mlx5_cmd_mailbox *next; 350 }; 351 352 struct mlx5_buf_list { 353 void *buf; 354 dma_addr_t map; 355 }; 356 357 struct mlx5_buf { 358 struct mlx5_buf_list direct; 359 struct mlx5_buf_list *page_list; 360 int nbufs; 361 int npages; 362 int size; 363 u8 page_shift; 364 }; 365 366 struct mlx5_eq { 367 struct mlx5_core_dev *dev; 368 __be32 __iomem *doorbell; 369 u32 cons_index; 370 struct mlx5_buf buf; 371 int size; 372 u8 irqn; 373 u8 eqn; 374 int nent; 375 u64 mask; 376 struct list_head list; 377 int index; 378 struct mlx5_rsc_debug *dbg; 379 }; 380 381 struct mlx5_core_psv { 382 u32 psv_idx; 383 struct psv_layout { 384 u32 pd; 385 u16 syndrome; 386 u16 reserved; 387 u16 bg; 388 u16 app_tag; 389 u32 ref_tag; 390 } psv; 391 }; 392 393 struct mlx5_core_sig_ctx { 394 struct mlx5_core_psv psv_memory; 395 struct mlx5_core_psv psv_wire; 396 #if (__FreeBSD_version >= 1100000) 397 struct ib_sig_err err_item; 398 #endif 399 bool sig_status_checked; 400 bool sig_err_exists; 401 u32 sigerr_count; 402 }; 403 404 struct mlx5_core_mr { 405 u64 iova; 406 u64 size; 407 u32 key; 408 u32 pd; 409 }; 410 411 enum mlx5_res_type { 412 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 413 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 414 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 415 MLX5_RES_SRQ = 3, 416 MLX5_RES_XSRQ = 4, 417 MLX5_RES_DCT = 5, 418 }; 419 420 struct mlx5_core_rsc_common { 421 enum mlx5_res_type res; 422 atomic_t refcount; 423 struct completion free; 424 }; 425 426 struct mlx5_core_srq { 427 struct mlx5_core_rsc_common common; /* must be first */ 428 u32 srqn; 429 int max; 430 int max_gs; 431 int max_avail_gather; 432 int wqe_shift; 433 void (*event)(struct mlx5_core_srq *, int); 434 atomic_t refcount; 435 struct completion free; 436 }; 437 438 struct mlx5_eq_table { 439 void __iomem *update_ci; 440 void __iomem *update_arm_ci; 441 struct list_head comp_eqs_list; 442 struct mlx5_eq pages_eq; 443 struct mlx5_eq async_eq; 444 struct mlx5_eq cmd_eq; 445 int num_comp_vectors; 446 /* protect EQs list 447 */ 448 spinlock_t lock; 449 }; 450 451 struct mlx5_uar { 452 u32 index; 453 void __iomem *bf_map; 454 void __iomem *map; 455 }; 456 457 458 struct mlx5_core_health { 459 struct mlx5_health_buffer __iomem *health; 460 __be32 __iomem *health_counter; 461 struct timer_list timer; 462 struct list_head list; 463 u32 prev; 464 int miss_counter; 465 }; 466 467 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 468 469 struct mlx5_cq_linear_array_entry { 470 spinlock_t lock; 471 struct mlx5_core_cq * volatile cq; 472 }; 473 474 struct mlx5_cq_table { 475 /* protect radix tree 476 */ 477 spinlock_t lock; 478 struct radix_tree_root tree; 479 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 480 }; 481 482 struct mlx5_qp_table { 483 /* protect radix tree 484 */ 485 spinlock_t lock; 486 struct radix_tree_root tree; 487 }; 488 489 struct mlx5_srq_table { 490 /* protect radix tree 491 */ 492 spinlock_t lock; 493 struct radix_tree_root tree; 494 }; 495 496 struct mlx5_mr_table { 497 /* protect radix tree 498 */ 499 spinlock_t lock; 500 struct radix_tree_root tree; 501 }; 502 503 struct mlx5_irq_info { 504 char name[MLX5_MAX_IRQ_NAME]; 505 }; 506 507 struct mlx5_priv { 508 char name[MLX5_MAX_NAME_LEN]; 509 struct mlx5_eq_table eq_table; 510 struct msix_entry *msix_arr; 511 struct mlx5_irq_info *irq_info; 512 struct mlx5_uuar_info uuari; 513 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 514 515 struct io_mapping *bf_mapping; 516 517 /* pages stuff */ 518 struct workqueue_struct *pg_wq; 519 struct rb_root page_root; 520 int fw_pages; 521 atomic_t reg_pages; 522 struct list_head free_list; 523 524 struct mlx5_core_health health; 525 526 struct mlx5_srq_table srq_table; 527 528 /* start: qp staff */ 529 struct mlx5_qp_table qp_table; 530 struct dentry *qp_debugfs; 531 struct dentry *eq_debugfs; 532 struct dentry *cq_debugfs; 533 struct dentry *cmdif_debugfs; 534 /* end: qp staff */ 535 536 /* start: cq staff */ 537 struct mlx5_cq_table cq_table; 538 /* end: cq staff */ 539 540 /* start: mr staff */ 541 struct mlx5_mr_table mr_table; 542 /* end: mr staff */ 543 544 /* start: alloc staff */ 545 int numa_node; 546 547 struct mutex pgdir_mutex; 548 struct list_head pgdir_list; 549 /* end: alloc staff */ 550 struct dentry *dbg_root; 551 552 /* protect mkey key part */ 553 spinlock_t mkey_lock; 554 u8 mkey_key; 555 556 struct list_head dev_list; 557 struct list_head ctx_list; 558 spinlock_t ctx_lock; 559 unsigned long pci_dev_data; 560 }; 561 562 enum mlx5_device_state { 563 MLX5_DEVICE_STATE_UP, 564 MLX5_DEVICE_STATE_INTERNAL_ERROR, 565 }; 566 567 struct mlx5_special_contexts { 568 int resd_lkey; 569 }; 570 571 struct mlx5_core_dev { 572 struct pci_dev *pdev; 573 char board_id[MLX5_BOARD_ID_LEN]; 574 struct mlx5_cmd cmd; 575 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 576 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 577 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 578 struct mlx5_init_seg __iomem *iseg; 579 enum mlx5_device_state state; 580 void (*event) (struct mlx5_core_dev *dev, 581 enum mlx5_dev_event event, 582 unsigned long param); 583 struct mlx5_priv priv; 584 struct mlx5_profile *profile; 585 atomic_t num_qps; 586 u32 issi; 587 struct mlx5_special_contexts special_contexts; 588 unsigned int module_status[MLX5_MAX_PORTS]; 589 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 590 }; 591 592 enum { 593 MLX5_WOL_DISABLE = 0, 594 MLX5_WOL_SECURED_MAGIC = 1 << 1, 595 MLX5_WOL_MAGIC = 1 << 2, 596 MLX5_WOL_ARP = 1 << 3, 597 MLX5_WOL_BROADCAST = 1 << 4, 598 MLX5_WOL_MULTICAST = 1 << 5, 599 MLX5_WOL_UNICAST = 1 << 6, 600 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 601 }; 602 603 struct mlx5_db { 604 __be32 *db; 605 union { 606 struct mlx5_db_pgdir *pgdir; 607 struct mlx5_ib_user_db_page *user_page; 608 } u; 609 dma_addr_t dma; 610 int index; 611 }; 612 613 struct mlx5_net_counters { 614 u64 packets; 615 u64 octets; 616 }; 617 618 struct mlx5_ptys_reg { 619 u8 an_dis_admin; 620 u8 an_dis_ap; 621 u8 local_port; 622 u8 proto_mask; 623 u32 eth_proto_cap; 624 u16 ib_link_width_cap; 625 u16 ib_proto_cap; 626 u32 eth_proto_admin; 627 u16 ib_link_width_admin; 628 u16 ib_proto_admin; 629 u32 eth_proto_oper; 630 u16 ib_link_width_oper; 631 u16 ib_proto_oper; 632 u32 eth_proto_lp_advertise; 633 }; 634 635 struct mlx5_pvlc_reg { 636 u8 local_port; 637 u8 vl_hw_cap; 638 u8 vl_admin; 639 u8 vl_operational; 640 }; 641 642 struct mlx5_pmtu_reg { 643 u8 local_port; 644 u16 max_mtu; 645 u16 admin_mtu; 646 u16 oper_mtu; 647 }; 648 649 struct mlx5_vport_counters { 650 struct mlx5_net_counters received_errors; 651 struct mlx5_net_counters transmit_errors; 652 struct mlx5_net_counters received_ib_unicast; 653 struct mlx5_net_counters transmitted_ib_unicast; 654 struct mlx5_net_counters received_ib_multicast; 655 struct mlx5_net_counters transmitted_ib_multicast; 656 struct mlx5_net_counters received_eth_broadcast; 657 struct mlx5_net_counters transmitted_eth_broadcast; 658 struct mlx5_net_counters received_eth_unicast; 659 struct mlx5_net_counters transmitted_eth_unicast; 660 struct mlx5_net_counters received_eth_multicast; 661 struct mlx5_net_counters transmitted_eth_multicast; 662 }; 663 664 enum { 665 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 666 }; 667 668 struct mlx5_core_dct { 669 struct mlx5_core_rsc_common common; /* must be first */ 670 void (*event)(struct mlx5_core_dct *, int); 671 int dctn; 672 struct completion drained; 673 struct mlx5_rsc_debug *dbg; 674 int pid; 675 }; 676 677 enum { 678 MLX5_COMP_EQ_SIZE = 1024, 679 }; 680 681 enum { 682 MLX5_PTYS_IB = 1 << 0, 683 MLX5_PTYS_EN = 1 << 2, 684 }; 685 686 struct mlx5_db_pgdir { 687 struct list_head list; 688 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 689 __be32 *db_page; 690 dma_addr_t db_dma; 691 }; 692 693 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 694 695 struct mlx5_cmd_work_ent { 696 struct mlx5_cmd_msg *in; 697 struct mlx5_cmd_msg *out; 698 void *uout; 699 int uout_size; 700 mlx5_cmd_cbk_t callback; 701 void *context; 702 int idx; 703 struct completion done; 704 struct mlx5_cmd *cmd; 705 struct work_struct work; 706 struct mlx5_cmd_layout *lay; 707 int ret; 708 int page_queue; 709 u8 status; 710 u8 token; 711 u64 ts1; 712 u64 ts2; 713 u16 op; 714 }; 715 716 struct mlx5_pas { 717 u64 pa; 718 u8 log_sz; 719 }; 720 721 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 722 { 723 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1)) 724 return buf->direct.buf + offset; 725 else 726 return buf->page_list[offset >> PAGE_SHIFT].buf + 727 (offset & (PAGE_SIZE - 1)); 728 } 729 730 731 extern struct workqueue_struct *mlx5_core_wq; 732 733 #define STRUCT_FIELD(header, field) \ 734 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 735 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 736 737 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 738 { 739 return pci_get_drvdata(pdev); 740 } 741 742 extern struct dentry *mlx5_debugfs_root; 743 744 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 745 { 746 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 747 } 748 749 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 750 { 751 return ioread32be(&dev->iseg->fw_rev) >> 16; 752 } 753 754 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 755 { 756 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 757 } 758 759 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 760 { 761 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 762 } 763 764 static inline int mlx5_get_gid_table_len(u16 param) 765 { 766 if (param > 4) { 767 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 768 return 0; 769 } 770 771 return 8 * (1 << param); 772 } 773 774 static inline void *mlx5_vzalloc(unsigned long size) 775 { 776 void *rtn; 777 778 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 779 return rtn; 780 } 781 782 static inline void *mlx5_vmalloc(unsigned long size) 783 { 784 void *rtn; 785 786 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 787 if (!rtn) 788 rtn = vmalloc(size); 789 return rtn; 790 } 791 792 int mlx5_cmd_init(struct mlx5_core_dev *dev); 793 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 794 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 795 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 796 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 797 int mlx5_cmd_status_to_err_v2(void *ptr); 798 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 799 enum mlx5_cap_mode cap_mode); 800 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 801 int out_size); 802 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 803 void *out, int out_size, mlx5_cmd_cbk_t callback, 804 void *context); 805 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 806 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 807 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 808 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 809 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 810 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 811 void mlx5_health_cleanup(void); 812 void __init mlx5_health_init(void); 813 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 814 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 815 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, int max_direct, 816 struct mlx5_buf *buf, int node); 817 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 818 struct mlx5_buf *buf); 819 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 820 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 821 struct mlx5_create_srq_mbox_in *in, int inlen, 822 int is_xrc); 823 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 824 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 825 struct mlx5_query_srq_mbox_out *out); 826 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 827 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 828 u16 lwm, int is_srq); 829 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 830 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 831 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 832 struct mlx5_create_mkey_mbox_in *in, int inlen, 833 mlx5_cmd_cbk_t callback, void *context, 834 struct mlx5_create_mkey_mbox_out *out); 835 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 836 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 837 struct mlx5_query_mkey_mbox_out *out, int outlen); 838 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 839 u32 *mkey); 840 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 841 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 842 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, 843 u16 opmod, u8 port); 844 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 845 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 846 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 847 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 848 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 849 s32 npages); 850 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 851 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 852 void mlx5_register_debugfs(void); 853 void mlx5_unregister_debugfs(void); 854 int mlx5_eq_init(struct mlx5_core_dev *dev); 855 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 856 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 857 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 858 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 859 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 860 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 861 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); 862 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 863 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 864 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 865 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 866 int mlx5_start_eqs(struct mlx5_core_dev *dev); 867 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 868 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 869 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 870 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 871 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 872 u64 addr); 873 874 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 875 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 876 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 877 int size_in, void *data_out, int size_out, 878 u16 reg_num, int arg, int write); 879 880 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 881 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 882 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 883 int ptys_size, int proto_mask); 884 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 885 u32 *proto_cap, int proto_mask); 886 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, 887 u8 *an_disable_cap, u8 *an_disable_status); 888 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable, 889 u32 eth_proto_admin, int proto_mask); 890 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 891 u32 *proto_admin, int proto_mask); 892 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 893 int proto_mask); 894 int mlx5_set_port_status(struct mlx5_core_dev *dev, 895 enum mlx5_port_status status); 896 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 897 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 898 enum mlx5_port_status *status); 899 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port, 900 u32 rx_pause, u32 tx_pause); 901 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 902 u32 *rx_pause, u32 *tx_pause); 903 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); 904 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx); 905 906 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 907 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 908 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 909 910 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 911 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 912 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 913 int device_addr, int size, int module_num, u32 *data, 914 int *size_read); 915 916 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 917 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 918 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 919 struct mlx5_query_eq_mbox_out *out, int outlen); 920 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 921 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 922 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 923 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 924 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 925 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 926 int node); 927 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 928 929 const char *mlx5_command_str(int command); 930 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 931 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 932 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 933 int npsvs, u32 *sig_index); 934 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 935 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 936 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 937 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 938 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 939 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 940 struct mlx5_pvlc_reg *pvlc, int write); 941 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 942 struct mlx5_ptys_reg *ptys, int write); 943 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 944 struct mlx5_pmtu_reg *pmtu, int write); 945 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 946 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 947 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 948 int priority, int *is_enable); 949 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 950 int priority, int enable); 951 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 952 void *out, int out_size); 953 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 954 void *in, int in_size); 955 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 956 void *out, int out_size); 957 int mlx5_set_diagnostics(struct mlx5_core_dev *mdev, void *in, int in_size); 958 int mlx5_query_diagnostics(struct mlx5_core_dev *mdev, u8 num_of_samples, 959 u16 sample_index, void *out, int out_size); 960 static inline u32 mlx5_mkey_to_idx(u32 mkey) 961 { 962 return mkey >> 8; 963 } 964 965 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 966 { 967 return mkey_idx << 8; 968 } 969 970 static inline u8 mlx5_mkey_variant(u32 mkey) 971 { 972 return mkey & 0xff; 973 } 974 975 enum { 976 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 977 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 978 }; 979 980 enum { 981 MAX_MR_CACHE_ENTRIES = 15, 982 }; 983 984 struct mlx5_interface { 985 void * (*add)(struct mlx5_core_dev *dev); 986 void (*remove)(struct mlx5_core_dev *dev, void *context); 987 void (*event)(struct mlx5_core_dev *dev, void *context, 988 enum mlx5_dev_event event, unsigned long param); 989 void * (*get_dev)(void *context); 990 int protocol; 991 struct list_head list; 992 }; 993 994 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 995 int mlx5_register_interface(struct mlx5_interface *intf); 996 void mlx5_unregister_interface(struct mlx5_interface *intf); 997 998 struct mlx5_profile { 999 u64 mask; 1000 u8 log_max_qp; 1001 struct { 1002 int size; 1003 int limit; 1004 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1005 }; 1006 1007 enum { 1008 MLX5_PCI_DEV_IS_VF = 1 << 0, 1009 }; 1010 1011 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1012 { 1013 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1014 } 1015 1016 #define MLX5_EEPROM_MAX_BYTES 32 1017 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 1018 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 1019 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 1020 #endif /* MLX5_DRIVER_H */ 1021