1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include <linux/kernel.h> 32 #include <linux/completion.h> 33 #include <linux/pci.h> 34 #include <linux/cache.h> 35 #include <linux/rbtree.h> 36 #include <linux/if_ether.h> 37 #include <linux/semaphore.h> 38 #include <linux/slab.h> 39 #include <linux/vmalloc.h> 40 #include <linux/radix-tree.h> 41 42 #include <dev/mlx5/device.h> 43 #include <dev/mlx5/doorbell.h> 44 #include <dev/mlx5/srq.h> 45 46 #define MLX5_QCOUNTER_SETS_NETDEV 64 47 #define MLX5_MAX_NUMBER_OF_VFS 128 48 49 enum { 50 MLX5_BOARD_ID_LEN = 64, 51 MLX5_MAX_NAME_LEN = 16, 52 }; 53 54 enum { 55 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 56 MLX5_CMD_WQ_MAX_NAME = 32, 57 }; 58 59 enum { 60 CMD_OWNER_SW = 0x0, 61 CMD_OWNER_HW = 0x1, 62 CMD_STATUS_SUCCESS = 0, 63 }; 64 65 enum mlx5_sqp_t { 66 MLX5_SQP_SMI = 0, 67 MLX5_SQP_GSI = 1, 68 MLX5_SQP_IEEE_1588 = 2, 69 MLX5_SQP_SNIFFER = 3, 70 MLX5_SQP_SYNC_UMR = 4, 71 }; 72 73 enum { 74 MLX5_MAX_PORTS = 2, 75 }; 76 77 enum { 78 MLX5_EQ_VEC_PAGES = 0, 79 MLX5_EQ_VEC_CMD = 1, 80 MLX5_EQ_VEC_ASYNC = 2, 81 MLX5_EQ_VEC_COMP_BASE, 82 }; 83 84 enum { 85 MLX5_MAX_IRQ_NAME = 32 86 }; 87 88 enum { 89 MLX5_ATOMIC_MODE_OFF = 16, 90 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 91 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 99 }; 100 101 enum { 102 MLX5_ATOMIC_MODE_DCT_OFF = 20, 103 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 104 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 112 }; 113 114 enum { 115 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 116 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 117 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 118 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 119 }; 120 121 enum { 122 MLX5_REG_QETCR = 0x4005, 123 MLX5_REG_QPDP = 0x4007, 124 MLX5_REG_QTCT = 0x400A, 125 MLX5_REG_QHLL = 0x4016, 126 MLX5_REG_DCBX_PARAM = 0x4020, 127 MLX5_REG_DCBX_APP = 0x4021, 128 MLX5_REG_PCAP = 0x5001, 129 MLX5_REG_PMTU = 0x5003, 130 MLX5_REG_PTYS = 0x5004, 131 MLX5_REG_PAOS = 0x5006, 132 MLX5_REG_PFCC = 0x5007, 133 MLX5_REG_PPCNT = 0x5008, 134 MLX5_REG_PMAOS = 0x5012, 135 MLX5_REG_PUDE = 0x5009, 136 MLX5_REG_PPTB = 0x500B, 137 MLX5_REG_PBMC = 0x500C, 138 MLX5_REG_PMPE = 0x5010, 139 MLX5_REG_PELC = 0x500e, 140 MLX5_REG_PVLC = 0x500f, 141 MLX5_REG_PMLP = 0x5002, 142 MLX5_REG_NODE_DESC = 0x6001, 143 MLX5_REG_HOST_ENDIANNESS = 0x7004, 144 MLX5_REG_MCIA = 0x9014, 145 MLX5_REG_MPCNT = 0x9051, 146 }; 147 148 enum dbg_rsc_type { 149 MLX5_DBG_RSC_QP, 150 MLX5_DBG_RSC_EQ, 151 MLX5_DBG_RSC_CQ, 152 }; 153 154 enum { 155 MLX5_INTERFACE_PROTOCOL_IB = 0, 156 MLX5_INTERFACE_PROTOCOL_ETH = 1, 157 MLX5_INTERFACE_NUMBER = 2, 158 }; 159 160 struct mlx5_field_desc { 161 struct dentry *dent; 162 int i; 163 }; 164 165 struct mlx5_rsc_debug { 166 struct mlx5_core_dev *dev; 167 void *object; 168 enum dbg_rsc_type type; 169 struct dentry *root; 170 struct mlx5_field_desc fields[0]; 171 }; 172 173 enum mlx5_dev_event { 174 MLX5_DEV_EVENT_SYS_ERROR, 175 MLX5_DEV_EVENT_PORT_UP, 176 MLX5_DEV_EVENT_PORT_DOWN, 177 MLX5_DEV_EVENT_PORT_INITIALIZED, 178 MLX5_DEV_EVENT_LID_CHANGE, 179 MLX5_DEV_EVENT_PKEY_CHANGE, 180 MLX5_DEV_EVENT_GUID_CHANGE, 181 MLX5_DEV_EVENT_CLIENT_REREG, 182 MLX5_DEV_EVENT_VPORT_CHANGE, 183 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 184 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 185 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 186 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 187 }; 188 189 enum mlx5_port_status { 190 MLX5_PORT_UP = 1 << 0, 191 MLX5_PORT_DOWN = 1 << 1, 192 }; 193 194 enum mlx5_link_mode { 195 MLX5_1000BASE_CX_SGMII = 0, 196 MLX5_1000BASE_KX = 1, 197 MLX5_10GBASE_CX4 = 2, 198 MLX5_10GBASE_KX4 = 3, 199 MLX5_10GBASE_KR = 4, 200 MLX5_20GBASE_KR2 = 5, 201 MLX5_40GBASE_CR4 = 6, 202 MLX5_40GBASE_KR4 = 7, 203 MLX5_56GBASE_R4 = 8, 204 MLX5_10GBASE_CR = 12, 205 MLX5_10GBASE_SR = 13, 206 MLX5_10GBASE_ER = 14, 207 MLX5_40GBASE_SR4 = 15, 208 MLX5_40GBASE_LR4 = 16, 209 MLX5_100GBASE_CR4 = 20, 210 MLX5_100GBASE_SR4 = 21, 211 MLX5_100GBASE_KR4 = 22, 212 MLX5_100GBASE_LR4 = 23, 213 MLX5_100BASE_TX = 24, 214 MLX5_1000BASE_T = 25, 215 MLX5_10GBASE_T = 26, 216 MLX5_25GBASE_CR = 27, 217 MLX5_25GBASE_KR = 28, 218 MLX5_25GBASE_SR = 29, 219 MLX5_50GBASE_CR2 = 30, 220 MLX5_50GBASE_KR2 = 31, 221 MLX5_LINK_MODES_NUMBER, 222 }; 223 224 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 225 226 struct mlx5_uuar_info { 227 struct mlx5_uar *uars; 228 int num_uars; 229 int num_low_latency_uuars; 230 unsigned long *bitmap; 231 unsigned int *count; 232 struct mlx5_bf *bfs; 233 234 /* 235 * protect uuar allocation data structs 236 */ 237 struct mutex lock; 238 u32 ver; 239 }; 240 241 struct mlx5_bf { 242 void __iomem *reg; 243 void __iomem *regreg; 244 int buf_size; 245 struct mlx5_uar *uar; 246 unsigned long offset; 247 int need_lock; 248 /* protect blue flame buffer selection when needed 249 */ 250 spinlock_t lock; 251 252 /* serialize 64 bit writes when done as two 32 bit accesses 253 */ 254 spinlock_t lock32; 255 int uuarn; 256 }; 257 258 struct mlx5_cmd_first { 259 __be32 data[4]; 260 }; 261 262 struct cache_ent; 263 struct mlx5_fw_page { 264 union { 265 struct rb_node rb_node; 266 struct list_head list; 267 }; 268 struct mlx5_cmd_first first; 269 struct mlx5_core_dev *dev; 270 bus_dmamap_t dma_map; 271 bus_addr_t dma_addr; 272 void *virt_addr; 273 struct cache_ent *cache; 274 u32 numpages; 275 u16 load_done; 276 #define MLX5_LOAD_ST_NONE 0 277 #define MLX5_LOAD_ST_SUCCESS 1 278 #define MLX5_LOAD_ST_FAILURE 2 279 u16 func_id; 280 }; 281 #define mlx5_cmd_msg mlx5_fw_page 282 283 struct mlx5_cmd_debug { 284 struct dentry *dbg_root; 285 struct dentry *dbg_in; 286 struct dentry *dbg_out; 287 struct dentry *dbg_outlen; 288 struct dentry *dbg_status; 289 struct dentry *dbg_run; 290 void *in_msg; 291 void *out_msg; 292 u8 status; 293 u16 inlen; 294 u16 outlen; 295 }; 296 297 struct cache_ent { 298 /* protect block chain allocations 299 */ 300 spinlock_t lock; 301 struct list_head head; 302 }; 303 304 struct cmd_msg_cache { 305 struct cache_ent large; 306 struct cache_ent med; 307 308 }; 309 310 struct mlx5_traffic_counter { 311 u64 packets; 312 u64 octets; 313 }; 314 315 struct mlx5_cmd_stats { 316 u64 sum; 317 u64 n; 318 struct dentry *root; 319 struct dentry *avg; 320 struct dentry *count; 321 /* protect command average calculations */ 322 spinlock_t lock; 323 }; 324 325 struct mlx5_cmd { 326 struct mlx5_fw_page *cmd_page; 327 bus_dma_tag_t dma_tag; 328 struct sx dma_sx; 329 struct mtx dma_mtx; 330 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 331 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 332 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 333 struct cv dma_cv; 334 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 335 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 336 void *cmd_buf; 337 dma_addr_t dma; 338 u16 cmdif_rev; 339 u8 log_sz; 340 u8 log_stride; 341 int max_reg_cmds; 342 int events; 343 u32 __iomem *vector; 344 345 /* protect command queue allocations 346 */ 347 spinlock_t alloc_lock; 348 349 /* protect token allocations 350 */ 351 spinlock_t token_lock; 352 u8 token; 353 unsigned long bitmask; 354 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 355 struct workqueue_struct *wq; 356 struct semaphore sem; 357 struct semaphore pages_sem; 358 int mode; 359 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 360 struct mlx5_cmd_debug dbg; 361 struct cmd_msg_cache cache; 362 int checksum_disabled; 363 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 364 int moving_to_polling; 365 }; 366 367 struct mlx5_port_caps { 368 int gid_table_len; 369 int pkey_table_len; 370 u8 ext_port_cap; 371 }; 372 373 struct mlx5_buf { 374 bus_dma_tag_t dma_tag; 375 bus_dmamap_t dma_map; 376 struct mlx5_core_dev *dev; 377 struct { 378 void *buf; 379 } direct; 380 u64 *page_list; 381 int npages; 382 int size; 383 u8 page_shift; 384 u8 load_done; 385 }; 386 387 struct mlx5_eq { 388 struct mlx5_core_dev *dev; 389 __be32 __iomem *doorbell; 390 u32 cons_index; 391 struct mlx5_buf buf; 392 int size; 393 u8 irqn; 394 u8 eqn; 395 int nent; 396 u64 mask; 397 struct list_head list; 398 int index; 399 struct mlx5_rsc_debug *dbg; 400 }; 401 402 struct mlx5_core_psv { 403 u32 psv_idx; 404 struct psv_layout { 405 u32 pd; 406 u16 syndrome; 407 u16 reserved; 408 u16 bg; 409 u16 app_tag; 410 u32 ref_tag; 411 } psv; 412 }; 413 414 struct mlx5_core_sig_ctx { 415 struct mlx5_core_psv psv_memory; 416 struct mlx5_core_psv psv_wire; 417 #if (__FreeBSD_version >= 1100000) 418 struct ib_sig_err err_item; 419 #endif 420 bool sig_status_checked; 421 bool sig_err_exists; 422 u32 sigerr_count; 423 }; 424 425 struct mlx5_core_mr { 426 u64 iova; 427 u64 size; 428 u32 key; 429 u32 pd; 430 }; 431 432 enum mlx5_res_type { 433 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 434 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 435 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 436 MLX5_RES_SRQ = 3, 437 MLX5_RES_XSRQ = 4, 438 MLX5_RES_DCT = 5, 439 }; 440 441 struct mlx5_core_rsc_common { 442 enum mlx5_res_type res; 443 atomic_t refcount; 444 struct completion free; 445 }; 446 447 struct mlx5_core_srq { 448 struct mlx5_core_rsc_common common; /* must be first */ 449 u32 srqn; 450 int max; 451 int max_gs; 452 int max_avail_gather; 453 int wqe_shift; 454 void (*event)(struct mlx5_core_srq *, int); 455 atomic_t refcount; 456 struct completion free; 457 }; 458 459 struct mlx5_eq_table { 460 void __iomem *update_ci; 461 void __iomem *update_arm_ci; 462 struct list_head comp_eqs_list; 463 struct mlx5_eq pages_eq; 464 struct mlx5_eq async_eq; 465 struct mlx5_eq cmd_eq; 466 int num_comp_vectors; 467 /* protect EQs list 468 */ 469 spinlock_t lock; 470 }; 471 472 struct mlx5_uar { 473 u32 index; 474 void __iomem *bf_map; 475 void __iomem *map; 476 }; 477 478 479 struct mlx5_core_health { 480 struct mlx5_health_buffer __iomem *health; 481 __be32 __iomem *health_counter; 482 struct timer_list timer; 483 u32 prev; 484 int miss_counter; 485 bool sick; 486 /* wq spinlock to synchronize draining */ 487 spinlock_t wq_lock; 488 struct workqueue_struct *wq; 489 unsigned long flags; 490 struct work_struct work; 491 }; 492 493 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 494 495 struct mlx5_cq_linear_array_entry { 496 spinlock_t lock; 497 struct mlx5_core_cq * volatile cq; 498 }; 499 500 struct mlx5_cq_table { 501 /* protect radix tree 502 */ 503 spinlock_t lock; 504 struct radix_tree_root tree; 505 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 506 }; 507 508 struct mlx5_qp_table { 509 /* protect radix tree 510 */ 511 spinlock_t lock; 512 struct radix_tree_root tree; 513 }; 514 515 struct mlx5_srq_table { 516 /* protect radix tree 517 */ 518 spinlock_t lock; 519 struct radix_tree_root tree; 520 }; 521 522 struct mlx5_mr_table { 523 /* protect radix tree 524 */ 525 spinlock_t lock; 526 struct radix_tree_root tree; 527 }; 528 529 struct mlx5_irq_info { 530 char name[MLX5_MAX_IRQ_NAME]; 531 }; 532 533 struct mlx5_priv { 534 char name[MLX5_MAX_NAME_LEN]; 535 struct mlx5_eq_table eq_table; 536 struct msix_entry *msix_arr; 537 struct mlx5_irq_info *irq_info; 538 struct mlx5_uuar_info uuari; 539 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 540 541 struct io_mapping *bf_mapping; 542 543 /* pages stuff */ 544 struct workqueue_struct *pg_wq; 545 struct rb_root page_root; 546 s64 fw_pages; 547 atomic_t reg_pages; 548 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 549 struct mlx5_core_health health; 550 551 struct mlx5_srq_table srq_table; 552 553 /* start: qp staff */ 554 struct mlx5_qp_table qp_table; 555 struct dentry *qp_debugfs; 556 struct dentry *eq_debugfs; 557 struct dentry *cq_debugfs; 558 struct dentry *cmdif_debugfs; 559 /* end: qp staff */ 560 561 /* start: cq staff */ 562 struct mlx5_cq_table cq_table; 563 /* end: cq staff */ 564 565 /* start: mr staff */ 566 struct mlx5_mr_table mr_table; 567 /* end: mr staff */ 568 569 /* start: alloc staff */ 570 int numa_node; 571 572 struct mutex pgdir_mutex; 573 struct list_head pgdir_list; 574 /* end: alloc staff */ 575 struct dentry *dbg_root; 576 577 /* protect mkey key part */ 578 spinlock_t mkey_lock; 579 u8 mkey_key; 580 581 struct list_head dev_list; 582 struct list_head ctx_list; 583 spinlock_t ctx_lock; 584 unsigned long pci_dev_data; 585 }; 586 587 enum mlx5_device_state { 588 MLX5_DEVICE_STATE_UP, 589 MLX5_DEVICE_STATE_INTERNAL_ERROR, 590 }; 591 592 enum mlx5_interface_state { 593 MLX5_INTERFACE_STATE_DOWN = BIT(0), 594 MLX5_INTERFACE_STATE_UP = BIT(1), 595 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), 596 }; 597 598 enum mlx5_pci_status { 599 MLX5_PCI_STATUS_DISABLED, 600 MLX5_PCI_STATUS_ENABLED, 601 }; 602 603 struct mlx5_special_contexts { 604 int resd_lkey; 605 }; 606 607 struct mlx5_flow_root_namespace; 608 struct mlx5_core_dev { 609 struct pci_dev *pdev; 610 /* sync pci state */ 611 struct mutex pci_status_mutex; 612 enum mlx5_pci_status pci_status; 613 char board_id[MLX5_BOARD_ID_LEN]; 614 struct mlx5_cmd cmd; 615 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 616 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 617 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 618 phys_addr_t iseg_base; 619 struct mlx5_init_seg __iomem *iseg; 620 enum mlx5_device_state state; 621 /* sync interface state */ 622 struct mutex intf_state_mutex; 623 unsigned long intf_state; 624 void (*event) (struct mlx5_core_dev *dev, 625 enum mlx5_dev_event event, 626 unsigned long param); 627 struct mlx5_priv priv; 628 struct mlx5_profile *profile; 629 atomic_t num_qps; 630 u32 issi; 631 struct mlx5_special_contexts special_contexts; 632 unsigned int module_status[MLX5_MAX_PORTS]; 633 struct mlx5_flow_root_namespace *root_ns; 634 struct mlx5_flow_root_namespace *fdb_root_ns; 635 struct mlx5_flow_root_namespace *esw_egress_root_ns; 636 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 637 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 638 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 639 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 640 }; 641 642 enum { 643 MLX5_WOL_DISABLE = 0, 644 MLX5_WOL_SECURED_MAGIC = 1 << 1, 645 MLX5_WOL_MAGIC = 1 << 2, 646 MLX5_WOL_ARP = 1 << 3, 647 MLX5_WOL_BROADCAST = 1 << 4, 648 MLX5_WOL_MULTICAST = 1 << 5, 649 MLX5_WOL_UNICAST = 1 << 6, 650 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 651 }; 652 653 struct mlx5_db { 654 __be32 *db; 655 union { 656 struct mlx5_db_pgdir *pgdir; 657 struct mlx5_ib_user_db_page *user_page; 658 } u; 659 dma_addr_t dma; 660 int index; 661 }; 662 663 struct mlx5_net_counters { 664 u64 packets; 665 u64 octets; 666 }; 667 668 struct mlx5_ptys_reg { 669 u8 an_dis_admin; 670 u8 an_dis_ap; 671 u8 local_port; 672 u8 proto_mask; 673 u32 eth_proto_cap; 674 u16 ib_link_width_cap; 675 u16 ib_proto_cap; 676 u32 eth_proto_admin; 677 u16 ib_link_width_admin; 678 u16 ib_proto_admin; 679 u32 eth_proto_oper; 680 u16 ib_link_width_oper; 681 u16 ib_proto_oper; 682 u32 eth_proto_lp_advertise; 683 }; 684 685 struct mlx5_pvlc_reg { 686 u8 local_port; 687 u8 vl_hw_cap; 688 u8 vl_admin; 689 u8 vl_operational; 690 }; 691 692 struct mlx5_pmtu_reg { 693 u8 local_port; 694 u16 max_mtu; 695 u16 admin_mtu; 696 u16 oper_mtu; 697 }; 698 699 struct mlx5_vport_counters { 700 struct mlx5_net_counters received_errors; 701 struct mlx5_net_counters transmit_errors; 702 struct mlx5_net_counters received_ib_unicast; 703 struct mlx5_net_counters transmitted_ib_unicast; 704 struct mlx5_net_counters received_ib_multicast; 705 struct mlx5_net_counters transmitted_ib_multicast; 706 struct mlx5_net_counters received_eth_broadcast; 707 struct mlx5_net_counters transmitted_eth_broadcast; 708 struct mlx5_net_counters received_eth_unicast; 709 struct mlx5_net_counters transmitted_eth_unicast; 710 struct mlx5_net_counters received_eth_multicast; 711 struct mlx5_net_counters transmitted_eth_multicast; 712 }; 713 714 enum { 715 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 716 }; 717 718 struct mlx5_core_dct { 719 struct mlx5_core_rsc_common common; /* must be first */ 720 void (*event)(struct mlx5_core_dct *, int); 721 int dctn; 722 struct completion drained; 723 struct mlx5_rsc_debug *dbg; 724 int pid; 725 }; 726 727 enum { 728 MLX5_COMP_EQ_SIZE = 1024, 729 }; 730 731 enum { 732 MLX5_PTYS_IB = 1 << 0, 733 MLX5_PTYS_EN = 1 << 2, 734 }; 735 736 struct mlx5_db_pgdir { 737 struct list_head list; 738 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 739 struct mlx5_fw_page *fw_page; 740 __be32 *db_page; 741 dma_addr_t db_dma; 742 }; 743 744 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 745 746 struct mlx5_cmd_work_ent { 747 struct mlx5_cmd_msg *in; 748 struct mlx5_cmd_msg *out; 749 int uin_size; 750 void *uout; 751 int uout_size; 752 mlx5_cmd_cbk_t callback; 753 struct delayed_work cb_timeout_work; 754 void *context; 755 int idx; 756 struct completion done; 757 struct mlx5_cmd *cmd; 758 struct work_struct work; 759 struct mlx5_cmd_layout *lay; 760 int ret; 761 int page_queue; 762 u8 status; 763 u8 token; 764 u64 ts1; 765 u64 ts2; 766 u16 op; 767 u8 busy; 768 }; 769 770 struct mlx5_pas { 771 u64 pa; 772 u8 log_sz; 773 }; 774 775 enum port_state_policy { 776 MLX5_POLICY_DOWN = 0, 777 MLX5_POLICY_UP = 1, 778 MLX5_POLICY_FOLLOW = 2, 779 MLX5_POLICY_INVALID = 0xffffffff 780 }; 781 782 static inline void * 783 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 784 { 785 return ((char *)buf->direct.buf + offset); 786 } 787 788 789 extern struct workqueue_struct *mlx5_core_wq; 790 791 #define STRUCT_FIELD(header, field) \ 792 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 793 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 794 795 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 796 { 797 return pci_get_drvdata(pdev); 798 } 799 800 extern struct dentry *mlx5_debugfs_root; 801 802 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 803 { 804 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 805 } 806 807 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 808 { 809 return ioread32be(&dev->iseg->fw_rev) >> 16; 810 } 811 812 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 813 { 814 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 815 } 816 817 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 818 { 819 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 820 } 821 822 static inline int mlx5_get_gid_table_len(u16 param) 823 { 824 if (param > 4) { 825 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 826 return 0; 827 } 828 829 return 8 * (1 << param); 830 } 831 832 static inline void *mlx5_vzalloc(unsigned long size) 833 { 834 void *rtn; 835 836 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 837 return rtn; 838 } 839 840 static inline void *mlx5_vmalloc(unsigned long size) 841 { 842 void *rtn; 843 844 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 845 if (!rtn) 846 rtn = vmalloc(size); 847 return rtn; 848 } 849 850 static inline u32 mlx5_base_mkey(const u32 key) 851 { 852 return key & 0xffffff00u; 853 } 854 855 void mlx5_enter_error_state(struct mlx5_core_dev *dev); 856 int mlx5_cmd_init(struct mlx5_core_dev *dev); 857 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 858 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 859 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 860 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 861 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 862 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 863 int out_size); 864 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 865 void *out, int out_size, mlx5_cmd_cbk_t callback, 866 void *context); 867 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 868 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 869 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 870 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 871 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 872 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 873 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 874 int mlx5_health_init(struct mlx5_core_dev *dev); 875 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 876 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 877 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 878 879 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 880 mlx5_buf_alloc(dev, size, direct, buf) 881 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 882 struct mlx5_buf *buf); 883 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 884 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 885 struct mlx5_srq_attr *in); 886 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 887 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 888 struct mlx5_srq_attr *out); 889 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 890 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 891 u16 lwm, int is_srq); 892 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 893 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 894 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 895 struct mlx5_core_mr *mkey, 896 u32 *in, int inlen, 897 u32 *out, int outlen, 898 mlx5_cmd_cbk_t callback, void *context); 899 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 900 struct mlx5_core_mr *mr, 901 u32 *in, int inlen); 902 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 903 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 904 u32 *out, int outlen); 905 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 906 u32 *mkey); 907 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 908 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 909 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 910 u16 opmod, u8 port); 911 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 912 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 913 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 914 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 915 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 916 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 917 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 918 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 919 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 920 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 921 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 922 s32 npages); 923 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 924 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 925 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 926 void mlx5_register_debugfs(void); 927 void mlx5_unregister_debugfs(void); 928 int mlx5_eq_init(struct mlx5_core_dev *dev); 929 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 930 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 931 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 932 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 933 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 934 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 935 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector); 936 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 937 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 938 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 939 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 940 int mlx5_start_eqs(struct mlx5_core_dev *dev); 941 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 942 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 943 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 944 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 945 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 946 u64 addr); 947 948 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 949 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 950 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 951 int size_in, void *data_out, int size_out, 952 u16 reg_num, int arg, int write); 953 954 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 955 956 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 957 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 958 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 959 u32 *out, int outlen); 960 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 961 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 962 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 963 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 964 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 965 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 966 int node); 967 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 968 969 const char *mlx5_command_str(int command); 970 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 971 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 972 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 973 int npsvs, u32 *sig_index); 974 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 975 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 976 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 977 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 978 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 979 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 980 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 981 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 982 struct mlx5_pvlc_reg *pvlc, int write); 983 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 984 struct mlx5_ptys_reg *ptys, int write); 985 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 986 struct mlx5_pmtu_reg *pmtu, int write); 987 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 988 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 989 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 990 int priority, int *is_enable); 991 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 992 int priority, int enable); 993 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 994 void *out, int out_size); 995 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 996 void *in, int in_size); 997 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 998 void *out, int out_size); 999 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1000 int in_size); 1001 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1002 u8 num_of_samples, u16 sample_index, 1003 void *out, int out_size); 1004 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1005 { 1006 return mkey >> 8; 1007 } 1008 1009 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1010 { 1011 return mkey_idx << 8; 1012 } 1013 1014 static inline u8 mlx5_mkey_variant(u32 mkey) 1015 { 1016 return mkey & 0xff; 1017 } 1018 1019 enum { 1020 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1021 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1022 }; 1023 1024 enum { 1025 MAX_MR_CACHE_ENTRIES = 15, 1026 }; 1027 1028 struct mlx5_interface { 1029 void * (*add)(struct mlx5_core_dev *dev); 1030 void (*remove)(struct mlx5_core_dev *dev, void *context); 1031 void (*event)(struct mlx5_core_dev *dev, void *context, 1032 enum mlx5_dev_event event, unsigned long param); 1033 void * (*get_dev)(void *context); 1034 int protocol; 1035 struct list_head list; 1036 }; 1037 1038 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1039 int mlx5_register_interface(struct mlx5_interface *intf); 1040 void mlx5_unregister_interface(struct mlx5_interface *intf); 1041 1042 struct mlx5_profile { 1043 u64 mask; 1044 u8 log_max_qp; 1045 struct { 1046 int size; 1047 int limit; 1048 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1049 }; 1050 1051 enum { 1052 MLX5_PCI_DEV_IS_VF = 1 << 0, 1053 }; 1054 1055 enum { 1056 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1057 }; 1058 1059 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1060 { 1061 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1062 } 1063 1064 #endif /* MLX5_DRIVER_H */ 1065