xref: /freebsd/sys/dev/mlx5/driver.h (revision 036d2e814bf0f5d88ffb4b24c159320894541757) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 enum {
53 	MLX5_BOARD_ID_LEN = 64,
54 	MLX5_MAX_NAME_LEN = 16,
55 };
56 
57 enum {
58 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
59 };
60 
61 enum {
62 	CMD_OWNER_SW		= 0x0,
63 	CMD_OWNER_HW		= 0x1,
64 	CMD_STATUS_SUCCESS	= 0,
65 };
66 
67 enum mlx5_sqp_t {
68 	MLX5_SQP_SMI		= 0,
69 	MLX5_SQP_GSI		= 1,
70 	MLX5_SQP_IEEE_1588	= 2,
71 	MLX5_SQP_SNIFFER	= 3,
72 	MLX5_SQP_SYNC_UMR	= 4,
73 };
74 
75 enum {
76 	MLX5_MAX_PORTS	= 2,
77 };
78 
79 enum {
80 	MLX5_EQ_VEC_PAGES	 = 0,
81 	MLX5_EQ_VEC_CMD		 = 1,
82 	MLX5_EQ_VEC_ASYNC	 = 2,
83 	MLX5_EQ_VEC_COMP_BASE,
84 };
85 
86 enum {
87 	MLX5_ATOMIC_MODE_OFF		= 16,
88 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
89 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
90 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
91 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
92 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
93 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
97 };
98 
99 enum {
100 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
101 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
102 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
103 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
104 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
105 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
106 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
110 };
111 
112 enum {
113 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
114 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
115 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
116 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
117 };
118 
119 enum {
120 	MLX5_REG_QPTS		 = 0x4002,
121 	MLX5_REG_QETCR		 = 0x4005,
122 	MLX5_REG_QPDP		 = 0x4007,
123 	MLX5_REG_QTCT		 = 0x400A,
124 	MLX5_REG_QPDPM		 = 0x4013,
125 	MLX5_REG_QHLL		 = 0x4016,
126 	MLX5_REG_QCAM		 = 0x4019,
127 	MLX5_REG_DCBX_PARAM	 = 0x4020,
128 	MLX5_REG_DCBX_APP	 = 0x4021,
129 	MLX5_REG_FPGA_CAP	 = 0x4022,
130 	MLX5_REG_FPGA_CTRL	 = 0x4023,
131 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
132 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
133 	MLX5_REG_PCAP		 = 0x5001,
134 	MLX5_REG_PMLP		 = 0x5002,
135 	MLX5_REG_PMTU		 = 0x5003,
136 	MLX5_REG_PTYS		 = 0x5004,
137 	MLX5_REG_PAOS		 = 0x5006,
138 	MLX5_REG_PFCC		 = 0x5007,
139 	MLX5_REG_PPCNT		 = 0x5008,
140 	MLX5_REG_PUDE		 = 0x5009,
141 	MLX5_REG_PPTB		 = 0x500B,
142 	MLX5_REG_PBMC		 = 0x500C,
143 	MLX5_REG_PELC		 = 0x500E,
144 	MLX5_REG_PVLC		 = 0x500F,
145 	MLX5_REG_PMPE		 = 0x5010,
146 	MLX5_REG_PMAOS		 = 0x5012,
147 	MLX5_REG_PPLM		 = 0x5023,
148 	MLX5_REG_PBSR		 = 0x5038,
149 	MLX5_REG_PCAM		 = 0x507f,
150 	MLX5_REG_NODE_DESC	 = 0x6001,
151 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
152 	MLX5_REG_MTMP		 = 0x900a,
153 	MLX5_REG_MCIA		 = 0x9014,
154 	MLX5_REG_MFRL		 = 0x9028,
155 	MLX5_REG_MPCNT		 = 0x9051,
156 	MLX5_REG_MCQI		 = 0x9061,
157 	MLX5_REG_MCC		 = 0x9062,
158 	MLX5_REG_MCDA		 = 0x9063,
159 	MLX5_REG_MCAM		 = 0x907f,
160 };
161 
162 enum dbg_rsc_type {
163 	MLX5_DBG_RSC_QP,
164 	MLX5_DBG_RSC_EQ,
165 	MLX5_DBG_RSC_CQ,
166 };
167 
168 enum {
169 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
170 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
171 	MLX5_INTERFACE_NUMBER       = 2,
172 };
173 
174 struct mlx5_field_desc {
175 	struct dentry	       *dent;
176 	int			i;
177 };
178 
179 struct mlx5_rsc_debug {
180 	struct mlx5_core_dev   *dev;
181 	void		       *object;
182 	enum dbg_rsc_type	type;
183 	struct dentry	       *root;
184 	struct mlx5_field_desc	fields[0];
185 };
186 
187 enum mlx5_dev_event {
188 	MLX5_DEV_EVENT_SYS_ERROR,
189 	MLX5_DEV_EVENT_PORT_UP,
190 	MLX5_DEV_EVENT_PORT_DOWN,
191 	MLX5_DEV_EVENT_PORT_INITIALIZED,
192 	MLX5_DEV_EVENT_LID_CHANGE,
193 	MLX5_DEV_EVENT_PKEY_CHANGE,
194 	MLX5_DEV_EVENT_GUID_CHANGE,
195 	MLX5_DEV_EVENT_CLIENT_REREG,
196 	MLX5_DEV_EVENT_VPORT_CHANGE,
197 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
198 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
199 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
200 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
201 };
202 
203 enum mlx5_port_status {
204 	MLX5_PORT_UP        = 1 << 0,
205 	MLX5_PORT_DOWN      = 1 << 1,
206 };
207 
208 enum {
209 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
210 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
211 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
212 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
213 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
214 	MLX5_VSC_DATA_OFFSET	 = 0x14,
215 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
216 };
217 
218 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
219 
220 struct mlx5_uuar_info {
221 	struct mlx5_uar	       *uars;
222 	int			num_uars;
223 	int			num_low_latency_uuars;
224 	unsigned long	       *bitmap;
225 	unsigned int	       *count;
226 	struct mlx5_bf	       *bfs;
227 
228 	/*
229 	 * protect uuar allocation data structs
230 	 */
231 	struct mutex		lock;
232 	u32			ver;
233 };
234 
235 struct mlx5_bf {
236 	void __iomem	       *reg;
237 	void __iomem	       *regreg;
238 	int			buf_size;
239 	struct mlx5_uar	       *uar;
240 	unsigned long		offset;
241 	int			need_lock;
242 	/* protect blue flame buffer selection when needed
243 	 */
244 	spinlock_t		lock;
245 
246 	/* serialize 64 bit writes when done as two 32 bit accesses
247 	 */
248 	spinlock_t		lock32;
249 	int			uuarn;
250 };
251 
252 struct mlx5_cmd_first {
253 	__be32		data[4];
254 };
255 
256 struct cache_ent;
257 struct mlx5_fw_page {
258 	union {
259 		struct rb_node rb_node;
260 		struct list_head list;
261 	};
262 	struct mlx5_cmd_first first;
263 	struct mlx5_core_dev *dev;
264 	bus_dmamap_t dma_map;
265 	bus_addr_t dma_addr;
266 	void *virt_addr;
267 	struct cache_ent *cache;
268 	u32 numpages;
269 	u16 load_done;
270 #define	MLX5_LOAD_ST_NONE 0
271 #define	MLX5_LOAD_ST_SUCCESS 1
272 #define	MLX5_LOAD_ST_FAILURE 2
273 	u16 func_id;
274 };
275 #define	mlx5_cmd_msg mlx5_fw_page
276 
277 struct mlx5_cmd_debug {
278 	struct dentry	       *dbg_root;
279 	struct dentry	       *dbg_in;
280 	struct dentry	       *dbg_out;
281 	struct dentry	       *dbg_outlen;
282 	struct dentry	       *dbg_status;
283 	struct dentry	       *dbg_run;
284 	void		       *in_msg;
285 	void		       *out_msg;
286 	u8			status;
287 	u16			inlen;
288 	u16			outlen;
289 };
290 
291 struct cache_ent {
292 	/* protect block chain allocations
293 	 */
294 	spinlock_t		lock;
295 	struct list_head	head;
296 };
297 
298 struct cmd_msg_cache {
299 	struct cache_ent	large;
300 	struct cache_ent	med;
301 
302 };
303 
304 struct mlx5_traffic_counter {
305 	u64         packets;
306 	u64         octets;
307 };
308 
309 enum mlx5_cmd_mode {
310 	MLX5_CMD_MODE_POLLING,
311 	MLX5_CMD_MODE_EVENTS
312 };
313 
314 struct mlx5_cmd_stats {
315 	u64		sum;
316 	u64		n;
317 	struct dentry  *root;
318 	struct dentry  *avg;
319 	struct dentry  *count;
320 	/* protect command average calculations */
321 	spinlock_t	lock;
322 };
323 
324 struct mlx5_cmd {
325 	struct mlx5_fw_page *cmd_page;
326 	bus_dma_tag_t dma_tag;
327 	struct sx dma_sx;
328 	struct mtx dma_mtx;
329 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
330 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
331 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
332 	struct cv dma_cv;
333 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
334 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
335 	void	       *cmd_buf;
336 	dma_addr_t	dma;
337 	u16		cmdif_rev;
338 	u8		log_sz;
339 	u8		log_stride;
340 	int		max_reg_cmds;
341 	int		events;
342 	u32 __iomem    *vector;
343 
344 	/* protect command queue allocations
345 	 */
346 	spinlock_t	alloc_lock;
347 
348 	/* protect token allocations
349 	 */
350 	spinlock_t	token_lock;
351 	u8		token;
352 	unsigned long	bitmask;
353 	struct semaphore sem;
354 	struct semaphore pages_sem;
355 	enum mlx5_cmd_mode mode;
356 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
357 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
358 	struct mlx5_cmd_debug dbg;
359 	struct cmd_msg_cache cache;
360 	int checksum_disabled;
361 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
362 };
363 
364 struct mlx5_port_caps {
365 	int	gid_table_len;
366 	int	pkey_table_len;
367 	u8	ext_port_cap;
368 };
369 
370 struct mlx5_buf {
371 	bus_dma_tag_t		dma_tag;
372 	bus_dmamap_t		dma_map;
373 	struct mlx5_core_dev   *dev;
374 	struct {
375 		void	       *buf;
376 	} direct;
377 	u64		       *page_list;
378 	int			npages;
379 	int			size;
380 	u8			page_shift;
381 	u8			load_done;
382 };
383 
384 struct mlx5_frag_buf {
385 	struct mlx5_buf_list	*frags;
386 	int			npages;
387 	int			size;
388 	u8			page_shift;
389 };
390 
391 struct mlx5_eq {
392 	struct mlx5_core_dev   *dev;
393 	__be32 __iomem	       *doorbell;
394 	u32			cons_index;
395 	struct mlx5_buf		buf;
396 	int			size;
397 	u8			irqn;
398 	u8			eqn;
399 	int			nent;
400 	u64			mask;
401 	struct list_head	list;
402 	int			index;
403 	struct mlx5_rsc_debug	*dbg;
404 };
405 
406 struct mlx5_core_psv {
407 	u32	psv_idx;
408 	struct psv_layout {
409 		u32	pd;
410 		u16	syndrome;
411 		u16	reserved;
412 		u16	bg;
413 		u16	app_tag;
414 		u32	ref_tag;
415 	} psv;
416 };
417 
418 struct mlx5_core_sig_ctx {
419 	struct mlx5_core_psv	psv_memory;
420 	struct mlx5_core_psv	psv_wire;
421 #if (__FreeBSD_version >= 1100000)
422 	struct ib_sig_err       err_item;
423 #endif
424 	bool			sig_status_checked;
425 	bool			sig_err_exists;
426 	u32			sigerr_count;
427 };
428 
429 enum {
430 	MLX5_MKEY_MR = 1,
431 	MLX5_MKEY_MW,
432 	MLX5_MKEY_MR_USER,
433 };
434 
435 struct mlx5_core_mkey {
436 	u64			iova;
437 	u64			size;
438 	u32			key;
439 	u32			pd;
440 	u32			type;
441 };
442 
443 struct mlx5_core_mr {
444 	u64			iova;
445 	u64			size;
446 	u32			key;
447 	u32			pd;
448 };
449 
450 enum mlx5_res_type {
451 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
452 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
453 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
454 	MLX5_RES_SRQ	= 3,
455 	MLX5_RES_XSRQ	= 4,
456 	MLX5_RES_DCT	= 5,
457 };
458 
459 struct mlx5_core_rsc_common {
460 	enum mlx5_res_type	res;
461 	atomic_t		refcount;
462 	struct completion	free;
463 };
464 
465 struct mlx5_core_srq {
466 	struct mlx5_core_rsc_common	common; /* must be first */
467 	u32				srqn;
468 	int				max;
469 	size_t				max_gs;
470 	size_t				max_avail_gather;
471 	int				wqe_shift;
472 	void				(*event)(struct mlx5_core_srq *, int);
473 	atomic_t			refcount;
474 	struct completion		free;
475 };
476 
477 struct mlx5_eq_table {
478 	void __iomem	       *update_ci;
479 	void __iomem	       *update_arm_ci;
480 	struct list_head	comp_eqs_list;
481 	struct mlx5_eq		pages_eq;
482 	struct mlx5_eq		async_eq;
483 	struct mlx5_eq		cmd_eq;
484 	int			num_comp_vectors;
485 	/* protect EQs list
486 	 */
487 	spinlock_t		lock;
488 };
489 
490 struct mlx5_uar {
491 	u32			index;
492 	void __iomem	       *bf_map;
493 	void __iomem	       *map;
494 };
495 
496 
497 struct mlx5_core_health {
498 	struct mlx5_health_buffer __iomem	*health;
499 	__be32 __iomem		       *health_counter;
500 	struct timer_list		timer;
501 	u32				prev;
502 	int				miss_counter;
503 	u32				fatal_error;
504 	struct workqueue_struct	       *wq_watchdog;
505 	struct work_struct		work_watchdog;
506 	/* wq spinlock to synchronize draining */
507 	spinlock_t			wq_lock;
508 	struct workqueue_struct	       *wq;
509 	unsigned long			flags;
510 	struct work_struct		work;
511 	struct delayed_work		recover_work;
512 	unsigned int			last_reset_req;
513 	struct work_struct		work_cmd_completion;
514 	struct workqueue_struct	       *wq_cmd;
515 };
516 
517 #ifdef RATELIMIT
518 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	(128 * 1024)
519 #else
520 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
521 #endif
522 
523 struct mlx5_cq_linear_array_entry {
524 	spinlock_t	lock;
525 	struct mlx5_core_cq * volatile cq;
526 };
527 
528 struct mlx5_cq_table {
529 	/* protect radix tree
530 	 */
531 	spinlock_t		lock;
532 	struct radix_tree_root	tree;
533 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
534 };
535 
536 struct mlx5_qp_table {
537 	/* protect radix tree
538 	 */
539 	spinlock_t		lock;
540 	struct radix_tree_root	tree;
541 };
542 
543 struct mlx5_srq_table {
544 	/* protect radix tree
545 	 */
546 	spinlock_t		lock;
547 	struct radix_tree_root	tree;
548 };
549 
550 struct mlx5_mr_table {
551 	/* protect radix tree
552 	 */
553 	spinlock_t		lock;
554 	struct radix_tree_root	tree;
555 };
556 
557 #ifdef RATELIMIT
558 struct mlx5_rl_entry {
559 	u32			rate;
560 	u16			burst;
561 	u16			index;
562 	u32			refcount;
563 };
564 
565 struct mlx5_rl_table {
566 	struct mutex		rl_lock;
567 	u16			max_size;
568 	u32			max_rate;
569 	u32			min_rate;
570 	struct mlx5_rl_entry   *rl_entry;
571 };
572 #endif
573 
574 struct mlx5_pme_stats {
575 	u64			status_counters[MLX5_MODULE_STATUS_NUM];
576 	u64			error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
577 };
578 
579 struct mlx5_priv {
580 	char			name[MLX5_MAX_NAME_LEN];
581 	struct mlx5_eq_table	eq_table;
582 	struct msix_entry	*msix_arr;
583 	struct mlx5_uuar_info	uuari;
584 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
585 	int			disable_irqs;
586 
587 	struct io_mapping	*bf_mapping;
588 
589 	/* pages stuff */
590 	struct workqueue_struct *pg_wq;
591 	struct rb_root		page_root;
592 	s64			fw_pages;
593 	atomic_t		reg_pages;
594 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
595 	struct mlx5_core_health health;
596 
597 	struct mlx5_srq_table	srq_table;
598 
599 	/* start: qp staff */
600 	struct mlx5_qp_table	qp_table;
601 	struct dentry	       *qp_debugfs;
602 	struct dentry	       *eq_debugfs;
603 	struct dentry	       *cq_debugfs;
604 	struct dentry	       *cmdif_debugfs;
605 	/* end: qp staff */
606 
607 	/* start: cq staff */
608 	struct mlx5_cq_table	cq_table;
609 	/* end: cq staff */
610 
611 	/* start: mr staff */
612 	struct mlx5_mr_table	mr_table;
613 	/* end: mr staff */
614 
615 	/* start: alloc staff */
616 	int			numa_node;
617 
618 	struct mutex   pgdir_mutex;
619 	struct list_head        pgdir_list;
620 	/* end: alloc staff */
621 	struct dentry	       *dbg_root;
622 
623 	/* protect mkey key part */
624 	spinlock_t		mkey_lock;
625 	u8			mkey_key;
626 
627 	struct list_head        dev_list;
628 	struct list_head        ctx_list;
629 	spinlock_t              ctx_lock;
630 	unsigned long		pci_dev_data;
631 #ifdef RATELIMIT
632 	struct mlx5_rl_table	rl_table;
633 #endif
634 	struct mlx5_pme_stats pme_stats;
635 };
636 
637 enum mlx5_device_state {
638 	MLX5_DEVICE_STATE_UP,
639 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
640 };
641 
642 enum mlx5_interface_state {
643 	MLX5_INTERFACE_STATE_UP,
644 };
645 
646 enum mlx5_pci_status {
647 	MLX5_PCI_STATUS_DISABLED,
648 	MLX5_PCI_STATUS_ENABLED,
649 };
650 
651 #define	MLX5_MAX_RESERVED_GIDS	8
652 
653 struct mlx5_rsvd_gids {
654 	unsigned int start;
655 	unsigned int count;
656 	struct ida ida;
657 };
658 
659 struct mlx5_special_contexts {
660 	int resd_lkey;
661 };
662 
663 struct mlx5_flow_root_namespace;
664 struct mlx5_core_dev {
665 	struct pci_dev	       *pdev;
666 	/* sync pci state */
667 	struct mutex		pci_status_mutex;
668 	enum mlx5_pci_status	pci_status;
669 	char			board_id[MLX5_BOARD_ID_LEN];
670 	struct mlx5_cmd		cmd;
671 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
672 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
673 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
674 	struct {
675 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
676 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
677 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
678 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
679 	} caps;
680 	phys_addr_t		iseg_base;
681 	struct mlx5_init_seg __iomem *iseg;
682 	enum mlx5_device_state	state;
683 	/* sync interface state */
684 	struct mutex		intf_state_mutex;
685 	unsigned long		intf_state;
686 	void			(*event) (struct mlx5_core_dev *dev,
687 					  enum mlx5_dev_event event,
688 					  unsigned long param);
689 	struct mlx5_priv	priv;
690 	struct mlx5_profile	*profile;
691 	atomic_t		num_qps;
692 	u32			vsc_addr;
693 	u32			issi;
694 	struct mlx5_special_contexts special_contexts;
695 	unsigned int module_status[MLX5_MAX_PORTS];
696 	struct mlx5_flow_root_namespace *root_ns;
697 	struct mlx5_flow_root_namespace *fdb_root_ns;
698 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
699 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
700 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
701 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
702 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
703 	struct mlx5_crspace_regmap *dump_rege;
704 	uint32_t *dump_data;
705 	unsigned dump_size;
706 	bool dump_valid;
707 	bool dump_copyout;
708 	struct mtx dump_lock;
709 
710 	struct sysctl_ctx_list	sysctl_ctx;
711 	int			msix_eqvec;
712 	int			pwr_status;
713 	int			pwr_value;
714 
715 	struct {
716 		struct mlx5_rsvd_gids	reserved_gids;
717 		atomic_t		roce_en;
718 	} roce;
719 
720 	struct {
721 		spinlock_t	spinlock;
722 #define	MLX5_MPFS_TABLE_MAX 32
723 		long		bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
724 	} mpfs;
725 #ifdef CONFIG_MLX5_FPGA
726 	struct mlx5_fpga_device	*fpga;
727 #endif
728 };
729 
730 enum {
731 	MLX5_WOL_DISABLE       = 0,
732 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
733 	MLX5_WOL_MAGIC         = 1 << 2,
734 	MLX5_WOL_ARP           = 1 << 3,
735 	MLX5_WOL_BROADCAST     = 1 << 4,
736 	MLX5_WOL_MULTICAST     = 1 << 5,
737 	MLX5_WOL_UNICAST       = 1 << 6,
738 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
739 };
740 
741 struct mlx5_db {
742 	__be32			*db;
743 	union {
744 		struct mlx5_db_pgdir		*pgdir;
745 		struct mlx5_ib_user_db_page	*user_page;
746 	}			u;
747 	dma_addr_t		dma;
748 	int			index;
749 };
750 
751 struct mlx5_net_counters {
752 	u64	packets;
753 	u64	octets;
754 };
755 
756 struct mlx5_ptys_reg {
757 	u8	an_dis_admin;
758 	u8	an_dis_ap;
759 	u8	local_port;
760 	u8	proto_mask;
761 	u32	eth_proto_cap;
762 	u16	ib_link_width_cap;
763 	u16	ib_proto_cap;
764 	u32	eth_proto_admin;
765 	u16	ib_link_width_admin;
766 	u16	ib_proto_admin;
767 	u32	eth_proto_oper;
768 	u16	ib_link_width_oper;
769 	u16	ib_proto_oper;
770 	u32	eth_proto_lp_advertise;
771 };
772 
773 struct mlx5_pvlc_reg {
774 	u8	local_port;
775 	u8	vl_hw_cap;
776 	u8	vl_admin;
777 	u8	vl_operational;
778 };
779 
780 struct mlx5_pmtu_reg {
781 	u8	local_port;
782 	u16	max_mtu;
783 	u16	admin_mtu;
784 	u16	oper_mtu;
785 };
786 
787 struct mlx5_vport_counters {
788 	struct mlx5_net_counters	received_errors;
789 	struct mlx5_net_counters	transmit_errors;
790 	struct mlx5_net_counters	received_ib_unicast;
791 	struct mlx5_net_counters	transmitted_ib_unicast;
792 	struct mlx5_net_counters	received_ib_multicast;
793 	struct mlx5_net_counters	transmitted_ib_multicast;
794 	struct mlx5_net_counters	received_eth_broadcast;
795 	struct mlx5_net_counters	transmitted_eth_broadcast;
796 	struct mlx5_net_counters	received_eth_unicast;
797 	struct mlx5_net_counters	transmitted_eth_unicast;
798 	struct mlx5_net_counters	received_eth_multicast;
799 	struct mlx5_net_counters	transmitted_eth_multicast;
800 };
801 
802 enum {
803 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
804 };
805 
806 struct mlx5_core_dct {
807 	struct mlx5_core_rsc_common	common; /* must be first */
808 	void (*event)(struct mlx5_core_dct *, int);
809 	int			dctn;
810 	struct completion	drained;
811 	struct mlx5_rsc_debug	*dbg;
812 	int			pid;
813 };
814 
815 enum {
816 	MLX5_COMP_EQ_SIZE = 1024,
817 };
818 
819 enum {
820 	MLX5_PTYS_IB = 1 << 0,
821 	MLX5_PTYS_EN = 1 << 2,
822 };
823 
824 struct mlx5_db_pgdir {
825 	struct list_head	list;
826 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
827 	struct mlx5_fw_page    *fw_page;
828 	__be32		       *db_page;
829 	dma_addr_t		db_dma;
830 };
831 
832 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
833 
834 struct mlx5_cmd_work_ent {
835 	struct mlx5_cmd_msg    *in;
836 	struct mlx5_cmd_msg    *out;
837 	int			uin_size;
838 	void		       *uout;
839 	int			uout_size;
840 	mlx5_cmd_cbk_t		callback;
841         struct delayed_work     cb_timeout_work;
842 	void		       *context;
843 	int			idx;
844 	struct completion	done;
845 	struct mlx5_cmd        *cmd;
846 	struct work_struct	work;
847 	struct mlx5_cmd_layout *lay;
848 	int			ret;
849 	int			page_queue;
850 	u8			status;
851 	u8			token;
852 	u64			ts1;
853 	u64			ts2;
854 	u16			op;
855 	u8			busy;
856 	bool			polling;
857 };
858 
859 struct mlx5_pas {
860 	u64	pa;
861 	u8	log_sz;
862 };
863 
864 enum port_state_policy {
865 	MLX5_POLICY_DOWN        = 0,
866 	MLX5_POLICY_UP          = 1,
867 	MLX5_POLICY_FOLLOW      = 2,
868 	MLX5_POLICY_INVALID     = 0xffffffff
869 };
870 
871 static inline void *
872 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
873 {
874 	return ((char *)buf->direct.buf + offset);
875 }
876 
877 
878 extern struct workqueue_struct *mlx5_core_wq;
879 
880 #define STRUCT_FIELD(header, field) \
881 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
882 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
883 
884 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
885 {
886 	return pci_get_drvdata(pdev);
887 }
888 
889 extern struct dentry *mlx5_debugfs_root;
890 
891 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
892 {
893 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
894 }
895 
896 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
897 {
898 	return ioread32be(&dev->iseg->fw_rev) >> 16;
899 }
900 
901 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
902 {
903 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
904 }
905 
906 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
907 {
908 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
909 }
910 
911 static inline int mlx5_get_gid_table_len(u16 param)
912 {
913 	if (param > 4) {
914 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
915 		return 0;
916 	}
917 
918 	return 8 * (1 << param);
919 }
920 
921 static inline void *mlx5_vzalloc(unsigned long size)
922 {
923 	void *rtn;
924 
925 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
926 	return rtn;
927 }
928 
929 static inline void *mlx5_vmalloc(unsigned long size)
930 {
931 	void *rtn;
932 
933 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
934 	if (!rtn)
935 		rtn = vmalloc(size);
936 	return rtn;
937 }
938 
939 static inline u32 mlx5_base_mkey(const u32 key)
940 {
941 	return key & 0xffffff00u;
942 }
943 
944 int mlx5_cmd_init(struct mlx5_core_dev *dev);
945 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
946 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
947 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
948 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
949 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
950 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
951 		  int out_size);
952 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
953 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
954 		     void *context);
955 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
956 			  void *out, int out_size);
957 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
958 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
959 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
960 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
961 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
962 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
963 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
964 int mlx5_health_init(struct mlx5_core_dev *dev);
965 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
966 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
967 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
968 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
969 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
970 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
971 
972 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
973 	mlx5_buf_alloc(dev, size, direct, buf)
974 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
975 		   struct mlx5_buf *buf);
976 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
977 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
978 			 struct mlx5_srq_attr *in);
979 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
980 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
981 			struct mlx5_srq_attr *out);
982 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
983 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
984 		      u16 lwm, int is_srq);
985 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
986 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
987 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
988 			     struct mlx5_core_mr *mkey,
989 			     u32 *in, int inlen,
990 			     u32 *out, int outlen,
991 			     mlx5_cmd_cbk_t callback, void *context);
992 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
993 			  struct mlx5_core_mr *mr,
994 			  u32 *in, int inlen);
995 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
996 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
997 			 u32 *out, int outlen);
998 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
999 			     u32 *mkey);
1000 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1001 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1002 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1003 		      u16 opmod, u8 port);
1004 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1005 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1006 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1007 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1008 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1009 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1010 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1011 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1012 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1013 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1014 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1015 				 s32 npages);
1016 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1017 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1018 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1019 void mlx5_register_debugfs(void);
1020 void mlx5_unregister_debugfs(void);
1021 int mlx5_eq_init(struct mlx5_core_dev *dev);
1022 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1023 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1024 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1025 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1026 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1027 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1028 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1029 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1030 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1031 		       int nent, u64 mask, struct mlx5_uar *uar);
1032 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1033 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1034 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1035 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1036 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1037 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1038 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1039 				u64 addr);
1040 
1041 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1042 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1043 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1044 			 int size_in, void *data_out, int size_out,
1045 			 u16 reg_num, int arg, int write);
1046 
1047 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1048 
1049 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1050 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1051 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1052 		       u32 *out, int outlen);
1053 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1054 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1055 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1056 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1057 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1058 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1059 		       int node);
1060 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1061 
1062 const char *mlx5_command_str(int command);
1063 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1064 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1065 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1066 			 int npsvs, u32 *sig_index);
1067 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1068 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1069 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1070 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1071 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1072 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1073 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1074 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1075 			  struct mlx5_pvlc_reg *pvlc, int write);
1076 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1077 			  struct mlx5_ptys_reg *ptys, int write);
1078 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1079 			  struct mlx5_pmtu_reg *pmtu, int write);
1080 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1081 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1082 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1083 				int priority, int *is_enable);
1084 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1085 				 int priority, int enable);
1086 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1087 				void *out, int out_size);
1088 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1089 				 void *in, int in_size);
1090 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1091 				    void *out, int out_size);
1092 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1093 			       int in_size);
1094 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1095 				   u8 num_of_samples, u16 sample_index,
1096 				   void *out, int out_size);
1097 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1098 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1099 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1100 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1101 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1102 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1103 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1104 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1105 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1106 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1107 			       u16 *p_power, u8 *p_status);
1108 
1109 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1110 {
1111 	return mkey >> 8;
1112 }
1113 
1114 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1115 {
1116 	return mkey_idx << 8;
1117 }
1118 
1119 static inline u8 mlx5_mkey_variant(u32 mkey)
1120 {
1121 	return mkey & 0xff;
1122 }
1123 
1124 enum {
1125 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1126 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1127 };
1128 
1129 enum {
1130 	MAX_MR_CACHE_ENTRIES    = 15,
1131 };
1132 
1133 struct mlx5_interface {
1134 	void *			(*add)(struct mlx5_core_dev *dev);
1135 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1136 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1137 					 enum mlx5_dev_event event, unsigned long param);
1138 	void *                  (*get_dev)(void *context);
1139 	int			protocol;
1140 	struct list_head	list;
1141 };
1142 
1143 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1144 int mlx5_register_interface(struct mlx5_interface *intf);
1145 void mlx5_unregister_interface(struct mlx5_interface *intf);
1146 
1147 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1148 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1149     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1150     const u8 *mac, bool vlan, u16 vlan_id);
1151 
1152 struct mlx5_profile {
1153 	u64	mask;
1154 	u8	log_max_qp;
1155 	struct {
1156 		int	size;
1157 		int	limit;
1158 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1159 };
1160 
1161 enum {
1162 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1163 };
1164 
1165 enum {
1166 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1167 };
1168 
1169 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1170 {
1171 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1172 }
1173 #ifdef RATELIMIT
1174 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1175 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1176 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1177 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1178 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1179 
1180 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1181 {
1182 	return !!(dev->priv.rl_table.max_size);
1183 }
1184 #endif
1185 
1186 #endif /* MLX5_DRIVER_H */
1187