xref: /freebsd/sys/dev/mlx5/driver.h (revision 1c807f67959d14169d62f62bbed018a85f86472c)
1dc7e38acSHans Petter Selasky /*-
2*1c807f67SHans Petter Selasky  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
3dc7e38acSHans Petter Selasky  *
4dc7e38acSHans Petter Selasky  * Redistribution and use in source and binary forms, with or without
5dc7e38acSHans Petter Selasky  * modification, are permitted provided that the following conditions
6dc7e38acSHans Petter Selasky  * are met:
7dc7e38acSHans Petter Selasky  * 1. Redistributions of source code must retain the above copyright
8dc7e38acSHans Petter Selasky  *    notice, this list of conditions and the following disclaimer.
9dc7e38acSHans Petter Selasky  * 2. Redistributions in binary form must reproduce the above copyright
10dc7e38acSHans Petter Selasky  *    notice, this list of conditions and the following disclaimer in the
11dc7e38acSHans Petter Selasky  *    documentation and/or other materials provided with the distribution.
12dc7e38acSHans Petter Selasky  *
13dc7e38acSHans Petter Selasky  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14dc7e38acSHans Petter Selasky  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15dc7e38acSHans Petter Selasky  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16dc7e38acSHans Petter Selasky  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17dc7e38acSHans Petter Selasky  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18dc7e38acSHans Petter Selasky  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19dc7e38acSHans Petter Selasky  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20dc7e38acSHans Petter Selasky  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21dc7e38acSHans Petter Selasky  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22dc7e38acSHans Petter Selasky  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23dc7e38acSHans Petter Selasky  * SUCH DAMAGE.
24dc7e38acSHans Petter Selasky  *
25dc7e38acSHans Petter Selasky  * $FreeBSD$
26dc7e38acSHans Petter Selasky  */
27dc7e38acSHans Petter Selasky 
28dc7e38acSHans Petter Selasky #ifndef MLX5_DRIVER_H
29dc7e38acSHans Petter Selasky #define MLX5_DRIVER_H
30dc7e38acSHans Petter Selasky 
31dc7e38acSHans Petter Selasky #include <linux/kernel.h>
32dc7e38acSHans Petter Selasky #include <linux/completion.h>
33dc7e38acSHans Petter Selasky #include <linux/pci.h>
34dc7e38acSHans Petter Selasky #include <linux/cache.h>
35dc7e38acSHans Petter Selasky #include <linux/rbtree.h>
3676a5241fSHans Petter Selasky #include <linux/if_ether.h>
37dc7e38acSHans Petter Selasky #include <linux/semaphore.h>
38dc7e38acSHans Petter Selasky #include <linux/slab.h>
39dc7e38acSHans Petter Selasky #include <linux/vmalloc.h>
40dc7e38acSHans Petter Selasky #include <linux/radix-tree.h>
41dc7e38acSHans Petter Selasky 
42dc7e38acSHans Petter Selasky #include <dev/mlx5/device.h>
43dc7e38acSHans Petter Selasky #include <dev/mlx5/doorbell.h>
44dc7e38acSHans Petter Selasky 
45cb4e4a6eSHans Petter Selasky #define MLX5_QCOUNTER_SETS_NETDEV 64
4644a03e91SHans Petter Selasky #define MLX5_MAX_NUMBER_OF_VFS 128
47cb4e4a6eSHans Petter Selasky 
48dc7e38acSHans Petter Selasky enum {
49dc7e38acSHans Petter Selasky 	MLX5_BOARD_ID_LEN = 64,
50dc7e38acSHans Petter Selasky 	MLX5_MAX_NAME_LEN = 16,
51dc7e38acSHans Petter Selasky };
52dc7e38acSHans Petter Selasky 
53dc7e38acSHans Petter Selasky enum {
54cb4e4a6eSHans Petter Selasky 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
55dc7e38acSHans Petter Selasky 	MLX5_CMD_WQ_MAX_NAME	= 32,
56dc7e38acSHans Petter Selasky };
57dc7e38acSHans Petter Selasky 
58dc7e38acSHans Petter Selasky enum {
59dc7e38acSHans Petter Selasky 	CMD_OWNER_SW		= 0x0,
60dc7e38acSHans Petter Selasky 	CMD_OWNER_HW		= 0x1,
61dc7e38acSHans Petter Selasky 	CMD_STATUS_SUCCESS	= 0,
62dc7e38acSHans Petter Selasky };
63dc7e38acSHans Petter Selasky 
64dc7e38acSHans Petter Selasky enum mlx5_sqp_t {
65dc7e38acSHans Petter Selasky 	MLX5_SQP_SMI		= 0,
66dc7e38acSHans Petter Selasky 	MLX5_SQP_GSI		= 1,
67dc7e38acSHans Petter Selasky 	MLX5_SQP_IEEE_1588	= 2,
68dc7e38acSHans Petter Selasky 	MLX5_SQP_SNIFFER	= 3,
69dc7e38acSHans Petter Selasky 	MLX5_SQP_SYNC_UMR	= 4,
70dc7e38acSHans Petter Selasky };
71dc7e38acSHans Petter Selasky 
72dc7e38acSHans Petter Selasky enum {
73dc7e38acSHans Petter Selasky 	MLX5_MAX_PORTS	= 2,
74dc7e38acSHans Petter Selasky };
75dc7e38acSHans Petter Selasky 
76dc7e38acSHans Petter Selasky enum {
77dc7e38acSHans Petter Selasky 	MLX5_EQ_VEC_PAGES	 = 0,
78dc7e38acSHans Petter Selasky 	MLX5_EQ_VEC_CMD		 = 1,
79dc7e38acSHans Petter Selasky 	MLX5_EQ_VEC_ASYNC	 = 2,
80dc7e38acSHans Petter Selasky 	MLX5_EQ_VEC_COMP_BASE,
81dc7e38acSHans Petter Selasky };
82dc7e38acSHans Petter Selasky 
83dc7e38acSHans Petter Selasky enum {
84dc7e38acSHans Petter Selasky 	MLX5_MAX_IRQ_NAME	= 32
85dc7e38acSHans Petter Selasky };
86dc7e38acSHans Petter Selasky 
87dc7e38acSHans Petter Selasky enum {
88cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_OFF		= 16,
89cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
90cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
91cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
92cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
93cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
94cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
95cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
96cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
97cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
98cb4e4a6eSHans Petter Selasky };
99cb4e4a6eSHans Petter Selasky 
100cb4e4a6eSHans Petter Selasky enum {
101cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
102cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
103cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
104cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
105cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
106cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
107cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
108cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
109cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
110cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
111cb4e4a6eSHans Petter Selasky };
112cb4e4a6eSHans Petter Selasky 
113cb4e4a6eSHans Petter Selasky enum {
114cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
115cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
116cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
117cb4e4a6eSHans Petter Selasky 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
118dc7e38acSHans Petter Selasky };
119dc7e38acSHans Petter Selasky 
120dc7e38acSHans Petter Selasky enum {
121dc7e38acSHans Petter Selasky 	MLX5_REG_QETCR		 = 0x4005,
122dc7e38acSHans Petter Selasky 	MLX5_REG_QPDP		 = 0x4007,
123dc7e38acSHans Petter Selasky 	MLX5_REG_QTCT		 = 0x400A,
124cb022443SHans Petter Selasky 	MLX5_REG_QHLL		 = 0x4016,
125cb4e4a6eSHans Petter Selasky 	MLX5_REG_DCBX_PARAM	 = 0x4020,
126cb4e4a6eSHans Petter Selasky 	MLX5_REG_DCBX_APP	 = 0x4021,
127dc7e38acSHans Petter Selasky 	MLX5_REG_PCAP		 = 0x5001,
128dc7e38acSHans Petter Selasky 	MLX5_REG_PMTU		 = 0x5003,
129dc7e38acSHans Petter Selasky 	MLX5_REG_PTYS		 = 0x5004,
130dc7e38acSHans Petter Selasky 	MLX5_REG_PAOS		 = 0x5006,
131dc7e38acSHans Petter Selasky 	MLX5_REG_PFCC		 = 0x5007,
132dc7e38acSHans Petter Selasky 	MLX5_REG_PPCNT		 = 0x5008,
133dc7e38acSHans Petter Selasky 	MLX5_REG_PMAOS		 = 0x5012,
134dc7e38acSHans Petter Selasky 	MLX5_REG_PUDE		 = 0x5009,
135dc7e38acSHans Petter Selasky 	MLX5_REG_PPTB		 = 0x500B,
136dc7e38acSHans Petter Selasky 	MLX5_REG_PBMC		 = 0x500C,
137dc7e38acSHans Petter Selasky 	MLX5_REG_PMPE		 = 0x5010,
138dc7e38acSHans Petter Selasky 	MLX5_REG_PELC		 = 0x500e,
139dc7e38acSHans Petter Selasky 	MLX5_REG_PVLC		 = 0x500f,
140dc7e38acSHans Petter Selasky 	MLX5_REG_PMLP		 = 0x5002,
141dc7e38acSHans Petter Selasky 	MLX5_REG_NODE_DESC	 = 0x6001,
142dc7e38acSHans Petter Selasky 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
143dc7e38acSHans Petter Selasky 	MLX5_REG_MCIA		 = 0x9014,
144cb4e4a6eSHans Petter Selasky 	MLX5_REG_MPCNT		 = 0x9051,
145dc7e38acSHans Petter Selasky };
146dc7e38acSHans Petter Selasky 
147dc7e38acSHans Petter Selasky enum dbg_rsc_type {
148dc7e38acSHans Petter Selasky 	MLX5_DBG_RSC_QP,
149dc7e38acSHans Petter Selasky 	MLX5_DBG_RSC_EQ,
150dc7e38acSHans Petter Selasky 	MLX5_DBG_RSC_CQ,
151dc7e38acSHans Petter Selasky };
152dc7e38acSHans Petter Selasky 
153cb4e4a6eSHans Petter Selasky enum {
154cb4e4a6eSHans Petter Selasky 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
155cb4e4a6eSHans Petter Selasky 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
156cb4e4a6eSHans Petter Selasky 	MLX5_INTERFACE_NUMBER       = 2,
157cb4e4a6eSHans Petter Selasky };
158cb4e4a6eSHans Petter Selasky 
159dc7e38acSHans Petter Selasky struct mlx5_field_desc {
160dc7e38acSHans Petter Selasky 	struct dentry	       *dent;
161dc7e38acSHans Petter Selasky 	int			i;
162dc7e38acSHans Petter Selasky };
163dc7e38acSHans Petter Selasky 
164dc7e38acSHans Petter Selasky struct mlx5_rsc_debug {
165dc7e38acSHans Petter Selasky 	struct mlx5_core_dev   *dev;
166dc7e38acSHans Petter Selasky 	void		       *object;
167dc7e38acSHans Petter Selasky 	enum dbg_rsc_type	type;
168dc7e38acSHans Petter Selasky 	struct dentry	       *root;
169dc7e38acSHans Petter Selasky 	struct mlx5_field_desc	fields[0];
170dc7e38acSHans Petter Selasky };
171dc7e38acSHans Petter Selasky 
172dc7e38acSHans Petter Selasky enum mlx5_dev_event {
173dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_SYS_ERROR,
174dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_PORT_UP,
175dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_PORT_DOWN,
176dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_PORT_INITIALIZED,
177dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_LID_CHANGE,
178dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_PKEY_CHANGE,
179dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_GUID_CHANGE,
180dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_CLIENT_REREG,
181dc7e38acSHans Petter Selasky 	MLX5_DEV_EVENT_VPORT_CHANGE,
182cb4e4a6eSHans Petter Selasky 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
183cb4e4a6eSHans Petter Selasky 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
184cb4e4a6eSHans Petter Selasky 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
185cb4e4a6eSHans Petter Selasky 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
186dc7e38acSHans Petter Selasky };
187dc7e38acSHans Petter Selasky 
188dc7e38acSHans Petter Selasky enum mlx5_port_status {
189dc7e38acSHans Petter Selasky 	MLX5_PORT_UP        = 1 << 0,
190dc7e38acSHans Petter Selasky 	MLX5_PORT_DOWN      = 1 << 1,
191dc7e38acSHans Petter Selasky };
192dc7e38acSHans Petter Selasky 
193dc7e38acSHans Petter Selasky enum mlx5_link_mode {
194dc7e38acSHans Petter Selasky 	MLX5_1000BASE_CX_SGMII	= 0,
195dc7e38acSHans Petter Selasky 	MLX5_1000BASE_KX	= 1,
196dc7e38acSHans Petter Selasky 	MLX5_10GBASE_CX4	= 2,
197dc7e38acSHans Petter Selasky 	MLX5_10GBASE_KX4	= 3,
198dc7e38acSHans Petter Selasky 	MLX5_10GBASE_KR		= 4,
199dc7e38acSHans Petter Selasky 	MLX5_20GBASE_KR2	= 5,
200dc7e38acSHans Petter Selasky 	MLX5_40GBASE_CR4	= 6,
201dc7e38acSHans Petter Selasky 	MLX5_40GBASE_KR4	= 7,
202dc7e38acSHans Petter Selasky 	MLX5_56GBASE_R4		= 8,
203dc7e38acSHans Petter Selasky 	MLX5_10GBASE_CR		= 12,
204dc7e38acSHans Petter Selasky 	MLX5_10GBASE_SR		= 13,
205dc7e38acSHans Petter Selasky 	MLX5_10GBASE_ER		= 14,
206dc7e38acSHans Petter Selasky 	MLX5_40GBASE_SR4	= 15,
207dc7e38acSHans Petter Selasky 	MLX5_40GBASE_LR4	= 16,
208dc7e38acSHans Petter Selasky 	MLX5_100GBASE_CR4	= 20,
209dc7e38acSHans Petter Selasky 	MLX5_100GBASE_SR4	= 21,
210dc7e38acSHans Petter Selasky 	MLX5_100GBASE_KR4	= 22,
211dc7e38acSHans Petter Selasky 	MLX5_100GBASE_LR4	= 23,
212dc7e38acSHans Petter Selasky 	MLX5_100BASE_TX		= 24,
213dc7e38acSHans Petter Selasky 	MLX5_1000BASE_T		= 25,
214dc7e38acSHans Petter Selasky 	MLX5_10GBASE_T		= 26,
215dc7e38acSHans Petter Selasky 	MLX5_25GBASE_CR		= 27,
216dc7e38acSHans Petter Selasky 	MLX5_25GBASE_KR		= 28,
217dc7e38acSHans Petter Selasky 	MLX5_25GBASE_SR		= 29,
218dc7e38acSHans Petter Selasky 	MLX5_50GBASE_CR2	= 30,
219dc7e38acSHans Petter Selasky 	MLX5_50GBASE_KR2	= 31,
220dc7e38acSHans Petter Selasky 	MLX5_LINK_MODES_NUMBER,
221dc7e38acSHans Petter Selasky };
222dc7e38acSHans Petter Selasky 
223dc7e38acSHans Petter Selasky #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
224dc7e38acSHans Petter Selasky 
225dc7e38acSHans Petter Selasky struct mlx5_uuar_info {
226dc7e38acSHans Petter Selasky 	struct mlx5_uar	       *uars;
227dc7e38acSHans Petter Selasky 	int			num_uars;
228dc7e38acSHans Petter Selasky 	int			num_low_latency_uuars;
229dc7e38acSHans Petter Selasky 	unsigned long	       *bitmap;
230dc7e38acSHans Petter Selasky 	unsigned int	       *count;
231dc7e38acSHans Petter Selasky 	struct mlx5_bf	       *bfs;
232dc7e38acSHans Petter Selasky 
233dc7e38acSHans Petter Selasky 	/*
234dc7e38acSHans Petter Selasky 	 * protect uuar allocation data structs
235dc7e38acSHans Petter Selasky 	 */
236dc7e38acSHans Petter Selasky 	struct mutex		lock;
237dc7e38acSHans Petter Selasky 	u32			ver;
238dc7e38acSHans Petter Selasky };
239dc7e38acSHans Petter Selasky 
240dc7e38acSHans Petter Selasky struct mlx5_bf {
241dc7e38acSHans Petter Selasky 	void __iomem	       *reg;
242dc7e38acSHans Petter Selasky 	void __iomem	       *regreg;
243dc7e38acSHans Petter Selasky 	int			buf_size;
244dc7e38acSHans Petter Selasky 	struct mlx5_uar	       *uar;
245dc7e38acSHans Petter Selasky 	unsigned long		offset;
246dc7e38acSHans Petter Selasky 	int			need_lock;
247dc7e38acSHans Petter Selasky 	/* protect blue flame buffer selection when needed
248dc7e38acSHans Petter Selasky 	 */
249dc7e38acSHans Petter Selasky 	spinlock_t		lock;
250dc7e38acSHans Petter Selasky 
251dc7e38acSHans Petter Selasky 	/* serialize 64 bit writes when done as two 32 bit accesses
252dc7e38acSHans Petter Selasky 	 */
253dc7e38acSHans Petter Selasky 	spinlock_t		lock32;
254dc7e38acSHans Petter Selasky 	int			uuarn;
255dc7e38acSHans Petter Selasky };
256dc7e38acSHans Petter Selasky 
257dc7e38acSHans Petter Selasky struct mlx5_cmd_first {
258dc7e38acSHans Petter Selasky 	__be32		data[4];
259dc7e38acSHans Petter Selasky };
260dc7e38acSHans Petter Selasky 
261*1c807f67SHans Petter Selasky struct cache_ent;
262*1c807f67SHans Petter Selasky struct mlx5_fw_page {
263*1c807f67SHans Petter Selasky 	union {
264*1c807f67SHans Petter Selasky 		struct rb_node rb_node;
265dc7e38acSHans Petter Selasky 		struct list_head list;
266dc7e38acSHans Petter Selasky 	};
267*1c807f67SHans Petter Selasky 	struct mlx5_cmd_first first;
268*1c807f67SHans Petter Selasky 	struct mlx5_core_dev *dev;
269*1c807f67SHans Petter Selasky 	bus_dmamap_t dma_map;
270*1c807f67SHans Petter Selasky 	bus_addr_t dma_addr;
271*1c807f67SHans Petter Selasky 	void *virt_addr;
272*1c807f67SHans Petter Selasky 	struct cache_ent *cache;
273*1c807f67SHans Petter Selasky 	u32 numpages;
274*1c807f67SHans Petter Selasky 	u16 load_done;
275*1c807f67SHans Petter Selasky #define	MLX5_LOAD_ST_NONE 0
276*1c807f67SHans Petter Selasky #define	MLX5_LOAD_ST_SUCCESS 1
277*1c807f67SHans Petter Selasky #define	MLX5_LOAD_ST_FAILURE 2
278*1c807f67SHans Petter Selasky 	u16 func_id;
279*1c807f67SHans Petter Selasky };
280*1c807f67SHans Petter Selasky #define	mlx5_cmd_msg mlx5_fw_page
281dc7e38acSHans Petter Selasky 
282dc7e38acSHans Petter Selasky struct mlx5_cmd_debug {
283dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_root;
284dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_in;
285dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_out;
286dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_outlen;
287dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_status;
288dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_run;
289dc7e38acSHans Petter Selasky 	void		       *in_msg;
290dc7e38acSHans Petter Selasky 	void		       *out_msg;
291dc7e38acSHans Petter Selasky 	u8			status;
292dc7e38acSHans Petter Selasky 	u16			inlen;
293dc7e38acSHans Petter Selasky 	u16			outlen;
294dc7e38acSHans Petter Selasky };
295dc7e38acSHans Petter Selasky 
296dc7e38acSHans Petter Selasky struct cache_ent {
297dc7e38acSHans Petter Selasky 	/* protect block chain allocations
298dc7e38acSHans Petter Selasky 	 */
299dc7e38acSHans Petter Selasky 	spinlock_t		lock;
300dc7e38acSHans Petter Selasky 	struct list_head	head;
301dc7e38acSHans Petter Selasky };
302dc7e38acSHans Petter Selasky 
303dc7e38acSHans Petter Selasky struct cmd_msg_cache {
304dc7e38acSHans Petter Selasky 	struct cache_ent	large;
305dc7e38acSHans Petter Selasky 	struct cache_ent	med;
306dc7e38acSHans Petter Selasky 
307dc7e38acSHans Petter Selasky };
308dc7e38acSHans Petter Selasky 
309dc7e38acSHans Petter Selasky struct mlx5_cmd_stats {
310dc7e38acSHans Petter Selasky 	u64		sum;
311dc7e38acSHans Petter Selasky 	u64		n;
312dc7e38acSHans Petter Selasky 	struct dentry  *root;
313dc7e38acSHans Petter Selasky 	struct dentry  *avg;
314dc7e38acSHans Petter Selasky 	struct dentry  *count;
315dc7e38acSHans Petter Selasky 	/* protect command average calculations */
316dc7e38acSHans Petter Selasky 	spinlock_t	lock;
317dc7e38acSHans Petter Selasky };
318dc7e38acSHans Petter Selasky 
319dc7e38acSHans Petter Selasky struct mlx5_cmd {
320*1c807f67SHans Petter Selasky 	struct mlx5_fw_page *cmd_page;
321*1c807f67SHans Petter Selasky 	bus_dma_tag_t dma_tag;
322*1c807f67SHans Petter Selasky 	struct sx dma_sx;
323*1c807f67SHans Petter Selasky 	struct mtx dma_mtx;
324*1c807f67SHans Petter Selasky #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
325*1c807f67SHans Petter Selasky #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
326*1c807f67SHans Petter Selasky #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
327*1c807f67SHans Petter Selasky 	struct cv dma_cv;
328*1c807f67SHans Petter Selasky #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
329*1c807f67SHans Petter Selasky #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
330dc7e38acSHans Petter Selasky 	void	       *cmd_buf;
331dc7e38acSHans Petter Selasky 	dma_addr_t	dma;
332dc7e38acSHans Petter Selasky 	u16		cmdif_rev;
333dc7e38acSHans Petter Selasky 	u8		log_sz;
334dc7e38acSHans Petter Selasky 	u8		log_stride;
335dc7e38acSHans Petter Selasky 	int		max_reg_cmds;
336dc7e38acSHans Petter Selasky 	int		events;
337dc7e38acSHans Petter Selasky 	u32 __iomem    *vector;
338dc7e38acSHans Petter Selasky 
339dc7e38acSHans Petter Selasky 	/* protect command queue allocations
340dc7e38acSHans Petter Selasky 	 */
341dc7e38acSHans Petter Selasky 	spinlock_t	alloc_lock;
342dc7e38acSHans Petter Selasky 
343dc7e38acSHans Petter Selasky 	/* protect token allocations
344dc7e38acSHans Petter Selasky 	 */
345dc7e38acSHans Petter Selasky 	spinlock_t	token_lock;
346dc7e38acSHans Petter Selasky 	u8		token;
347dc7e38acSHans Petter Selasky 	unsigned long	bitmask;
348dc7e38acSHans Petter Selasky 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
349dc7e38acSHans Petter Selasky 	struct workqueue_struct *wq;
350dc7e38acSHans Petter Selasky 	struct semaphore sem;
351dc7e38acSHans Petter Selasky 	struct semaphore pages_sem;
352dc7e38acSHans Petter Selasky 	int	mode;
353dc7e38acSHans Petter Selasky 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
354dc7e38acSHans Petter Selasky 	struct mlx5_cmd_debug dbg;
355dc7e38acSHans Petter Selasky 	struct cmd_msg_cache cache;
356dc7e38acSHans Petter Selasky 	int checksum_disabled;
357dc7e38acSHans Petter Selasky 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
358dc7e38acSHans Petter Selasky 	int moving_to_polling;
359dc7e38acSHans Petter Selasky };
360dc7e38acSHans Petter Selasky 
361dc7e38acSHans Petter Selasky struct mlx5_port_caps {
362dc7e38acSHans Petter Selasky 	int	gid_table_len;
363dc7e38acSHans Petter Selasky 	int	pkey_table_len;
364dc7e38acSHans Petter Selasky 	u8	ext_port_cap;
365dc7e38acSHans Petter Selasky };
366dc7e38acSHans Petter Selasky 
367dc7e38acSHans Petter Selasky struct mlx5_buf {
368*1c807f67SHans Petter Selasky 	bus_dma_tag_t		dma_tag;
369*1c807f67SHans Petter Selasky 	bus_dmamap_t		dma_map;
370*1c807f67SHans Petter Selasky 	struct mlx5_core_dev   *dev;
371*1c807f67SHans Petter Selasky 	struct {
372*1c807f67SHans Petter Selasky 		void	       *buf;
373*1c807f67SHans Petter Selasky 	} direct;
374*1c807f67SHans Petter Selasky 	u64		       *page_list;
375dc7e38acSHans Petter Selasky 	int			npages;
376dc7e38acSHans Petter Selasky 	int			size;
377dc7e38acSHans Petter Selasky 	u8			page_shift;
378*1c807f67SHans Petter Selasky 	u8			load_done;
379dc7e38acSHans Petter Selasky };
380dc7e38acSHans Petter Selasky 
381dc7e38acSHans Petter Selasky struct mlx5_eq {
382dc7e38acSHans Petter Selasky 	struct mlx5_core_dev   *dev;
383dc7e38acSHans Petter Selasky 	__be32 __iomem	       *doorbell;
384dc7e38acSHans Petter Selasky 	u32			cons_index;
385dc7e38acSHans Petter Selasky 	struct mlx5_buf		buf;
386dc7e38acSHans Petter Selasky 	int			size;
387dc7e38acSHans Petter Selasky 	u8			irqn;
388dc7e38acSHans Petter Selasky 	u8			eqn;
389dc7e38acSHans Petter Selasky 	int			nent;
390dc7e38acSHans Petter Selasky 	u64			mask;
391dc7e38acSHans Petter Selasky 	struct list_head	list;
392dc7e38acSHans Petter Selasky 	int			index;
393dc7e38acSHans Petter Selasky 	struct mlx5_rsc_debug	*dbg;
394dc7e38acSHans Petter Selasky };
395dc7e38acSHans Petter Selasky 
396dc7e38acSHans Petter Selasky struct mlx5_core_psv {
397dc7e38acSHans Petter Selasky 	u32	psv_idx;
398dc7e38acSHans Petter Selasky 	struct psv_layout {
399dc7e38acSHans Petter Selasky 		u32	pd;
400dc7e38acSHans Petter Selasky 		u16	syndrome;
401dc7e38acSHans Petter Selasky 		u16	reserved;
402dc7e38acSHans Petter Selasky 		u16	bg;
403dc7e38acSHans Petter Selasky 		u16	app_tag;
404dc7e38acSHans Petter Selasky 		u32	ref_tag;
405dc7e38acSHans Petter Selasky 	} psv;
406dc7e38acSHans Petter Selasky };
407dc7e38acSHans Petter Selasky 
408dc7e38acSHans Petter Selasky struct mlx5_core_sig_ctx {
409dc7e38acSHans Petter Selasky 	struct mlx5_core_psv	psv_memory;
410dc7e38acSHans Petter Selasky 	struct mlx5_core_psv	psv_wire;
411dc7e38acSHans Petter Selasky #if (__FreeBSD_version >= 1100000)
412dc7e38acSHans Petter Selasky 	struct ib_sig_err       err_item;
413dc7e38acSHans Petter Selasky #endif
414dc7e38acSHans Petter Selasky 	bool			sig_status_checked;
415dc7e38acSHans Petter Selasky 	bool			sig_err_exists;
416dc7e38acSHans Petter Selasky 	u32			sigerr_count;
417dc7e38acSHans Petter Selasky };
418dc7e38acSHans Petter Selasky 
419dc7e38acSHans Petter Selasky struct mlx5_core_mr {
420dc7e38acSHans Petter Selasky 	u64			iova;
421dc7e38acSHans Petter Selasky 	u64			size;
422dc7e38acSHans Petter Selasky 	u32			key;
423dc7e38acSHans Petter Selasky 	u32			pd;
424dc7e38acSHans Petter Selasky };
425dc7e38acSHans Petter Selasky 
426dc7e38acSHans Petter Selasky enum mlx5_res_type {
427cb4e4a6eSHans Petter Selasky 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
428cb4e4a6eSHans Petter Selasky 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
429cb4e4a6eSHans Petter Selasky 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
430cb4e4a6eSHans Petter Selasky 	MLX5_RES_SRQ	= 3,
431cb4e4a6eSHans Petter Selasky 	MLX5_RES_XSRQ	= 4,
432cb4e4a6eSHans Petter Selasky 	MLX5_RES_DCT	= 5,
433dc7e38acSHans Petter Selasky };
434dc7e38acSHans Petter Selasky 
435dc7e38acSHans Petter Selasky struct mlx5_core_rsc_common {
436dc7e38acSHans Petter Selasky 	enum mlx5_res_type	res;
437dc7e38acSHans Petter Selasky 	atomic_t		refcount;
438dc7e38acSHans Petter Selasky 	struct completion	free;
439dc7e38acSHans Petter Selasky };
440dc7e38acSHans Petter Selasky 
441dc7e38acSHans Petter Selasky struct mlx5_core_srq {
442dc7e38acSHans Petter Selasky 	struct mlx5_core_rsc_common	common; /* must be first */
443dc7e38acSHans Petter Selasky 	u32				srqn;
444dc7e38acSHans Petter Selasky 	int				max;
445dc7e38acSHans Petter Selasky 	int				max_gs;
446dc7e38acSHans Petter Selasky 	int				max_avail_gather;
447dc7e38acSHans Petter Selasky 	int				wqe_shift;
448dc7e38acSHans Petter Selasky 	void				(*event)(struct mlx5_core_srq *, int);
449dc7e38acSHans Petter Selasky 	atomic_t			refcount;
450dc7e38acSHans Petter Selasky 	struct completion		free;
451dc7e38acSHans Petter Selasky };
452dc7e38acSHans Petter Selasky 
453dc7e38acSHans Petter Selasky struct mlx5_eq_table {
454dc7e38acSHans Petter Selasky 	void __iomem	       *update_ci;
455dc7e38acSHans Petter Selasky 	void __iomem	       *update_arm_ci;
456dc7e38acSHans Petter Selasky 	struct list_head	comp_eqs_list;
457dc7e38acSHans Petter Selasky 	struct mlx5_eq		pages_eq;
458dc7e38acSHans Petter Selasky 	struct mlx5_eq		async_eq;
459dc7e38acSHans Petter Selasky 	struct mlx5_eq		cmd_eq;
460dc7e38acSHans Petter Selasky 	int			num_comp_vectors;
461dc7e38acSHans Petter Selasky 	/* protect EQs list
462dc7e38acSHans Petter Selasky 	 */
463dc7e38acSHans Petter Selasky 	spinlock_t		lock;
464dc7e38acSHans Petter Selasky };
465dc7e38acSHans Petter Selasky 
466dc7e38acSHans Petter Selasky struct mlx5_uar {
467dc7e38acSHans Petter Selasky 	u32			index;
468dc7e38acSHans Petter Selasky 	void __iomem	       *bf_map;
469dc7e38acSHans Petter Selasky 	void __iomem	       *map;
470dc7e38acSHans Petter Selasky };
471dc7e38acSHans Petter Selasky 
472dc7e38acSHans Petter Selasky 
473dc7e38acSHans Petter Selasky struct mlx5_core_health {
474dc7e38acSHans Petter Selasky 	struct mlx5_health_buffer __iomem	*health;
475dc7e38acSHans Petter Selasky 	__be32 __iomem		       *health_counter;
476dc7e38acSHans Petter Selasky 	struct timer_list		timer;
477dc7e38acSHans Petter Selasky 	struct list_head		list;
478dc7e38acSHans Petter Selasky 	u32				prev;
479dc7e38acSHans Petter Selasky 	int				miss_counter;
480dc7e38acSHans Petter Selasky };
481dc7e38acSHans Petter Selasky 
482dc7e38acSHans Petter Selasky #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
483dc7e38acSHans Petter Selasky 
484dc7e38acSHans Petter Selasky struct mlx5_cq_linear_array_entry {
485dc7e38acSHans Petter Selasky 	spinlock_t	lock;
486dc7e38acSHans Petter Selasky 	struct mlx5_core_cq * volatile cq;
487dc7e38acSHans Petter Selasky };
488dc7e38acSHans Petter Selasky 
489dc7e38acSHans Petter Selasky struct mlx5_cq_table {
490dc7e38acSHans Petter Selasky 	/* protect radix tree
491dc7e38acSHans Petter Selasky 	 */
492dc7e38acSHans Petter Selasky 	spinlock_t		lock;
493dc7e38acSHans Petter Selasky 	struct radix_tree_root	tree;
494dc7e38acSHans Petter Selasky 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
495dc7e38acSHans Petter Selasky };
496dc7e38acSHans Petter Selasky 
497dc7e38acSHans Petter Selasky struct mlx5_qp_table {
498dc7e38acSHans Petter Selasky 	/* protect radix tree
499dc7e38acSHans Petter Selasky 	 */
500dc7e38acSHans Petter Selasky 	spinlock_t		lock;
501dc7e38acSHans Petter Selasky 	struct radix_tree_root	tree;
502dc7e38acSHans Petter Selasky };
503dc7e38acSHans Petter Selasky 
504dc7e38acSHans Petter Selasky struct mlx5_srq_table {
505dc7e38acSHans Petter Selasky 	/* protect radix tree
506dc7e38acSHans Petter Selasky 	 */
507dc7e38acSHans Petter Selasky 	spinlock_t		lock;
508dc7e38acSHans Petter Selasky 	struct radix_tree_root	tree;
509dc7e38acSHans Petter Selasky };
510dc7e38acSHans Petter Selasky 
511dc7e38acSHans Petter Selasky struct mlx5_mr_table {
512dc7e38acSHans Petter Selasky 	/* protect radix tree
513dc7e38acSHans Petter Selasky 	 */
514cb4e4a6eSHans Petter Selasky 	spinlock_t		lock;
515dc7e38acSHans Petter Selasky 	struct radix_tree_root	tree;
516dc7e38acSHans Petter Selasky };
517dc7e38acSHans Petter Selasky 
518dc7e38acSHans Petter Selasky struct mlx5_irq_info {
519dc7e38acSHans Petter Selasky 	char name[MLX5_MAX_IRQ_NAME];
520dc7e38acSHans Petter Selasky };
521dc7e38acSHans Petter Selasky 
522dc7e38acSHans Petter Selasky struct mlx5_priv {
523dc7e38acSHans Petter Selasky 	char			name[MLX5_MAX_NAME_LEN];
524dc7e38acSHans Petter Selasky 	struct mlx5_eq_table	eq_table;
525dc7e38acSHans Petter Selasky 	struct msix_entry	*msix_arr;
526dc7e38acSHans Petter Selasky 	struct mlx5_irq_info	*irq_info;
527dc7e38acSHans Petter Selasky 	struct mlx5_uuar_info	uuari;
528dc7e38acSHans Petter Selasky 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
529dc7e38acSHans Petter Selasky 
530dc7e38acSHans Petter Selasky 	struct io_mapping	*bf_mapping;
531dc7e38acSHans Petter Selasky 
532dc7e38acSHans Petter Selasky 	/* pages stuff */
533dc7e38acSHans Petter Selasky 	struct workqueue_struct *pg_wq;
534dc7e38acSHans Petter Selasky 	struct rb_root		page_root;
535115bc9b1SHans Petter Selasky 	s64			fw_pages;
536cb4e4a6eSHans Petter Selasky 	atomic_t		reg_pages;
53744a03e91SHans Petter Selasky 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
538dc7e38acSHans Petter Selasky 	struct mlx5_core_health health;
539dc7e38acSHans Petter Selasky 
540dc7e38acSHans Petter Selasky 	struct mlx5_srq_table	srq_table;
541dc7e38acSHans Petter Selasky 
542dc7e38acSHans Petter Selasky 	/* start: qp staff */
543dc7e38acSHans Petter Selasky 	struct mlx5_qp_table	qp_table;
544dc7e38acSHans Petter Selasky 	struct dentry	       *qp_debugfs;
545dc7e38acSHans Petter Selasky 	struct dentry	       *eq_debugfs;
546dc7e38acSHans Petter Selasky 	struct dentry	       *cq_debugfs;
547dc7e38acSHans Petter Selasky 	struct dentry	       *cmdif_debugfs;
548dc7e38acSHans Petter Selasky 	/* end: qp staff */
549dc7e38acSHans Petter Selasky 
550dc7e38acSHans Petter Selasky 	/* start: cq staff */
551dc7e38acSHans Petter Selasky 	struct mlx5_cq_table	cq_table;
552dc7e38acSHans Petter Selasky 	/* end: cq staff */
553dc7e38acSHans Petter Selasky 
554dc7e38acSHans Petter Selasky 	/* start: mr staff */
555dc7e38acSHans Petter Selasky 	struct mlx5_mr_table	mr_table;
556dc7e38acSHans Petter Selasky 	/* end: mr staff */
557dc7e38acSHans Petter Selasky 
558dc7e38acSHans Petter Selasky 	/* start: alloc staff */
559dc7e38acSHans Petter Selasky 	int			numa_node;
560dc7e38acSHans Petter Selasky 
561dc7e38acSHans Petter Selasky 	struct mutex   pgdir_mutex;
562dc7e38acSHans Petter Selasky 	struct list_head        pgdir_list;
563dc7e38acSHans Petter Selasky 	/* end: alloc staff */
564dc7e38acSHans Petter Selasky 	struct dentry	       *dbg_root;
565dc7e38acSHans Petter Selasky 
566dc7e38acSHans Petter Selasky 	/* protect mkey key part */
567dc7e38acSHans Petter Selasky 	spinlock_t		mkey_lock;
568dc7e38acSHans Petter Selasky 	u8			mkey_key;
569dc7e38acSHans Petter Selasky 
570dc7e38acSHans Petter Selasky 	struct list_head        dev_list;
571dc7e38acSHans Petter Selasky 	struct list_head        ctx_list;
572dc7e38acSHans Petter Selasky 	spinlock_t              ctx_lock;
573cb4e4a6eSHans Petter Selasky 	unsigned long		pci_dev_data;
574cb4e4a6eSHans Petter Selasky };
575cb4e4a6eSHans Petter Selasky 
576cb4e4a6eSHans Petter Selasky enum mlx5_device_state {
577cb4e4a6eSHans Petter Selasky 	MLX5_DEVICE_STATE_UP,
578cb4e4a6eSHans Petter Selasky 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
579dc7e38acSHans Petter Selasky };
580dc7e38acSHans Petter Selasky 
581dc7e38acSHans Petter Selasky struct mlx5_special_contexts {
582dc7e38acSHans Petter Selasky 	int resd_lkey;
583dc7e38acSHans Petter Selasky };
584dc7e38acSHans Petter Selasky 
585dc7e38acSHans Petter Selasky struct mlx5_core_dev {
586dc7e38acSHans Petter Selasky 	struct pci_dev	       *pdev;
587dc7e38acSHans Petter Selasky 	char			board_id[MLX5_BOARD_ID_LEN];
588dc7e38acSHans Petter Selasky 	struct mlx5_cmd		cmd;
589dc7e38acSHans Petter Selasky 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
590dc7e38acSHans Petter Selasky 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
591dc7e38acSHans Petter Selasky 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
592dc7e38acSHans Petter Selasky 	struct mlx5_init_seg __iomem *iseg;
593cb4e4a6eSHans Petter Selasky 	enum mlx5_device_state	state;
594dc7e38acSHans Petter Selasky 	void			(*event) (struct mlx5_core_dev *dev,
595dc7e38acSHans Petter Selasky 					  enum mlx5_dev_event event,
596dc7e38acSHans Petter Selasky 					  unsigned long param);
597dc7e38acSHans Petter Selasky 	struct mlx5_priv	priv;
598dc7e38acSHans Petter Selasky 	struct mlx5_profile	*profile;
599dc7e38acSHans Petter Selasky 	atomic_t		num_qps;
600dc7e38acSHans Petter Selasky 	u32			issi;
601dc7e38acSHans Petter Selasky 	struct mlx5_special_contexts special_contexts;
60221dd6527SHans Petter Selasky 	unsigned int module_status[MLX5_MAX_PORTS];
603cb4e4a6eSHans Petter Selasky 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
604dc7e38acSHans Petter Selasky };
605dc7e38acSHans Petter Selasky 
606dc7e38acSHans Petter Selasky enum {
607dc7e38acSHans Petter Selasky 	MLX5_WOL_DISABLE       = 0,
608dc7e38acSHans Petter Selasky 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
609dc7e38acSHans Petter Selasky 	MLX5_WOL_MAGIC         = 1 << 2,
610dc7e38acSHans Petter Selasky 	MLX5_WOL_ARP           = 1 << 3,
611dc7e38acSHans Petter Selasky 	MLX5_WOL_BROADCAST     = 1 << 4,
612dc7e38acSHans Petter Selasky 	MLX5_WOL_MULTICAST     = 1 << 5,
613dc7e38acSHans Petter Selasky 	MLX5_WOL_UNICAST       = 1 << 6,
614dc7e38acSHans Petter Selasky 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
615dc7e38acSHans Petter Selasky };
616dc7e38acSHans Petter Selasky 
617dc7e38acSHans Petter Selasky struct mlx5_db {
618dc7e38acSHans Petter Selasky 	__be32			*db;
619dc7e38acSHans Petter Selasky 	union {
620dc7e38acSHans Petter Selasky 		struct mlx5_db_pgdir		*pgdir;
621dc7e38acSHans Petter Selasky 		struct mlx5_ib_user_db_page	*user_page;
622dc7e38acSHans Petter Selasky 	}			u;
623dc7e38acSHans Petter Selasky 	dma_addr_t		dma;
624dc7e38acSHans Petter Selasky 	int			index;
625dc7e38acSHans Petter Selasky };
626dc7e38acSHans Petter Selasky 
627dc7e38acSHans Petter Selasky struct mlx5_net_counters {
628dc7e38acSHans Petter Selasky 	u64	packets;
629dc7e38acSHans Petter Selasky 	u64	octets;
630dc7e38acSHans Petter Selasky };
631dc7e38acSHans Petter Selasky 
632dc7e38acSHans Petter Selasky struct mlx5_ptys_reg {
633cb4e4a6eSHans Petter Selasky 	u8	an_dis_admin;
634cb4e4a6eSHans Petter Selasky 	u8	an_dis_ap;
635dc7e38acSHans Petter Selasky 	u8	local_port;
636dc7e38acSHans Petter Selasky 	u8	proto_mask;
637dc7e38acSHans Petter Selasky 	u32	eth_proto_cap;
638dc7e38acSHans Petter Selasky 	u16	ib_link_width_cap;
639dc7e38acSHans Petter Selasky 	u16	ib_proto_cap;
640dc7e38acSHans Petter Selasky 	u32	eth_proto_admin;
641dc7e38acSHans Petter Selasky 	u16	ib_link_width_admin;
642dc7e38acSHans Petter Selasky 	u16	ib_proto_admin;
643dc7e38acSHans Petter Selasky 	u32	eth_proto_oper;
644dc7e38acSHans Petter Selasky 	u16	ib_link_width_oper;
645dc7e38acSHans Petter Selasky 	u16	ib_proto_oper;
646dc7e38acSHans Petter Selasky 	u32	eth_proto_lp_advertise;
647dc7e38acSHans Petter Selasky };
648dc7e38acSHans Petter Selasky 
649dc7e38acSHans Petter Selasky struct mlx5_pvlc_reg {
650dc7e38acSHans Petter Selasky 	u8	local_port;
651dc7e38acSHans Petter Selasky 	u8	vl_hw_cap;
652dc7e38acSHans Petter Selasky 	u8	vl_admin;
653dc7e38acSHans Petter Selasky 	u8	vl_operational;
654dc7e38acSHans Petter Selasky };
655dc7e38acSHans Petter Selasky 
656dc7e38acSHans Petter Selasky struct mlx5_pmtu_reg {
657dc7e38acSHans Petter Selasky 	u8	local_port;
658dc7e38acSHans Petter Selasky 	u16	max_mtu;
659dc7e38acSHans Petter Selasky 	u16	admin_mtu;
660dc7e38acSHans Petter Selasky 	u16	oper_mtu;
661dc7e38acSHans Petter Selasky };
662dc7e38acSHans Petter Selasky 
663dc7e38acSHans Petter Selasky struct mlx5_vport_counters {
664dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	received_errors;
665dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	transmit_errors;
666dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	received_ib_unicast;
667dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	transmitted_ib_unicast;
668dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	received_ib_multicast;
669dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	transmitted_ib_multicast;
670dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	received_eth_broadcast;
671dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	transmitted_eth_broadcast;
672dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	received_eth_unicast;
673dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	transmitted_eth_unicast;
674dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	received_eth_multicast;
675dc7e38acSHans Petter Selasky 	struct mlx5_net_counters	transmitted_eth_multicast;
676dc7e38acSHans Petter Selasky };
677dc7e38acSHans Petter Selasky 
678dc7e38acSHans Petter Selasky enum {
679*1c807f67SHans Petter Selasky 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
680dc7e38acSHans Petter Selasky };
681dc7e38acSHans Petter Selasky 
682cb4e4a6eSHans Petter Selasky struct mlx5_core_dct {
683cb4e4a6eSHans Petter Selasky 	struct mlx5_core_rsc_common	common; /* must be first */
684cb4e4a6eSHans Petter Selasky 	void (*event)(struct mlx5_core_dct *, int);
685cb4e4a6eSHans Petter Selasky 	int			dctn;
686cb4e4a6eSHans Petter Selasky 	struct completion	drained;
687cb4e4a6eSHans Petter Selasky 	struct mlx5_rsc_debug	*dbg;
688cb4e4a6eSHans Petter Selasky 	int			pid;
689cb4e4a6eSHans Petter Selasky };
690cb4e4a6eSHans Petter Selasky 
691dc7e38acSHans Petter Selasky enum {
692dc7e38acSHans Petter Selasky 	MLX5_COMP_EQ_SIZE = 1024,
693dc7e38acSHans Petter Selasky };
694dc7e38acSHans Petter Selasky 
695dc7e38acSHans Petter Selasky enum {
696dc7e38acSHans Petter Selasky 	MLX5_PTYS_IB = 1 << 0,
697dc7e38acSHans Petter Selasky 	MLX5_PTYS_EN = 1 << 2,
698dc7e38acSHans Petter Selasky };
699dc7e38acSHans Petter Selasky 
700dc7e38acSHans Petter Selasky struct mlx5_db_pgdir {
701dc7e38acSHans Petter Selasky 	struct list_head	list;
702dc7e38acSHans Petter Selasky 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
703*1c807f67SHans Petter Selasky 	struct mlx5_fw_page    *fw_page;
704dc7e38acSHans Petter Selasky 	__be32		       *db_page;
705dc7e38acSHans Petter Selasky 	dma_addr_t		db_dma;
706dc7e38acSHans Petter Selasky };
707dc7e38acSHans Petter Selasky 
708dc7e38acSHans Petter Selasky typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
709dc7e38acSHans Petter Selasky 
710dc7e38acSHans Petter Selasky struct mlx5_cmd_work_ent {
711dc7e38acSHans Petter Selasky 	struct mlx5_cmd_msg    *in;
712dc7e38acSHans Petter Selasky 	struct mlx5_cmd_msg    *out;
713*1c807f67SHans Petter Selasky 	int			uin_size;
714dc7e38acSHans Petter Selasky 	void		       *uout;
715dc7e38acSHans Petter Selasky 	int			uout_size;
716dc7e38acSHans Petter Selasky 	mlx5_cmd_cbk_t		callback;
717dc7e38acSHans Petter Selasky 	void		       *context;
718dc7e38acSHans Petter Selasky 	int			idx;
719dc7e38acSHans Petter Selasky 	struct completion	done;
720dc7e38acSHans Petter Selasky 	struct mlx5_cmd        *cmd;
721dc7e38acSHans Petter Selasky 	struct work_struct	work;
722dc7e38acSHans Petter Selasky 	struct mlx5_cmd_layout *lay;
723dc7e38acSHans Petter Selasky 	int			ret;
724dc7e38acSHans Petter Selasky 	int			page_queue;
725dc7e38acSHans Petter Selasky 	u8			status;
726dc7e38acSHans Petter Selasky 	u8			token;
727dc7e38acSHans Petter Selasky 	u64			ts1;
728dc7e38acSHans Petter Selasky 	u64			ts2;
729dc7e38acSHans Petter Selasky 	u16			op;
73030dfc051SHans Petter Selasky 	u8			busy;
731dc7e38acSHans Petter Selasky };
732dc7e38acSHans Petter Selasky 
733dc7e38acSHans Petter Selasky struct mlx5_pas {
734dc7e38acSHans Petter Selasky 	u64	pa;
735dc7e38acSHans Petter Selasky 	u8	log_sz;
736dc7e38acSHans Petter Selasky };
737dc7e38acSHans Petter Selasky 
738*1c807f67SHans Petter Selasky static inline void *
739*1c807f67SHans Petter Selasky mlx5_buf_offset(struct mlx5_buf *buf, int offset)
740dc7e38acSHans Petter Selasky {
741*1c807f67SHans Petter Selasky 	return ((char *)buf->direct.buf + offset);
742dc7e38acSHans Petter Selasky }
743dc7e38acSHans Petter Selasky 
744dc7e38acSHans Petter Selasky 
745dc7e38acSHans Petter Selasky extern struct workqueue_struct *mlx5_core_wq;
746dc7e38acSHans Petter Selasky 
747dc7e38acSHans Petter Selasky #define STRUCT_FIELD(header, field) \
748dc7e38acSHans Petter Selasky 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
749dc7e38acSHans Petter Selasky 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
750dc7e38acSHans Petter Selasky 
751dc7e38acSHans Petter Selasky static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
752dc7e38acSHans Petter Selasky {
753dc7e38acSHans Petter Selasky 	return pci_get_drvdata(pdev);
754dc7e38acSHans Petter Selasky }
755dc7e38acSHans Petter Selasky 
756dc7e38acSHans Petter Selasky extern struct dentry *mlx5_debugfs_root;
757dc7e38acSHans Petter Selasky 
758dc7e38acSHans Petter Selasky static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
759dc7e38acSHans Petter Selasky {
760dc7e38acSHans Petter Selasky 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
761dc7e38acSHans Petter Selasky }
762dc7e38acSHans Petter Selasky 
763dc7e38acSHans Petter Selasky static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
764dc7e38acSHans Petter Selasky {
765dc7e38acSHans Petter Selasky 	return ioread32be(&dev->iseg->fw_rev) >> 16;
766dc7e38acSHans Petter Selasky }
767dc7e38acSHans Petter Selasky 
768dc7e38acSHans Petter Selasky static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
769dc7e38acSHans Petter Selasky {
770dc7e38acSHans Petter Selasky 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
771dc7e38acSHans Petter Selasky }
772dc7e38acSHans Petter Selasky 
773dc7e38acSHans Petter Selasky static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
774dc7e38acSHans Petter Selasky {
775dc7e38acSHans Petter Selasky 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
776dc7e38acSHans Petter Selasky }
777dc7e38acSHans Petter Selasky 
778dc7e38acSHans Petter Selasky static inline int mlx5_get_gid_table_len(u16 param)
779dc7e38acSHans Petter Selasky {
780dc7e38acSHans Petter Selasky 	if (param > 4) {
781dc7e38acSHans Petter Selasky 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
782dc7e38acSHans Petter Selasky 		return 0;
783dc7e38acSHans Petter Selasky 	}
784dc7e38acSHans Petter Selasky 
785dc7e38acSHans Petter Selasky 	return 8 * (1 << param);
786dc7e38acSHans Petter Selasky }
787dc7e38acSHans Petter Selasky 
788dc7e38acSHans Petter Selasky static inline void *mlx5_vzalloc(unsigned long size)
789dc7e38acSHans Petter Selasky {
790dc7e38acSHans Petter Selasky 	void *rtn;
791dc7e38acSHans Petter Selasky 
792dc7e38acSHans Petter Selasky 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
793dc7e38acSHans Petter Selasky 	return rtn;
794dc7e38acSHans Petter Selasky }
795dc7e38acSHans Petter Selasky 
796cb4e4a6eSHans Petter Selasky static inline void *mlx5_vmalloc(unsigned long size)
797dc7e38acSHans Petter Selasky {
798cb4e4a6eSHans Petter Selasky 	void *rtn;
799cb4e4a6eSHans Petter Selasky 
800cb4e4a6eSHans Petter Selasky 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
801cb4e4a6eSHans Petter Selasky 	if (!rtn)
802cb4e4a6eSHans Petter Selasky 		rtn = vmalloc(size);
803cb4e4a6eSHans Petter Selasky 	return rtn;
804dc7e38acSHans Petter Selasky }
805dc7e38acSHans Petter Selasky 
80630dfc051SHans Petter Selasky void mlx5_enter_error_state(struct mlx5_core_dev *dev);
807dc7e38acSHans Petter Selasky int mlx5_cmd_init(struct mlx5_core_dev *dev);
808dc7e38acSHans Petter Selasky void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
809dc7e38acSHans Petter Selasky void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
810dc7e38acSHans Petter Selasky void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
811dc7e38acSHans Petter Selasky int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
812dc7e38acSHans Petter Selasky int mlx5_cmd_status_to_err_v2(void *ptr);
813dc7e38acSHans Petter Selasky int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
814dc7e38acSHans Petter Selasky 		       enum mlx5_cap_mode cap_mode);
815dc7e38acSHans Petter Selasky int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
816dc7e38acSHans Petter Selasky 		  int out_size);
817dc7e38acSHans Petter Selasky int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
818dc7e38acSHans Petter Selasky 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
819dc7e38acSHans Petter Selasky 		     void *context);
820dc7e38acSHans Petter Selasky int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
821dc7e38acSHans Petter Selasky int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
822dc7e38acSHans Petter Selasky int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
823dc7e38acSHans Petter Selasky int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
824dc7e38acSHans Petter Selasky int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
825dc7e38acSHans Petter Selasky void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
826dc7e38acSHans Petter Selasky void mlx5_health_cleanup(void);
827dc7e38acSHans Petter Selasky void  __init mlx5_health_init(void);
828dc7e38acSHans Petter Selasky void mlx5_start_health_poll(struct mlx5_core_dev *dev);
829dc7e38acSHans Petter Selasky void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
830*1c807f67SHans Petter Selasky 
831*1c807f67SHans Petter Selasky #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
832*1c807f67SHans Petter Selasky 	mlx5_buf_alloc(dev, size, direct, buf)
833dc7e38acSHans Petter Selasky int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
834dc7e38acSHans Petter Selasky 		   struct mlx5_buf *buf);
835dc7e38acSHans Petter Selasky void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
836dc7e38acSHans Petter Selasky int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
837dc7e38acSHans Petter Selasky 			 struct mlx5_create_srq_mbox_in *in, int inlen,
838dc7e38acSHans Petter Selasky 			 int is_xrc);
839dc7e38acSHans Petter Selasky int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
840dc7e38acSHans Petter Selasky int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
841dc7e38acSHans Petter Selasky 			struct mlx5_query_srq_mbox_out *out);
842dc7e38acSHans Petter Selasky int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
843dc7e38acSHans Petter Selasky int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
844dc7e38acSHans Petter Selasky 		      u16 lwm, int is_srq);
845dc7e38acSHans Petter Selasky void mlx5_init_mr_table(struct mlx5_core_dev *dev);
846dc7e38acSHans Petter Selasky void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
847dc7e38acSHans Petter Selasky int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
848dc7e38acSHans Petter Selasky 			  struct mlx5_create_mkey_mbox_in *in, int inlen,
849dc7e38acSHans Petter Selasky 			  mlx5_cmd_cbk_t callback, void *context,
850dc7e38acSHans Petter Selasky 			  struct mlx5_create_mkey_mbox_out *out);
851dc7e38acSHans Petter Selasky int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
852dc7e38acSHans Petter Selasky int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
853dc7e38acSHans Petter Selasky 			 struct mlx5_query_mkey_mbox_out *out, int outlen);
854dc7e38acSHans Petter Selasky int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
855dc7e38acSHans Petter Selasky 			     u32 *mkey);
856dc7e38acSHans Petter Selasky int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
857dc7e38acSHans Petter Selasky int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
858dc7e38acSHans Petter Selasky int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
859dc7e38acSHans Petter Selasky 		      u16 opmod, u8 port);
860*1c807f67SHans Petter Selasky void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
861*1c807f67SHans Petter Selasky void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
862*1c807f67SHans Petter Selasky struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
863*1c807f67SHans Petter Selasky void mlx5_fwp_free(struct mlx5_fw_page *fwp);
864*1c807f67SHans Petter Selasky u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
865*1c807f67SHans Petter Selasky void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
866dc7e38acSHans Petter Selasky void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
867dc7e38acSHans Petter Selasky void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
868dc7e38acSHans Petter Selasky int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
869dc7e38acSHans Petter Selasky void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
870dc7e38acSHans Petter Selasky void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
871dc7e38acSHans Petter Selasky 				 s32 npages);
872dc7e38acSHans Petter Selasky int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
873dc7e38acSHans Petter Selasky int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
87444a03e91SHans Petter Selasky s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
875dc7e38acSHans Petter Selasky void mlx5_register_debugfs(void);
876dc7e38acSHans Petter Selasky void mlx5_unregister_debugfs(void);
877dc7e38acSHans Petter Selasky int mlx5_eq_init(struct mlx5_core_dev *dev);
878dc7e38acSHans Petter Selasky void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
879dc7e38acSHans Petter Selasky void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
880dc7e38acSHans Petter Selasky void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
881dc7e38acSHans Petter Selasky void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
882dc7e38acSHans Petter Selasky void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
883dc7e38acSHans Petter Selasky struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
884d0ce5a0dSHans Petter Selasky void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector);
88530dfc051SHans Petter Selasky void mlx5_trigger_cmd_completions(struct mlx5_core_dev *dev);
886dc7e38acSHans Petter Selasky void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
887dc7e38acSHans Petter Selasky int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
888dc7e38acSHans Petter Selasky 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
889dc7e38acSHans Petter Selasky int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
890dc7e38acSHans Petter Selasky int mlx5_start_eqs(struct mlx5_core_dev *dev);
891dc7e38acSHans Petter Selasky int mlx5_stop_eqs(struct mlx5_core_dev *dev);
892dc7e38acSHans Petter Selasky int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
893dc7e38acSHans Petter Selasky int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
894dc7e38acSHans Petter Selasky int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
895cb4e4a6eSHans Petter Selasky int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
896cb4e4a6eSHans Petter Selasky 				u64 addr);
897dc7e38acSHans Petter Selasky 
898dc7e38acSHans Petter Selasky int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
899dc7e38acSHans Petter Selasky void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
900dc7e38acSHans Petter Selasky int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
901dc7e38acSHans Petter Selasky 			 int size_in, void *data_out, int size_out,
902dc7e38acSHans Petter Selasky 			 u16 reg_num, int arg, int write);
903dc7e38acSHans Petter Selasky 
904cb4e4a6eSHans Petter Selasky void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
905dc7e38acSHans Petter Selasky int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
906dc7e38acSHans Petter Selasky int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
907dc7e38acSHans Petter Selasky 			 int ptys_size, int proto_mask);
908dc7e38acSHans Petter Selasky int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
909dc7e38acSHans Petter Selasky 			      u32 *proto_cap, int proto_mask);
910cb4e4a6eSHans Petter Selasky int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
911cb4e4a6eSHans Petter Selasky 			    u8 *an_disable_cap, u8 *an_disable_status);
912cb4e4a6eSHans Petter Selasky int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
913cb4e4a6eSHans Petter Selasky 			  u32 eth_proto_admin, int proto_mask);
914dc7e38acSHans Petter Selasky int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
915dc7e38acSHans Petter Selasky 				u32 *proto_admin, int proto_mask);
916dc7e38acSHans Petter Selasky int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
917dc7e38acSHans Petter Selasky 			int proto_mask);
918dc7e38acSHans Petter Selasky int mlx5_set_port_status(struct mlx5_core_dev *dev,
919dc7e38acSHans Petter Selasky 			 enum mlx5_port_status status);
920dc7e38acSHans Petter Selasky int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
921cb4e4a6eSHans Petter Selasky int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
922cb4e4a6eSHans Petter Selasky 				 enum mlx5_port_status *status);
923dc7e38acSHans Petter Selasky int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port,
924dc7e38acSHans Petter Selasky 			u32 rx_pause, u32 tx_pause);
925dc7e38acSHans Petter Selasky int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
926dc7e38acSHans Petter Selasky 			  u32 *rx_pause, u32 *tx_pause);
927cb4e4a6eSHans Petter Selasky int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
928cb4e4a6eSHans Petter Selasky int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
929dc7e38acSHans Petter Selasky 
930dc7e38acSHans Petter Selasky int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
931dc7e38acSHans Petter Selasky int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
932dc7e38acSHans Petter Selasky int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
933dc7e38acSHans Petter Selasky 
93421dd6527SHans Petter Selasky unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
935dc7e38acSHans Petter Selasky int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
936dc7e38acSHans Petter Selasky int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
937dc7e38acSHans Petter Selasky 		      int device_addr, int size, int module_num, u32 *data,
938dc7e38acSHans Petter Selasky 		      int *size_read);
939dc7e38acSHans Petter Selasky 
940dc7e38acSHans Petter Selasky int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
941dc7e38acSHans Petter Selasky void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
942dc7e38acSHans Petter Selasky int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
943dc7e38acSHans Petter Selasky 		       struct mlx5_query_eq_mbox_out *out, int outlen);
944dc7e38acSHans Petter Selasky int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
945dc7e38acSHans Petter Selasky void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
946dc7e38acSHans Petter Selasky int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
947dc7e38acSHans Petter Selasky void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
948dc7e38acSHans Petter Selasky int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
949dc7e38acSHans Petter Selasky int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
950dc7e38acSHans Petter Selasky 		       int node);
951dc7e38acSHans Petter Selasky void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
952dc7e38acSHans Petter Selasky 
953dc7e38acSHans Petter Selasky const char *mlx5_command_str(int command);
954dc7e38acSHans Petter Selasky int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
955dc7e38acSHans Petter Selasky void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
956dc7e38acSHans Petter Selasky int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
957dc7e38acSHans Petter Selasky 			 int npsvs, u32 *sig_index);
958dc7e38acSHans Petter Selasky int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
959dc7e38acSHans Petter Selasky void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
960dc7e38acSHans Petter Selasky u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
961dc7e38acSHans Petter Selasky int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
962dc7e38acSHans Petter Selasky int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
963dc7e38acSHans Petter Selasky int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
964dc7e38acSHans Petter Selasky 			  struct mlx5_pvlc_reg *pvlc, int write);
965dc7e38acSHans Petter Selasky int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
966dc7e38acSHans Petter Selasky 			  struct mlx5_ptys_reg *ptys, int write);
967dc7e38acSHans Petter Selasky int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
968dc7e38acSHans Petter Selasky 			  struct mlx5_pmtu_reg *pmtu, int write);
969dc7e38acSHans Petter Selasky int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
970dc7e38acSHans Petter Selasky int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
971dc7e38acSHans Petter Selasky int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
972dc7e38acSHans Petter Selasky 				int priority, int *is_enable);
973dc7e38acSHans Petter Selasky int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
974dc7e38acSHans Petter Selasky 				 int priority, int enable);
975dc7e38acSHans Petter Selasky int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
976dc7e38acSHans Petter Selasky 				void *out, int out_size);
977dc7e38acSHans Petter Selasky int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
978dc7e38acSHans Petter Selasky 				 void *in, int in_size);
979dc7e38acSHans Petter Selasky int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
980dc7e38acSHans Petter Selasky 				    void *out, int out_size);
981cb022443SHans Petter Selasky int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
982cb022443SHans Petter Selasky 			       int in_size);
983cb022443SHans Petter Selasky int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
984cb022443SHans Petter Selasky 				   u8 num_of_samples, u16 sample_index,
985cb022443SHans Petter Selasky 				   void *out, int out_size);
986dc7e38acSHans Petter Selasky static inline u32 mlx5_mkey_to_idx(u32 mkey)
987dc7e38acSHans Petter Selasky {
988dc7e38acSHans Petter Selasky 	return mkey >> 8;
989dc7e38acSHans Petter Selasky }
990dc7e38acSHans Petter Selasky 
991dc7e38acSHans Petter Selasky static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
992dc7e38acSHans Petter Selasky {
993dc7e38acSHans Petter Selasky 	return mkey_idx << 8;
994dc7e38acSHans Petter Selasky }
995dc7e38acSHans Petter Selasky 
996dc7e38acSHans Petter Selasky static inline u8 mlx5_mkey_variant(u32 mkey)
997dc7e38acSHans Petter Selasky {
998dc7e38acSHans Petter Selasky 	return mkey & 0xff;
999dc7e38acSHans Petter Selasky }
1000dc7e38acSHans Petter Selasky 
1001dc7e38acSHans Petter Selasky enum {
1002dc7e38acSHans Petter Selasky 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1003dc7e38acSHans Petter Selasky 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1004dc7e38acSHans Petter Selasky };
1005dc7e38acSHans Petter Selasky 
1006dc7e38acSHans Petter Selasky enum {
1007cb4e4a6eSHans Petter Selasky 	MAX_MR_CACHE_ENTRIES    = 15,
1008dc7e38acSHans Petter Selasky };
1009dc7e38acSHans Petter Selasky 
1010dc7e38acSHans Petter Selasky struct mlx5_interface {
1011dc7e38acSHans Petter Selasky 	void *			(*add)(struct mlx5_core_dev *dev);
1012dc7e38acSHans Petter Selasky 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1013dc7e38acSHans Petter Selasky 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1014dc7e38acSHans Petter Selasky 					 enum mlx5_dev_event event, unsigned long param);
1015dc7e38acSHans Petter Selasky 	void *                  (*get_dev)(void *context);
1016dc7e38acSHans Petter Selasky 	int			protocol;
1017dc7e38acSHans Petter Selasky 	struct list_head	list;
1018dc7e38acSHans Petter Selasky };
1019dc7e38acSHans Petter Selasky 
1020dc7e38acSHans Petter Selasky void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1021dc7e38acSHans Petter Selasky int mlx5_register_interface(struct mlx5_interface *intf);
1022dc7e38acSHans Petter Selasky void mlx5_unregister_interface(struct mlx5_interface *intf);
1023dc7e38acSHans Petter Selasky 
1024dc7e38acSHans Petter Selasky struct mlx5_profile {
1025dc7e38acSHans Petter Selasky 	u64	mask;
1026dc7e38acSHans Petter Selasky 	u8	log_max_qp;
1027dc7e38acSHans Petter Selasky 	struct {
1028dc7e38acSHans Petter Selasky 		int	size;
1029dc7e38acSHans Petter Selasky 		int	limit;
1030dc7e38acSHans Petter Selasky 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1031dc7e38acSHans Petter Selasky };
1032dc7e38acSHans Petter Selasky 
1033cb4e4a6eSHans Petter Selasky enum {
1034cb4e4a6eSHans Petter Selasky 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1035cb4e4a6eSHans Petter Selasky };
1036cb4e4a6eSHans Petter Selasky 
1037cb4e4a6eSHans Petter Selasky static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1038cb4e4a6eSHans Petter Selasky {
1039cb4e4a6eSHans Petter Selasky 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1040cb4e4a6eSHans Petter Selasky }
1041dc7e38acSHans Petter Selasky 
104298a998d5SHans Petter Selasky #define MLX5_EEPROM_MAX_BYTES			32
1043dc7e38acSHans Petter Selasky #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK	0x000000ff
1044dc7e38acSHans Petter Selasky #define MLX5_EEPROM_REVISION_ID_BYTE_MASK	0x0000ff00
1045dc7e38acSHans Petter Selasky #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK	0x00040000
1046dc7e38acSHans Petter Selasky #endif /* MLX5_DRIVER_H */
1047