1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DEVICE_H 29 #define MLX5_DEVICE_H 30 31 #include <linux/types.h> 32 #include <rdma/ib_verbs.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define FW_INIT_TIMEOUT_MILI 2000 36 #define FW_INIT_WAIT_MS 2 37 38 #if defined(__LITTLE_ENDIAN) 39 #define MLX5_SET_HOST_ENDIANNESS 0 40 #elif defined(__BIG_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0x80 42 #else 43 #error Host endianness not defined 44 #endif 45 46 /* helper macros */ 47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 51 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 52 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 53 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 54 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 55 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 56 57 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 58 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 59 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 60 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 61 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 62 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 63 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 64 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 65 66 /* insert a value to a struct */ 67 #define MLX5_SET(typ, p, fld, v) do { \ 68 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 69 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73 << __mlx5_dw_bit_off(typ, fld))); \ 74 } while (0) 75 76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 82 << __mlx5_dw_bit_off(typ, fld))); \ 83 } while (0) 84 85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 87 __mlx5_mask(typ, fld)) 88 89 #define MLX5_GET_PR(typ, p, fld) ({ \ 90 u32 ___t = MLX5_GET(typ, p, fld); \ 91 pr_debug(#fld " = 0x%x\n", ___t); \ 92 ___t; \ 93 }) 94 95 #define MLX5_SET64(typ, p, fld, v) do { \ 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 99 } while (0) 100 101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 102 103 enum { 104 MLX5_MAX_COMMANDS = 32, 105 MLX5_CMD_DATA_BLOCK_SIZE = 512, 106 MLX5_CMD_MBOX_SIZE = 1024, 107 MLX5_PCI_CMD_XPORT = 7, 108 MLX5_MKEY_BSF_OCTO_SIZE = 4, 109 MLX5_MAX_PSVS = 4, 110 }; 111 112 enum { 113 MLX5_EXTENDED_UD_AV = 0x80000000, 114 }; 115 116 enum { 117 MLX5_CQ_FLAGS_OI = 2, 118 }; 119 120 enum { 121 MLX5_STAT_RATE_OFFSET = 5, 122 }; 123 124 enum { 125 MLX5_INLINE_SEG = 0x80000000, 126 }; 127 128 enum { 129 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 130 }; 131 132 enum { 133 MLX5_MIN_PKEY_TABLE_SIZE = 128, 134 MLX5_MAX_LOG_PKEY_TABLE = 5, 135 }; 136 137 enum { 138 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 139 }; 140 141 enum { 142 MLX5_PERM_LOCAL_READ = 1 << 2, 143 MLX5_PERM_LOCAL_WRITE = 1 << 3, 144 MLX5_PERM_REMOTE_READ = 1 << 4, 145 MLX5_PERM_REMOTE_WRITE = 1 << 5, 146 MLX5_PERM_ATOMIC = 1 << 6, 147 MLX5_PERM_UMR_EN = 1 << 7, 148 }; 149 150 enum { 151 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 152 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 153 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 154 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 155 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 156 }; 157 158 enum { 159 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 160 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 161 MLX5_MKEY_BSF_EN = 1 << 30, 162 MLX5_MKEY_LEN64 = 1 << 31, 163 }; 164 165 enum { 166 MLX5_EN_RD = (u64)1, 167 MLX5_EN_WR = (u64)2 168 }; 169 170 enum { 171 MLX5_BF_REGS_PER_PAGE = 4, 172 MLX5_MAX_UAR_PAGES = 1 << 8, 173 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 174 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 175 }; 176 177 enum { 178 MLX5_MKEY_MASK_LEN = 1ull << 0, 179 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 180 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 181 MLX5_MKEY_MASK_PD = 1ull << 7, 182 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 183 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 184 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 185 MLX5_MKEY_MASK_KEY = 1ull << 13, 186 MLX5_MKEY_MASK_QPN = 1ull << 14, 187 MLX5_MKEY_MASK_LR = 1ull << 17, 188 MLX5_MKEY_MASK_LW = 1ull << 18, 189 MLX5_MKEY_MASK_RR = 1ull << 19, 190 MLX5_MKEY_MASK_RW = 1ull << 20, 191 MLX5_MKEY_MASK_A = 1ull << 21, 192 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 193 MLX5_MKEY_MASK_FREE = 1ull << 29, 194 }; 195 196 enum { 197 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 198 199 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 200 MLX5_UMR_CHECK_FREE = (2 << 5), 201 202 MLX5_UMR_INLINE = (1 << 7), 203 }; 204 205 #define MLX5_UMR_MTT_ALIGNMENT 0x40 206 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 207 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 208 209 enum { 210 MLX5_EVENT_QUEUE_TYPE_QP = 0, 211 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 212 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 213 }; 214 215 enum { 216 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 217 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 218 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 219 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 220 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 221 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 222 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 223 }; 224 225 enum { 226 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 227 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 228 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 229 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 230 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 231 }; 232 233 enum { 234 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 235 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 236 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 237 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 238 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 239 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 240 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 241 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 242 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 243 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 244 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 245 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 246 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 247 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 248 }; 249 250 enum { 251 MLX5_ROCE_VERSION_1 = 0, 252 MLX5_ROCE_VERSION_1_5 = 1, 253 MLX5_ROCE_VERSION_2 = 2, 254 }; 255 256 enum { 257 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 258 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 259 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 260 }; 261 262 enum { 263 MLX5_ROCE_L3_TYPE_IPV4 = 0, 264 MLX5_ROCE_L3_TYPE_IPV6 = 1, 265 }; 266 267 enum { 268 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 269 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 270 }; 271 272 enum { 273 MLX5_OPCODE_NOP = 0x00, 274 MLX5_OPCODE_SEND_INVAL = 0x01, 275 MLX5_OPCODE_RDMA_WRITE = 0x08, 276 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 277 MLX5_OPCODE_SEND = 0x0a, 278 MLX5_OPCODE_SEND_IMM = 0x0b, 279 MLX5_OPCODE_LSO = 0x0e, 280 MLX5_OPCODE_RDMA_READ = 0x10, 281 MLX5_OPCODE_ATOMIC_CS = 0x11, 282 MLX5_OPCODE_ATOMIC_FA = 0x12, 283 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 284 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 285 MLX5_OPCODE_BIND_MW = 0x18, 286 MLX5_OPCODE_CONFIG_CMD = 0x1f, 287 288 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 289 MLX5_RECV_OPCODE_SEND = 0x01, 290 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 291 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 292 293 MLX5_CQE_OPCODE_ERROR = 0x1e, 294 MLX5_CQE_OPCODE_RESIZE = 0x16, 295 296 MLX5_OPCODE_SET_PSV = 0x20, 297 MLX5_OPCODE_GET_PSV = 0x21, 298 MLX5_OPCODE_CHECK_PSV = 0x22, 299 MLX5_OPCODE_RGET_PSV = 0x26, 300 MLX5_OPCODE_RCHECK_PSV = 0x27, 301 302 MLX5_OPCODE_UMR = 0x25, 303 304 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 305 }; 306 307 enum { 308 MLX5_SET_PORT_RESET_QKEY = 0, 309 MLX5_SET_PORT_GUID0 = 16, 310 MLX5_SET_PORT_NODE_GUID = 17, 311 MLX5_SET_PORT_SYS_GUID = 18, 312 MLX5_SET_PORT_GID_TABLE = 19, 313 MLX5_SET_PORT_PKEY_TABLE = 20, 314 }; 315 316 enum { 317 MLX5_MAX_PAGE_SHIFT = 31 318 }; 319 320 enum { 321 MLX5_ADAPTER_PAGE_SHIFT = 12, 322 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 323 }; 324 325 enum { 326 MLX5_CAP_OFF_CMDIF_CSUM = 46, 327 }; 328 329 struct mlx5_inbox_hdr { 330 __be16 opcode; 331 u8 rsvd[4]; 332 __be16 opmod; 333 }; 334 335 struct mlx5_outbox_hdr { 336 u8 status; 337 u8 rsvd[3]; 338 __be32 syndrome; 339 }; 340 341 struct mlx5_cmd_set_dc_cnak_mbox_in { 342 struct mlx5_inbox_hdr hdr; 343 u8 enable; 344 u8 reserved[47]; 345 __be64 pa; 346 }; 347 348 struct mlx5_cmd_set_dc_cnak_mbox_out { 349 struct mlx5_outbox_hdr hdr; 350 u8 rsvd[8]; 351 }; 352 353 struct mlx5_cmd_layout { 354 u8 type; 355 u8 rsvd0[3]; 356 __be32 inlen; 357 __be64 in_ptr; 358 __be32 in[4]; 359 __be32 out[4]; 360 __be64 out_ptr; 361 __be32 outlen; 362 u8 token; 363 u8 sig; 364 u8 rsvd1; 365 u8 status_own; 366 }; 367 368 369 struct mlx5_health_buffer { 370 __be32 assert_var[5]; 371 __be32 rsvd0[3]; 372 __be32 assert_exit_ptr; 373 __be32 assert_callra; 374 __be32 rsvd1[2]; 375 __be32 fw_ver; 376 __be32 hw_id; 377 __be32 rsvd2; 378 u8 irisc_index; 379 u8 synd; 380 __be16 ext_sync; 381 }; 382 383 struct mlx5_init_seg { 384 __be32 fw_rev; 385 __be32 cmdif_rev_fw_sub; 386 __be32 rsvd0[2]; 387 __be32 cmdq_addr_h; 388 __be32 cmdq_addr_l_sz; 389 __be32 cmd_dbell; 390 __be32 rsvd1[120]; 391 __be32 initializing; 392 struct mlx5_health_buffer health; 393 __be32 rsvd2[880]; 394 __be32 internal_timer_h; 395 __be32 internal_timer_l; 396 __be32 rsvd3[2]; 397 __be32 health_counter; 398 __be32 rsvd4[1019]; 399 __be64 ieee1588_clk; 400 __be32 ieee1588_clk_type; 401 __be32 clr_intx; 402 }; 403 404 struct mlx5_eqe_comp { 405 __be32 reserved[6]; 406 __be32 cqn; 407 }; 408 409 struct mlx5_eqe_qp_srq { 410 __be32 reserved[6]; 411 __be32 qp_srq_n; 412 }; 413 414 struct mlx5_eqe_cq_err { 415 __be32 cqn; 416 u8 reserved1[7]; 417 u8 syndrome; 418 }; 419 420 struct mlx5_eqe_port_state { 421 u8 reserved0[8]; 422 u8 port; 423 }; 424 425 struct mlx5_eqe_gpio { 426 __be32 reserved0[2]; 427 __be64 gpio_event; 428 }; 429 430 struct mlx5_eqe_congestion { 431 u8 type; 432 u8 rsvd0; 433 u8 congestion_level; 434 }; 435 436 struct mlx5_eqe_stall_vl { 437 u8 rsvd0[3]; 438 u8 port_vl; 439 }; 440 441 struct mlx5_eqe_cmd { 442 __be32 vector; 443 __be32 rsvd[6]; 444 }; 445 446 struct mlx5_eqe_page_req { 447 u8 rsvd0[2]; 448 __be16 func_id; 449 __be32 num_pages; 450 __be32 rsvd1[5]; 451 }; 452 453 struct mlx5_eqe_vport_change { 454 u8 rsvd0[2]; 455 __be16 vport_num; 456 __be32 rsvd1[6]; 457 }; 458 459 460 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 461 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 462 463 enum { 464 MLX5_MODULE_STATUS_PLUGGED = 0x1, 465 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 466 MLX5_MODULE_STATUS_ERROR = 0x3, 467 }; 468 469 enum { 470 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 471 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 472 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 473 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 474 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 475 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 0x5, 476 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 477 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 478 }; 479 480 struct mlx5_eqe_port_module_event { 481 u8 rsvd0; 482 u8 module; 483 u8 rsvd1; 484 u8 module_status; 485 u8 rsvd2[2]; 486 u8 error_type; 487 }; 488 489 union ev_data { 490 __be32 raw[7]; 491 struct mlx5_eqe_cmd cmd; 492 struct mlx5_eqe_comp comp; 493 struct mlx5_eqe_qp_srq qp_srq; 494 struct mlx5_eqe_cq_err cq_err; 495 struct mlx5_eqe_port_state port; 496 struct mlx5_eqe_gpio gpio; 497 struct mlx5_eqe_congestion cong; 498 struct mlx5_eqe_stall_vl stall_vl; 499 struct mlx5_eqe_page_req req_pages; 500 struct mlx5_eqe_port_module_event port_module_event; 501 struct mlx5_eqe_vport_change vport_change; 502 } __packed; 503 504 struct mlx5_eqe { 505 u8 rsvd0; 506 u8 type; 507 u8 rsvd1; 508 u8 sub_type; 509 __be32 rsvd2[7]; 510 union ev_data data; 511 __be16 rsvd3; 512 u8 signature; 513 u8 owner; 514 } __packed; 515 516 struct mlx5_cmd_prot_block { 517 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 518 u8 rsvd0[48]; 519 __be64 next; 520 __be32 block_num; 521 u8 rsvd1; 522 u8 token; 523 u8 ctrl_sig; 524 u8 sig; 525 }; 526 527 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 528 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 529 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 530 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 531 532 enum { 533 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 534 }; 535 536 struct mlx5_err_cqe { 537 u8 rsvd0[32]; 538 __be32 srqn; 539 u8 rsvd1[18]; 540 u8 vendor_err_synd; 541 u8 syndrome; 542 __be32 s_wqe_opcode_qpn; 543 __be16 wqe_counter; 544 u8 signature; 545 u8 op_own; 546 }; 547 548 struct mlx5_cqe64 { 549 u8 tunneled_etc; 550 u8 rsvd0[3]; 551 u8 lro_tcppsh_abort_dupack; 552 u8 lro_min_ttl; 553 __be16 lro_tcp_win; 554 __be32 lro_ack_seq_num; 555 __be32 rss_hash_result; 556 u8 rss_hash_type; 557 u8 ml_path; 558 u8 rsvd20[2]; 559 __be16 check_sum; 560 __be16 slid; 561 __be32 flags_rqpn; 562 u8 hds_ip_ext; 563 u8 l4_hdr_type_etc; 564 __be16 vlan_info; 565 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 566 __be32 imm_inval_pkey; 567 u8 rsvd40[4]; 568 __be32 byte_cnt; 569 __be64 timestamp; 570 __be32 sop_drop_qpn; 571 __be16 wqe_counter; 572 u8 signature; 573 u8 op_own; 574 }; 575 576 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 577 { 578 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 579 } 580 581 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 582 { 583 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 584 } 585 586 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 587 { 588 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 589 } 590 591 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 592 { 593 return be16_to_cpu(cqe->vlan_info) & 0xfff; 594 } 595 596 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 597 { 598 memcpy(smac, &cqe->rss_hash_type , 4); 599 memcpy(smac + 4, &cqe->slid , 2); 600 } 601 602 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 603 { 604 return cqe->l4_hdr_type_etc & 0x1; 605 } 606 607 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 608 { 609 return cqe->tunneled_etc & 0x1; 610 } 611 612 enum { 613 CQE_L4_HDR_TYPE_NONE = 0x0, 614 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 615 CQE_L4_HDR_TYPE_UDP = 0x2, 616 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 617 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 618 }; 619 620 enum { 621 /* source L3 hash types */ 622 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 623 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 624 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 625 626 /* destination L3 hash types */ 627 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 628 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 629 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 630 631 /* source L4 hash types */ 632 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 633 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 634 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 635 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 636 637 /* destination L4 hash types */ 638 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 639 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 640 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 641 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 642 }; 643 644 enum { 645 CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 646 CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 647 CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 648 }; 649 650 enum { 651 CQE_L2_OK = 1 << 0, 652 CQE_L3_OK = 1 << 1, 653 CQE_L4_OK = 1 << 2, 654 }; 655 656 struct mlx5_sig_err_cqe { 657 u8 rsvd0[16]; 658 __be32 expected_trans_sig; 659 __be32 actual_trans_sig; 660 __be32 expected_reftag; 661 __be32 actual_reftag; 662 __be16 syndrome; 663 u8 rsvd22[2]; 664 __be32 mkey; 665 __be64 err_offset; 666 u8 rsvd30[8]; 667 __be32 qpn; 668 u8 rsvd38[2]; 669 u8 signature; 670 u8 op_own; 671 }; 672 673 struct mlx5_wqe_srq_next_seg { 674 u8 rsvd0[2]; 675 __be16 next_wqe_index; 676 u8 signature; 677 u8 rsvd1[11]; 678 }; 679 680 union mlx5_ext_cqe { 681 struct ib_grh grh; 682 u8 inl[64]; 683 }; 684 685 struct mlx5_cqe128 { 686 union mlx5_ext_cqe inl_grh; 687 struct mlx5_cqe64 cqe64; 688 }; 689 690 struct mlx5_srq_ctx { 691 u8 state_log_sz; 692 u8 rsvd0[3]; 693 __be32 flags_xrcd; 694 __be32 pgoff_cqn; 695 u8 rsvd1[4]; 696 u8 log_pg_sz; 697 u8 rsvd2[7]; 698 __be32 pd; 699 __be16 lwm; 700 __be16 wqe_cnt; 701 u8 rsvd3[8]; 702 __be64 db_record; 703 }; 704 705 struct mlx5_create_srq_mbox_in { 706 struct mlx5_inbox_hdr hdr; 707 __be32 input_srqn; 708 u8 rsvd0[4]; 709 struct mlx5_srq_ctx ctx; 710 u8 rsvd1[208]; 711 __be64 pas[0]; 712 }; 713 714 struct mlx5_create_srq_mbox_out { 715 struct mlx5_outbox_hdr hdr; 716 __be32 srqn; 717 u8 rsvd[4]; 718 }; 719 720 struct mlx5_destroy_srq_mbox_in { 721 struct mlx5_inbox_hdr hdr; 722 __be32 srqn; 723 u8 rsvd[4]; 724 }; 725 726 struct mlx5_destroy_srq_mbox_out { 727 struct mlx5_outbox_hdr hdr; 728 u8 rsvd[8]; 729 }; 730 731 struct mlx5_query_srq_mbox_in { 732 struct mlx5_inbox_hdr hdr; 733 __be32 srqn; 734 u8 rsvd0[4]; 735 }; 736 737 struct mlx5_query_srq_mbox_out { 738 struct mlx5_outbox_hdr hdr; 739 u8 rsvd0[8]; 740 struct mlx5_srq_ctx ctx; 741 u8 rsvd1[32]; 742 __be64 pas[0]; 743 }; 744 745 struct mlx5_arm_srq_mbox_in { 746 struct mlx5_inbox_hdr hdr; 747 __be32 srqn; 748 __be16 rsvd; 749 __be16 lwm; 750 }; 751 752 struct mlx5_arm_srq_mbox_out { 753 struct mlx5_outbox_hdr hdr; 754 u8 rsvd[8]; 755 }; 756 757 struct mlx5_cq_context { 758 u8 status; 759 u8 cqe_sz_flags; 760 u8 st; 761 u8 rsvd3; 762 u8 rsvd4[6]; 763 __be16 page_offset; 764 __be32 log_sz_usr_page; 765 __be16 cq_period; 766 __be16 cq_max_count; 767 __be16 rsvd20; 768 __be16 c_eqn; 769 u8 log_pg_sz; 770 u8 rsvd25[7]; 771 __be32 last_notified_index; 772 __be32 solicit_producer_index; 773 __be32 consumer_counter; 774 __be32 producer_counter; 775 u8 rsvd48[8]; 776 __be64 db_record_addr; 777 }; 778 779 struct mlx5_create_cq_mbox_in { 780 struct mlx5_inbox_hdr hdr; 781 __be32 input_cqn; 782 u8 rsvdx[4]; 783 struct mlx5_cq_context ctx; 784 u8 rsvd6[192]; 785 __be64 pas[0]; 786 }; 787 788 struct mlx5_create_cq_mbox_out { 789 struct mlx5_outbox_hdr hdr; 790 __be32 cqn; 791 u8 rsvd0[4]; 792 }; 793 794 struct mlx5_destroy_cq_mbox_in { 795 struct mlx5_inbox_hdr hdr; 796 __be32 cqn; 797 u8 rsvd0[4]; 798 }; 799 800 struct mlx5_destroy_cq_mbox_out { 801 struct mlx5_outbox_hdr hdr; 802 u8 rsvd0[8]; 803 }; 804 805 struct mlx5_query_cq_mbox_in { 806 struct mlx5_inbox_hdr hdr; 807 __be32 cqn; 808 u8 rsvd0[4]; 809 }; 810 811 struct mlx5_query_cq_mbox_out { 812 struct mlx5_outbox_hdr hdr; 813 u8 rsvd0[8]; 814 struct mlx5_cq_context ctx; 815 u8 rsvd6[16]; 816 __be64 pas[0]; 817 }; 818 819 struct mlx5_modify_cq_mbox_in { 820 struct mlx5_inbox_hdr hdr; 821 __be32 cqn; 822 __be32 field_select; 823 struct mlx5_cq_context ctx; 824 u8 rsvd[192]; 825 __be64 pas[0]; 826 }; 827 828 struct mlx5_modify_cq_mbox_out { 829 struct mlx5_outbox_hdr hdr; 830 u8 rsvd[8]; 831 }; 832 833 struct mlx5_eq_context { 834 u8 status; 835 u8 ec_oi; 836 u8 st; 837 u8 rsvd2[7]; 838 __be16 page_pffset; 839 __be32 log_sz_usr_page; 840 u8 rsvd3[7]; 841 u8 intr; 842 u8 log_page_size; 843 u8 rsvd4[15]; 844 __be32 consumer_counter; 845 __be32 produser_counter; 846 u8 rsvd5[16]; 847 }; 848 849 struct mlx5_create_eq_mbox_in { 850 struct mlx5_inbox_hdr hdr; 851 u8 rsvd0[3]; 852 u8 input_eqn; 853 u8 rsvd1[4]; 854 struct mlx5_eq_context ctx; 855 u8 rsvd2[8]; 856 __be64 events_mask; 857 u8 rsvd3[176]; 858 __be64 pas[0]; 859 }; 860 861 struct mlx5_create_eq_mbox_out { 862 struct mlx5_outbox_hdr hdr; 863 u8 rsvd0[3]; 864 u8 eq_number; 865 u8 rsvd1[4]; 866 }; 867 868 struct mlx5_map_eq_mbox_in { 869 struct mlx5_inbox_hdr hdr; 870 __be64 mask; 871 u8 mu; 872 u8 rsvd0[2]; 873 u8 eqn; 874 u8 rsvd1[24]; 875 }; 876 877 struct mlx5_map_eq_mbox_out { 878 struct mlx5_outbox_hdr hdr; 879 u8 rsvd[8]; 880 }; 881 882 struct mlx5_query_eq_mbox_in { 883 struct mlx5_inbox_hdr hdr; 884 u8 rsvd0[3]; 885 u8 eqn; 886 u8 rsvd1[4]; 887 }; 888 889 struct mlx5_query_eq_mbox_out { 890 struct mlx5_outbox_hdr hdr; 891 u8 rsvd[8]; 892 struct mlx5_eq_context ctx; 893 }; 894 895 enum { 896 MLX5_MKEY_STATUS_FREE = 1 << 6, 897 }; 898 899 struct mlx5_mkey_seg { 900 /* This is a two bit field occupying bits 31-30. 901 * bit 31 is always 0, 902 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 903 */ 904 u8 status; 905 u8 pcie_control; 906 u8 flags; 907 u8 version; 908 __be32 qpn_mkey7_0; 909 u8 rsvd1[4]; 910 __be32 flags_pd; 911 __be64 start_addr; 912 __be64 len; 913 __be32 bsfs_octo_size; 914 u8 rsvd2[16]; 915 __be32 xlt_oct_size; 916 u8 rsvd3[3]; 917 u8 log2_page_size; 918 u8 rsvd4[4]; 919 }; 920 921 struct mlx5_query_special_ctxs_mbox_in { 922 struct mlx5_inbox_hdr hdr; 923 u8 rsvd[8]; 924 }; 925 926 struct mlx5_query_special_ctxs_mbox_out { 927 struct mlx5_outbox_hdr hdr; 928 __be32 dump_fill_mkey; 929 __be32 reserved_lkey; 930 }; 931 932 struct mlx5_create_mkey_mbox_in { 933 struct mlx5_inbox_hdr hdr; 934 __be32 input_mkey_index; 935 __be32 flags; 936 struct mlx5_mkey_seg seg; 937 u8 rsvd1[16]; 938 __be32 xlat_oct_act_size; 939 __be32 rsvd2; 940 u8 rsvd3[168]; 941 __be64 pas[0]; 942 }; 943 944 struct mlx5_create_mkey_mbox_out { 945 struct mlx5_outbox_hdr hdr; 946 __be32 mkey; 947 u8 rsvd[4]; 948 }; 949 950 struct mlx5_query_mkey_mbox_in { 951 struct mlx5_inbox_hdr hdr; 952 __be32 mkey; 953 }; 954 955 struct mlx5_query_mkey_mbox_out { 956 struct mlx5_outbox_hdr hdr; 957 __be64 pas[0]; 958 }; 959 960 struct mlx5_modify_mkey_mbox_in { 961 struct mlx5_inbox_hdr hdr; 962 __be32 mkey; 963 __be64 pas[0]; 964 }; 965 966 struct mlx5_modify_mkey_mbox_out { 967 struct mlx5_outbox_hdr hdr; 968 u8 rsvd[8]; 969 }; 970 971 struct mlx5_dump_mkey_mbox_in { 972 struct mlx5_inbox_hdr hdr; 973 }; 974 975 struct mlx5_dump_mkey_mbox_out { 976 struct mlx5_outbox_hdr hdr; 977 __be32 mkey; 978 }; 979 980 struct mlx5_mad_ifc_mbox_in { 981 struct mlx5_inbox_hdr hdr; 982 __be16 remote_lid; 983 u8 rsvd0; 984 u8 port; 985 u8 rsvd1[4]; 986 u8 data[256]; 987 }; 988 989 struct mlx5_mad_ifc_mbox_out { 990 struct mlx5_outbox_hdr hdr; 991 u8 rsvd[8]; 992 u8 data[256]; 993 }; 994 995 struct mlx5_access_reg_mbox_in { 996 struct mlx5_inbox_hdr hdr; 997 u8 rsvd0[2]; 998 __be16 register_id; 999 __be32 arg; 1000 __be32 data[0]; 1001 }; 1002 1003 struct mlx5_access_reg_mbox_out { 1004 struct mlx5_outbox_hdr hdr; 1005 u8 rsvd[8]; 1006 __be32 data[0]; 1007 }; 1008 1009 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1010 1011 enum { 1012 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1013 }; 1014 1015 struct mlx5_allocate_psv_in { 1016 struct mlx5_inbox_hdr hdr; 1017 __be32 npsv_pd; 1018 __be32 rsvd_psv0; 1019 }; 1020 1021 struct mlx5_allocate_psv_out { 1022 struct mlx5_outbox_hdr hdr; 1023 u8 rsvd[8]; 1024 __be32 psv_idx[4]; 1025 }; 1026 1027 struct mlx5_destroy_psv_in { 1028 struct mlx5_inbox_hdr hdr; 1029 __be32 psv_number; 1030 u8 rsvd[4]; 1031 }; 1032 1033 struct mlx5_destroy_psv_out { 1034 struct mlx5_outbox_hdr hdr; 1035 u8 rsvd[8]; 1036 }; 1037 1038 static inline int mlx5_host_is_le(void) 1039 { 1040 #if defined(__LITTLE_ENDIAN) 1041 return 1; 1042 #elif defined(__BIG_ENDIAN) 1043 return 0; 1044 #else 1045 #error Host endianness not defined 1046 #endif 1047 } 1048 1049 #define MLX5_CMD_OP_MAX 0x939 1050 1051 enum { 1052 VPORT_STATE_DOWN = 0x0, 1053 VPORT_STATE_UP = 0x1, 1054 }; 1055 1056 enum { 1057 MLX5_L3_PROT_TYPE_IPV4 = 0, 1058 MLX5_L3_PROT_TYPE_IPV6 = 1, 1059 }; 1060 1061 enum { 1062 MLX5_L4_PROT_TYPE_TCP = 0, 1063 MLX5_L4_PROT_TYPE_UDP = 1, 1064 }; 1065 1066 enum { 1067 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1068 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1069 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1070 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1071 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1072 }; 1073 1074 enum { 1075 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1076 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1077 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1078 1079 }; 1080 1081 enum { 1082 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1083 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 1084 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 1085 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1086 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 1087 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 1088 }; 1089 1090 enum { 1091 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 1092 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 1093 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 1094 }; 1095 1096 enum { 1097 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 1098 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 1099 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 1100 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 1101 }; 1102 1103 enum { 1104 MLX5_UC_ADDR_CHANGE = (1 << 0), 1105 MLX5_MC_ADDR_CHANGE = (1 << 1), 1106 MLX5_VLAN_CHANGE = (1 << 2), 1107 MLX5_PROMISC_CHANGE = (1 << 3), 1108 MLX5_MTU_CHANGE = (1 << 4), 1109 }; 1110 1111 enum mlx5_list_type { 1112 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 1113 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 1114 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 1115 }; 1116 1117 enum { 1118 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 1119 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 1120 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 1121 }; 1122 1123 /* MLX5 DEV CAPs */ 1124 1125 /* TODO: EAT.ME */ 1126 enum mlx5_cap_mode { 1127 HCA_CAP_OPMOD_GET_MAX = 0, 1128 HCA_CAP_OPMOD_GET_CUR = 1, 1129 }; 1130 1131 enum mlx5_cap_type { 1132 MLX5_CAP_GENERAL = 0, 1133 MLX5_CAP_ETHERNET_OFFLOADS, 1134 MLX5_CAP_ODP, 1135 MLX5_CAP_ATOMIC, 1136 MLX5_CAP_ROCE, 1137 MLX5_CAP_IPOIB_OFFLOADS, 1138 MLX5_CAP_EOIB_OFFLOADS, 1139 MLX5_CAP_FLOW_TABLE, 1140 MLX5_CAP_ESWITCH_FLOW_TABLE, 1141 MLX5_CAP_ESWITCH, 1142 MLX5_CAP_SNAPSHOT, 1143 MLX5_CAP_VECTOR_CALC, 1144 MLX5_CAP_QOS, 1145 MLX5_CAP_DEBUG, 1146 /* NUM OF CAP Types */ 1147 MLX5_CAP_NUM 1148 }; 1149 1150 /* GET Dev Caps macros */ 1151 #define MLX5_CAP_GEN(mdev, cap) \ 1152 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1153 1154 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1155 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1156 1157 #define MLX5_CAP_ETH(mdev, cap) \ 1158 MLX5_GET(per_protocol_networking_offload_caps,\ 1159 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1160 1161 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1162 MLX5_GET(per_protocol_networking_offload_caps,\ 1163 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1164 1165 #define MLX5_CAP_ROCE(mdev, cap) \ 1166 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1167 1168 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1169 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1170 1171 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1172 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1173 1174 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1175 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1176 1177 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1178 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1179 1180 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1181 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1182 1183 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1184 MLX5_GET(flow_table_eswitch_cap, \ 1185 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1186 1187 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1188 MLX5_GET(flow_table_eswitch_cap, \ 1189 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1190 1191 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1192 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1193 1194 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1195 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1196 1197 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1198 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1199 1200 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1201 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1202 1203 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1204 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1205 1206 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1207 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1208 1209 #define MLX5_CAP_ESW(mdev, cap) \ 1210 MLX5_GET(e_switch_cap, \ 1211 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1212 1213 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1214 MLX5_GET(e_switch_cap, \ 1215 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1216 1217 #define MLX5_CAP_ODP(mdev, cap)\ 1218 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1219 1220 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1221 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1222 1223 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1224 MLX5_GET(snapshot_cap, \ 1225 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1226 1227 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1228 MLX5_GET(snapshot_cap, \ 1229 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1230 1231 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1232 MLX5_GET(per_protocol_networking_offload_caps,\ 1233 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1234 1235 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1236 MLX5_GET(per_protocol_networking_offload_caps,\ 1237 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1238 1239 #define MLX5_CAP_DEBUG(mdev, cap) \ 1240 MLX5_GET(debug_cap, \ 1241 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1242 1243 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1244 MLX5_GET(debug_cap, \ 1245 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1246 1247 #define MLX5_CAP_QOS(mdev, cap) \ 1248 MLX5_GET(qos_cap,\ 1249 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1250 1251 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 1252 MLX5_GET(qos_cap,\ 1253 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1254 1255 enum { 1256 MLX5_CMD_STAT_OK = 0x0, 1257 MLX5_CMD_STAT_INT_ERR = 0x1, 1258 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1259 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1260 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1261 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1262 MLX5_CMD_STAT_RES_BUSY = 0x6, 1263 MLX5_CMD_STAT_LIM_ERR = 0x8, 1264 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1265 MLX5_CMD_STAT_IX_ERR = 0xa, 1266 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1267 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1268 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1269 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1270 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1271 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1272 }; 1273 1274 enum { 1275 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1276 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1277 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1278 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1279 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1280 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1281 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1282 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1283 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1284 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1285 }; 1286 1287 enum { 1288 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1289 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1290 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1291 }; 1292 1293 enum { 1294 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1295 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1296 }; 1297 1298 enum { 1299 NUM_DRIVER_UARS = 4, 1300 NUM_LOW_LAT_UUARS = 4, 1301 }; 1302 1303 enum { 1304 MLX5_CAP_PORT_TYPE_IB = 0x0, 1305 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1306 }; 1307 1308 enum { 1309 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1310 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1311 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1312 }; 1313 1314 enum { 1315 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1316 }; 1317 1318 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1319 { 1320 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1321 return 0; 1322 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1323 } 1324 1325 struct mlx5_ifc_mcia_reg_bits { 1326 u8 l[0x1]; 1327 u8 reserved_0[0x7]; 1328 u8 module[0x8]; 1329 u8 reserved_1[0x8]; 1330 u8 status[0x8]; 1331 1332 u8 i2c_device_address[0x8]; 1333 u8 page_number[0x8]; 1334 u8 device_address[0x10]; 1335 1336 u8 reserved_2[0x10]; 1337 u8 size[0x10]; 1338 1339 u8 reserved_3[0x20]; 1340 1341 u8 dword_0[0x20]; 1342 u8 dword_1[0x20]; 1343 u8 dword_2[0x20]; 1344 u8 dword_3[0x20]; 1345 u8 dword_4[0x20]; 1346 u8 dword_5[0x20]; 1347 u8 dword_6[0x20]; 1348 u8 dword_7[0x20]; 1349 u8 dword_8[0x20]; 1350 u8 dword_9[0x20]; 1351 u8 dword_10[0x20]; 1352 u8 dword_11[0x20]; 1353 }; 1354 1355 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1356 1357 struct mlx5_mini_cqe8 { 1358 union { 1359 __be32 rx_hash_result; 1360 __be16 checksum; 1361 __be16 rsvd; 1362 struct { 1363 __be16 wqe_counter; 1364 u8 s_wqe_opcode; 1365 u8 reserved; 1366 } s_wqe_info; 1367 }; 1368 __be32 byte_cnt; 1369 }; 1370 1371 enum { 1372 MLX5_NO_INLINE_DATA, 1373 MLX5_INLINE_DATA32_SEG, 1374 MLX5_INLINE_DATA64_SEG, 1375 MLX5_COMPRESSED, 1376 }; 1377 1378 enum mlx5_exp_cqe_zip_recv_type { 1379 MLX5_CQE_FORMAT_HASH, 1380 MLX5_CQE_FORMAT_CSUM, 1381 }; 1382 1383 #define MLX5E_CQE_FORMAT_MASK 0xc 1384 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1385 { 1386 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1387 } 1388 1389 /* 8 regular priorities + 1 for multicast */ 1390 #define MLX5_NUM_BYPASS_FTS 9 1391 1392 #endif /* MLX5_DEVICE_H */ 1393