1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef MLX5_DEVICE_H 27 #define MLX5_DEVICE_H 28 29 #include <linux/types.h> 30 #include <rdma/ib_verbs.h> 31 #include <dev/mlx5/mlx5_ifc.h> 32 33 #define FW_INIT_TIMEOUT_MILI 2000 34 #define FW_INIT_WAIT_MS 2 35 #define FW_PRE_INIT_TIMEOUT_MILI 120000 36 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 37 38 #if defined(__LITTLE_ENDIAN) 39 #define MLX5_SET_HOST_ENDIANNESS 0 40 #elif defined(__BIG_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0x80 42 #else 43 #error Host endianness not defined 44 #endif 45 46 /* helper macros */ 47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 59 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 60 61 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 62 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 63 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 64 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 65 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 66 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 67 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 68 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 69 70 /* insert a value to a struct */ 71 #define MLX5_SET(typ, p, fld, v) do { \ 72 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 73 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 74 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 75 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 76 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 77 << __mlx5_dw_bit_off(typ, fld))); \ 78 } while (0) 79 80 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 81 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 82 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 83 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 84 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 85 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 86 << __mlx5_dw_bit_off(typ, fld))); \ 87 } while (0) 88 89 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 90 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 91 __mlx5_mask(typ, fld)) 92 93 #define MLX5_GET_PR(typ, p, fld) ({ \ 94 u32 ___t = MLX5_GET(typ, p, fld); \ 95 pr_debug(#fld " = 0x%x\n", ___t); \ 96 ___t; \ 97 }) 98 99 #define __MLX5_SET64(typ, p, fld, v) do { \ 100 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 101 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 102 } while (0) 103 104 #define MLX5_SET64(typ, p, fld, v) do { \ 105 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 106 __MLX5_SET64(typ, p, fld, v); \ 107 } while (0) 108 109 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 110 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 111 __MLX5_SET64(typ, p, fld[idx], v); \ 112 } while (0) 113 114 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 115 116 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 117 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 118 __mlx5_mask16(typ, fld)) 119 120 #define MLX5_SET16(typ, p, fld, v) do { \ 121 u16 _v = v; \ 122 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 123 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 124 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 125 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 126 << __mlx5_16_bit_off(typ, fld))); \ 127 } while (0) 128 129 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 130 __mlx5_64_off(typ, fld))) 131 132 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 133 type_t tmp; \ 134 switch (sizeof(tmp)) { \ 135 case sizeof(u8): \ 136 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 137 break; \ 138 case sizeof(u16): \ 139 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 140 break; \ 141 case sizeof(u32): \ 142 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 143 break; \ 144 case sizeof(u64): \ 145 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 146 break; \ 147 } \ 148 tmp; \ 149 }) 150 151 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2 152 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1 153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 159 160 /* insert a value to a struct */ 161 #define MLX5_VSC_SET(typ, p, fld, v) do { \ 162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 167 << __mlx5_dw_bit_off(typ, fld))); \ 168 } while (0) 169 170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 172 __mlx5_mask(typ, fld)) 173 174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 176 pr_debug(#fld " = 0x%x\n", ___t); \ 177 ___t; \ 178 }) 179 180 enum { 181 MLX5_MAX_COMMANDS = 32, 182 MLX5_CMD_DATA_BLOCK_SIZE = 512, 183 MLX5_CMD_MBOX_SIZE = 1024, 184 MLX5_PCI_CMD_XPORT = 7, 185 MLX5_MKEY_BSF_OCTO_SIZE = 4, 186 MLX5_MAX_PSVS = 4, 187 }; 188 189 enum { 190 MLX5_EXTENDED_UD_AV = 0x80000000, 191 }; 192 193 enum { 194 MLX5_CQ_FLAGS_OI = 2, 195 }; 196 197 enum { 198 MLX5_STAT_RATE_OFFSET = 5, 199 }; 200 201 enum { 202 MLX5_INLINE_SEG = 0x80000000, 203 }; 204 205 enum { 206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 207 }; 208 209 enum { 210 MLX5_MIN_PKEY_TABLE_SIZE = 128, 211 MLX5_MAX_LOG_PKEY_TABLE = 5, 212 }; 213 214 enum { 215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31 216 }; 217 218 enum { 219 MLX5_PERM_LOCAL_READ = 1 << 2, 220 MLX5_PERM_LOCAL_WRITE = 1 << 3, 221 MLX5_PERM_REMOTE_READ = 1 << 4, 222 MLX5_PERM_REMOTE_WRITE = 1 << 5, 223 MLX5_PERM_ATOMIC = 1 << 6, 224 MLX5_PERM_UMR_EN = 1 << 7, 225 }; 226 227 enum { 228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 233 }; 234 235 enum { 236 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 238 MLX5_MKEY_BSF_EN = 1 << 30, 239 MLX5_MKEY_LEN64 = 1U << 31, 240 }; 241 242 enum { 243 MLX5_EN_RD = (u64)1, 244 MLX5_EN_WR = (u64)2 245 }; 246 247 enum { 248 MLX5_ADAPTER_PAGE_SHIFT = 12, 249 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 250 }; 251 252 enum { 253 MLX5_BFREGS_PER_UAR = 4, 254 MLX5_MAX_UARS = 1 << 8, 255 MLX5_NON_FP_BFREGS_PER_UAR = 2, 256 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 257 MLX5_NON_FP_BFREGS_PER_UAR, 258 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 259 MLX5_NON_FP_BFREGS_PER_UAR, 260 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 261 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 262 MLX5_MIN_DYN_BFREGS = 512, 263 MLX5_MAX_DYN_BFREGS = 1024, 264 }; 265 266 enum { 267 MLX5_MKEY_MASK_LEN = 1ull << 0, 268 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 269 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 270 MLX5_MKEY_MASK_PD = 1ull << 7, 271 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 272 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 273 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 274 MLX5_MKEY_MASK_KEY = 1ull << 13, 275 MLX5_MKEY_MASK_QPN = 1ull << 14, 276 MLX5_MKEY_MASK_LR = 1ull << 17, 277 MLX5_MKEY_MASK_LW = 1ull << 18, 278 MLX5_MKEY_MASK_RR = 1ull << 19, 279 MLX5_MKEY_MASK_RW = 1ull << 20, 280 MLX5_MKEY_MASK_A = 1ull << 21, 281 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 282 MLX5_MKEY_MASK_FREE = 1ull << 29, 283 }; 284 285 enum { 286 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 287 288 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 289 MLX5_UMR_CHECK_FREE = (2 << 5), 290 291 MLX5_UMR_INLINE = (1 << 7), 292 }; 293 294 #define MLX5_UMR_MTT_ALIGNMENT 0x40 295 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 296 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 297 298 enum { 299 MLX5_EVENT_QUEUE_TYPE_QP = 0, 300 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 301 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 302 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 303 }; 304 305 enum { 306 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 307 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 308 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 309 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 310 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 311 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 312 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 313 }; 314 315 enum { 316 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 317 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 318 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 319 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 320 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 321 }; 322 323 enum { 324 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 325 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 326 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 327 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 328 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 329 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 330 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 331 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 332 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 333 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 334 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 335 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 336 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 337 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 338 }; 339 340 enum { 341 MLX5_ROCE_VERSION_1 = 0, 342 MLX5_ROCE_VERSION_1_5 = 1, 343 MLX5_ROCE_VERSION_2 = 2, 344 }; 345 346 enum { 347 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 348 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 349 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 350 }; 351 352 enum { 353 MLX5_ROCE_L3_TYPE_IPV4 = 0, 354 MLX5_ROCE_L3_TYPE_IPV6 = 1, 355 }; 356 357 enum { 358 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 359 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 360 }; 361 362 enum { 363 MLX5_OPCODE_NOP = 0x00, 364 MLX5_OPCODE_SEND_INVAL = 0x01, 365 MLX5_OPCODE_RDMA_WRITE = 0x08, 366 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 367 MLX5_OPCODE_SEND = 0x0a, 368 MLX5_OPCODE_SEND_IMM = 0x0b, 369 MLX5_OPCODE_LSO = 0x0e, 370 MLX5_OPCODE_RDMA_READ = 0x10, 371 MLX5_OPCODE_ATOMIC_CS = 0x11, 372 MLX5_OPCODE_ATOMIC_FA = 0x12, 373 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 374 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 375 MLX5_OPCODE_BIND_MW = 0x18, 376 MLX5_OPCODE_CONFIG_CMD = 0x1f, 377 MLX5_OPCODE_DUMP = 0x23, 378 379 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 380 MLX5_RECV_OPCODE_SEND = 0x01, 381 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 382 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 383 384 MLX5_CQE_OPCODE_ERROR = 0x1e, 385 MLX5_CQE_OPCODE_RESIZE = 0x16, 386 387 MLX5_OPCODE_SET_PSV = 0x20, 388 MLX5_OPCODE_GET_PSV = 0x21, 389 MLX5_OPCODE_CHECK_PSV = 0x22, 390 MLX5_OPCODE_RGET_PSV = 0x26, 391 MLX5_OPCODE_RCHECK_PSV = 0x27, 392 393 MLX5_OPCODE_UMR = 0x25, 394 MLX5_OPCODE_QOS_REMAP = 0x2a, 395 396 MLX5_OPCODE_ACCESS_ASO = 0x2d, 397 398 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 399 }; 400 401 enum { 402 MLX5_OPCODE_MOD_UMR_UMR = 0x0, 403 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1, 404 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2, 405 }; 406 407 enum { 408 MLX5_OPCODE_MOD_PSV_PSV = 0x0, 409 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1, 410 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2, 411 }; 412 413 struct mlx5_wqe_tls_static_params_seg { 414 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; 415 }; 416 417 struct mlx5_wqe_tls_progress_params_seg { 418 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; 419 } __aligned(64); 420 421 enum { 422 MLX5_SET_PORT_RESET_QKEY = 0, 423 MLX5_SET_PORT_GUID0 = 16, 424 MLX5_SET_PORT_NODE_GUID = 17, 425 MLX5_SET_PORT_SYS_GUID = 18, 426 MLX5_SET_PORT_GID_TABLE = 19, 427 MLX5_SET_PORT_PKEY_TABLE = 20, 428 }; 429 430 enum { 431 MLX5_MAX_PAGE_SHIFT = 31 432 }; 433 434 enum { 435 MLX5_CAP_OFF_CMDIF_CSUM = 46, 436 }; 437 438 enum { 439 /* 440 * Max wqe size for rdma read is 512 bytes, so this 441 * limits our max_sge_rd as the wqe needs to fit: 442 * - ctrl segment (16 bytes) 443 * - rdma segment (16 bytes) 444 * - scatter elements (16 bytes each) 445 */ 446 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 447 }; 448 449 struct mlx5_cmd_layout { 450 u8 type; 451 u8 rsvd0[3]; 452 __be32 inlen; 453 __be64 in_ptr; 454 __be32 in[4]; 455 __be32 out[4]; 456 __be64 out_ptr; 457 __be32 outlen; 458 u8 token; 459 u8 sig; 460 u8 rsvd1; 461 u8 status_own; 462 }; 463 464 enum mlx5_fatal_assert_bit_offsets { 465 MLX5_RFR_OFFSET = 31, 466 }; 467 468 struct mlx5_health_buffer { 469 __be32 assert_var[5]; 470 __be32 rsvd0[3]; 471 __be32 assert_exit_ptr; 472 __be32 assert_callra; 473 __be32 rsvd1[2]; 474 __be32 fw_ver; 475 __be32 hw_id; 476 __be32 rfr; 477 u8 irisc_index; 478 u8 synd; 479 __be16 ext_synd; 480 }; 481 482 enum mlx5_initializing_bit_offsets { 483 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 484 }; 485 486 enum mlx5_cmd_addr_l_sz_offset { 487 MLX5_NIC_IFC_OFFSET = 8, 488 }; 489 490 struct mlx5_init_seg { 491 __be32 fw_rev; 492 __be32 cmdif_rev_fw_sub; 493 __be32 rsvd0[2]; 494 __be32 cmdq_addr_h; 495 __be32 cmdq_addr_l_sz; 496 __be32 cmd_dbell; 497 __be32 rsvd1[120]; 498 __be32 initializing; 499 struct mlx5_health_buffer health; 500 __be32 rsvd2[880]; 501 __be32 internal_timer_h; 502 __be32 internal_timer_l; 503 __be32 rsvd3[2]; 504 __be32 health_counter; 505 __be32 rsvd4[1019]; 506 __be64 ieee1588_clk; 507 __be32 ieee1588_clk_type; 508 __be32 clr_intx; 509 }; 510 511 struct mlx5_eqe_comp { 512 __be32 reserved[6]; 513 __be32 cqn; 514 }; 515 516 struct mlx5_eqe_qp_srq { 517 __be32 reserved1[5]; 518 u8 type; 519 u8 reserved2[3]; 520 __be32 qp_srq_n; 521 }; 522 523 struct mlx5_eqe_cq_err { 524 __be32 cqn; 525 u8 reserved1[7]; 526 u8 syndrome; 527 }; 528 529 struct mlx5_eqe_xrq_err { 530 __be32 reserved1[5]; 531 __be32 type_xrqn; 532 __be32 reserved2; 533 }; 534 535 struct mlx5_eqe_port_state { 536 u8 reserved0[8]; 537 u8 port; 538 }; 539 540 struct mlx5_eqe_gpio { 541 __be32 reserved0[2]; 542 __be64 gpio_event; 543 }; 544 545 struct mlx5_eqe_congestion { 546 u8 type; 547 u8 rsvd0; 548 u8 congestion_level; 549 }; 550 551 struct mlx5_eqe_stall_vl { 552 u8 rsvd0[3]; 553 u8 port_vl; 554 }; 555 556 struct mlx5_eqe_cmd { 557 __be32 vector; 558 __be32 rsvd[6]; 559 }; 560 561 struct mlx5_eqe_page_req { 562 u8 rsvd0[2]; 563 __be16 func_id; 564 __be32 num_pages; 565 __be32 rsvd1[5]; 566 }; 567 568 struct mlx5_eqe_vport_change { 569 u8 rsvd0[2]; 570 __be16 vport_num; 571 __be32 rsvd1[6]; 572 }; 573 574 struct mlx5_eqe_obj_change { 575 u8 rsvd0[2]; 576 __be16 obj_type; 577 __be32 obj_id; 578 }; 579 580 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 581 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 582 583 enum { 584 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 585 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 586 MLX5_MODULE_STATUS_ERROR = 0x3, 587 MLX5_MODULE_STATUS_NUM , 588 }; 589 590 enum { 591 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 592 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 593 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 594 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 595 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 596 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 597 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 598 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 599 MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8, 600 MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9, 601 MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa, 602 MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb, 603 MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc, 604 MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd, 605 MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe, 606 MLX5_MODULE_EVENT_ERROR_NUM , 607 }; 608 609 struct mlx5_eqe_port_module_event { 610 u8 rsvd0; 611 u8 module; 612 u8 rsvd1; 613 u8 module_status; 614 u8 rsvd2[2]; 615 u8 error_type; 616 }; 617 618 struct mlx5_eqe_general_notification_event { 619 u32 rq_user_index_delay_drop; 620 u32 rsvd0[6]; 621 }; 622 623 struct mlx5_eqe_dct { 624 __be32 reserved[6]; 625 __be32 dctn; 626 }; 627 628 struct mlx5_eqe_temp_warning { 629 __be64 sensor_warning_msb; 630 __be64 sensor_warning_lsb; 631 } __packed; 632 633 union ev_data { 634 __be32 raw[7]; 635 struct mlx5_eqe_cmd cmd; 636 struct mlx5_eqe_comp comp; 637 struct mlx5_eqe_qp_srq qp_srq; 638 struct mlx5_eqe_cq_err cq_err; 639 struct mlx5_eqe_port_state port; 640 struct mlx5_eqe_gpio gpio; 641 struct mlx5_eqe_congestion cong; 642 struct mlx5_eqe_stall_vl stall_vl; 643 struct mlx5_eqe_page_req req_pages; 644 struct mlx5_eqe_port_module_event port_module_event; 645 struct mlx5_eqe_vport_change vport_change; 646 struct mlx5_eqe_general_notification_event general_notifications; 647 struct mlx5_eqe_dct dct; 648 struct mlx5_eqe_temp_warning temp_warning; 649 struct mlx5_eqe_xrq_err xrq_err; 650 struct mlx5_eqe_obj_change obj_change; 651 } __packed; 652 653 struct mlx5_eqe { 654 u8 rsvd0; 655 u8 type; 656 u8 rsvd1; 657 u8 sub_type; 658 __be32 rsvd2[7]; 659 union ev_data data; 660 __be16 rsvd3; 661 u8 signature; 662 u8 owner; 663 } __packed; 664 665 struct mlx5_cmd_prot_block { 666 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 667 u8 rsvd0[48]; 668 __be64 next; 669 __be32 block_num; 670 u8 rsvd1; 671 u8 token; 672 u8 ctrl_sig; 673 u8 sig; 674 }; 675 676 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 677 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 678 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 679 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 680 681 enum { 682 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 683 }; 684 685 struct mlx5_err_cqe { 686 u8 rsvd0[32]; 687 __be32 srqn; 688 u8 rsvd1[18]; 689 u8 vendor_err_synd; 690 u8 syndrome; 691 __be32 s_wqe_opcode_qpn; 692 __be16 wqe_counter; 693 u8 signature; 694 u8 op_own; 695 }; 696 697 struct mlx5_cqe64 { 698 u8 tls_outer_l3_tunneled; 699 u8 rsvd0; 700 __be16 wqe_id; 701 u8 lro_tcppsh_abort_dupack; 702 u8 lro_min_ttl; 703 __be16 lro_tcp_win; 704 __be32 lro_ack_seq_num; 705 __be32 rss_hash_result; 706 u8 rss_hash_type; 707 u8 ml_path; 708 u8 rsvd20[2]; 709 __be16 check_sum; 710 __be16 slid; 711 __be32 flags_rqpn; 712 u8 hds_ip_ext; 713 u8 l4_hdr_type_etc; 714 __be16 vlan_info; 715 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 716 union { 717 __be32 immediate; 718 __be32 inval_rkey; 719 __be32 pkey; 720 __be32 ft_metadata; 721 }; 722 u8 rsvd40[4]; 723 __be32 byte_cnt; 724 __be64 timestamp; 725 __be32 sop_drop_qpn; 726 __be16 wqe_counter; 727 u8 signature; 728 u8 op_own; 729 }; 730 _Static_assert(sizeof(struct mlx5_cqe64) == 0x40, "CQE layout broken"); 731 732 #define MLX5_CQE_TSTMP_PTP (1ULL << 63) 733 734 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 735 { 736 return (cqe->op_own >> 4); 737 } 738 739 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 740 { 741 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 742 } 743 744 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 745 { 746 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 747 } 748 749 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 750 { 751 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 752 } 753 754 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 755 { 756 return be16_to_cpu(cqe->vlan_info) & 0xfff; 757 } 758 759 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 760 { 761 memcpy(smac, &cqe->rss_hash_type , 4); 762 memcpy(smac + 4, &cqe->slid , 2); 763 } 764 765 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 766 { 767 return cqe->l4_hdr_type_etc & 0x1; 768 } 769 770 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 771 { 772 return cqe->tls_outer_l3_tunneled & 0x1; 773 } 774 775 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) 776 { 777 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; 778 } 779 780 enum { 781 CQE_L4_HDR_TYPE_NONE = 0x0, 782 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 783 CQE_L4_HDR_TYPE_UDP = 0x2, 784 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 785 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 786 }; 787 788 enum { 789 /* source L3 hash types */ 790 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 791 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 792 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 793 794 /* destination L3 hash types */ 795 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 796 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 797 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 798 799 /* source L4 hash types */ 800 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 801 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 802 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 803 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 804 805 /* destination L4 hash types */ 806 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 807 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 808 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 809 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 810 }; 811 812 enum { 813 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 814 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 815 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 816 }; 817 818 enum { 819 CQE_L2_OK = 1 << 0, 820 CQE_L3_OK = 1 << 1, 821 CQE_L4_OK = 1 << 2, 822 }; 823 824 enum { 825 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, 826 CQE_TLS_OFFLOAD_DECRYPTED = 0x1, 827 CQE_TLS_OFFLOAD_RESYNC = 0x2, 828 CQE_TLS_OFFLOAD_ERROR = 0x3, 829 }; 830 831 struct mlx5_sig_err_cqe { 832 u8 rsvd0[16]; 833 __be32 expected_trans_sig; 834 __be32 actual_trans_sig; 835 __be32 expected_reftag; 836 __be32 actual_reftag; 837 __be16 syndrome; 838 u8 rsvd22[2]; 839 __be32 mkey; 840 __be64 err_offset; 841 u8 rsvd30[8]; 842 __be32 qpn; 843 u8 rsvd38[2]; 844 u8 signature; 845 u8 op_own; 846 }; 847 848 struct mlx5_wqe_srq_next_seg { 849 u8 rsvd0[2]; 850 __be16 next_wqe_index; 851 u8 signature; 852 u8 rsvd1[11]; 853 }; 854 855 union mlx5_ext_cqe { 856 struct ib_grh grh; 857 u8 inl[64]; 858 }; 859 860 struct mlx5_cqe128 { 861 union mlx5_ext_cqe inl_grh; 862 struct mlx5_cqe64 cqe64; 863 }; 864 865 enum { 866 MLX5_MKEY_STATUS_FREE = 1 << 6, 867 }; 868 869 struct mlx5_mkey_seg { 870 /* This is a two bit field occupying bits 31-30. 871 * bit 31 is always 0, 872 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 873 */ 874 u8 status; 875 u8 pcie_control; 876 u8 flags; 877 u8 version; 878 __be32 qpn_mkey7_0; 879 u8 rsvd1[4]; 880 __be32 flags_pd; 881 __be64 start_addr; 882 __be64 len; 883 __be32 bsfs_octo_size; 884 u8 rsvd2[16]; 885 __be32 xlt_oct_size; 886 u8 rsvd3[3]; 887 u8 log2_page_size; 888 u8 rsvd4[4]; 889 }; 890 891 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 892 893 enum { 894 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 895 }; 896 897 static inline int mlx5_host_is_le(void) 898 { 899 #if defined(__LITTLE_ENDIAN) 900 return 1; 901 #elif defined(__BIG_ENDIAN) 902 return 0; 903 #else 904 #error Host endianness not defined 905 #endif 906 } 907 908 #define MLX5_CMD_OP_MAX 0x939 909 910 enum { 911 VPORT_STATE_DOWN = 0x0, 912 VPORT_STATE_UP = 0x1, 913 VPORT_STATE_FOLLOW = 0x2, 914 }; 915 916 enum { 917 MLX5_L3_PROT_TYPE_IPV4 = 0, 918 MLX5_L3_PROT_TYPE_IPV6 = 1, 919 }; 920 921 enum { 922 MLX5_L4_PROT_TYPE_TCP = 0, 923 MLX5_L4_PROT_TYPE_UDP = 1, 924 }; 925 926 enum { 927 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 928 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 929 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 930 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 931 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 932 }; 933 934 enum { 935 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 936 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 937 MLX5_MATCH_INNER_HEADERS = 1 << 2, 938 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 939 940 }; 941 942 enum { 943 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 944 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 945 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 946 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 947 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 948 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 949 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 950 }; 951 952 enum { 953 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 954 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 955 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 956 }; 957 958 enum { 959 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 960 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 961 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 962 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 963 }; 964 965 enum { 966 MLX5_UC_ADDR_CHANGE = (1 << 0), 967 MLX5_MC_ADDR_CHANGE = (1 << 1), 968 MLX5_VLAN_CHANGE = (1 << 2), 969 MLX5_PROMISC_CHANGE = (1 << 3), 970 MLX5_MTU_CHANGE = (1 << 4), 971 }; 972 973 enum mlx5_list_type { 974 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 975 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 976 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 977 }; 978 979 enum { 980 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 981 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 982 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 983 }; 984 985 /* MLX5 DEV CAPs */ 986 987 /* TODO: EAT.ME */ 988 enum mlx5_cap_mode { 989 HCA_CAP_OPMOD_GET_MAX = 0, 990 HCA_CAP_OPMOD_GET_CUR = 1, 991 }; 992 993 enum mlx5_cap_type { 994 MLX5_CAP_GENERAL = 0, 995 MLX5_CAP_ETHERNET_OFFLOADS, 996 MLX5_CAP_ODP, 997 MLX5_CAP_ATOMIC, 998 MLX5_CAP_ROCE, 999 MLX5_CAP_IPOIB_OFFLOADS, 1000 MLX5_CAP_EOIB_OFFLOADS, 1001 MLX5_CAP_FLOW_TABLE, 1002 MLX5_CAP_ESWITCH_FLOW_TABLE, 1003 MLX5_CAP_ESWITCH, 1004 MLX5_CAP_SNAPSHOT, 1005 MLX5_CAP_VECTOR_CALC, 1006 MLX5_CAP_QOS, 1007 MLX5_CAP_DEBUG, 1008 MLX5_CAP_RESERVED_14, 1009 MLX5_CAP_DEV_MEM, 1010 MLX5_CAP_RESERVED_16, 1011 MLX5_CAP_TLS, 1012 MLX5_CAP_VDPA_EMULATION = 0x13, 1013 MLX5_CAP_DEV_EVENT = 0x14, 1014 MLX5_CAP_IPSEC, 1015 MLX5_CAP_CRYPTO = 0x1a, 1016 MLX5_CAP_DEV_SHAMPO = 0x1d, 1017 MLX5_CAP_MACSEC = 0x1f, 1018 MLX5_CAP_GENERAL_2 = 0x20, 1019 MLX5_CAP_PORT_SELECTION = 0x25, 1020 MLX5_CAP_ADV_VIRTUALIZATION = 0x26, 1021 /* NUM OF CAP Types */ 1022 MLX5_CAP_NUM 1023 }; 1024 1025 enum mlx5_qcam_reg_groups { 1026 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1027 }; 1028 1029 enum mlx5_qcam_feature_groups { 1030 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1031 }; 1032 1033 enum mlx5_pcam_reg_groups { 1034 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1035 }; 1036 1037 enum mlx5_pcam_feature_groups { 1038 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1039 }; 1040 1041 enum mlx5_mcam_reg_groups { 1042 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1043 }; 1044 1045 enum mlx5_mcam_feature_groups { 1046 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1047 }; 1048 1049 /* GET Dev Caps macros */ 1050 #define MLX5_CAP_GEN(mdev, cap) \ 1051 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1052 1053 #define MLX5_CAP_GEN_64(mdev, cap) \ 1054 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1055 1056 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1057 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1058 1059 #define MLX5_CAP_GEN_2(mdev, cap) \ 1060 MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap) 1061 1062 #define MLX5_CAP_ETH(mdev, cap) \ 1063 MLX5_GET(per_protocol_networking_offload_caps,\ 1064 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1065 1066 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1067 MLX5_GET(per_protocol_networking_offload_caps,\ 1068 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1069 1070 #define MLX5_CAP_ROCE(mdev, cap) \ 1071 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1072 1073 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1074 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1075 1076 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1077 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1078 1079 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1080 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1081 1082 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1083 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1084 1085 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ 1086 MLX5_GET64(flow_table_nic_cap, (mdev)->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1087 1088 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1089 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1090 1091 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1092 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1093 1094 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1095 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1096 1097 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1098 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1099 1100 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ 1101 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap) 1102 1103 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1104 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1105 1106 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1107 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1108 1109 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1110 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1111 1112 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1113 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1114 1115 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1116 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1117 1118 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ 1119 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap) 1120 1121 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ 1122 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) 1123 1124 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \ 1125 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap) 1126 1127 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1128 MLX5_GET(flow_table_eswitch_cap, \ 1129 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1130 1131 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1132 MLX5_GET(flow_table_eswitch_cap, \ 1133 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1134 1135 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1136 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1137 1138 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1139 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1140 1141 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1142 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1143 1144 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1145 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1146 1147 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1148 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1149 1150 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1151 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1152 1153 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \ 1154 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap) 1155 1156 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2_MAX(mdev, cap) \ 1157 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, ft_field_support_2_esw_fdb.cap) 1158 1159 #define MLX5_CAP_ESW(mdev, cap) \ 1160 MLX5_GET(e_switch_cap, \ 1161 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1162 1163 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ 1164 MLX5_GET64(flow_table_eswitch_cap, \ 1165 (mdev)->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1166 1167 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1168 MLX5_GET(e_switch_cap, \ 1169 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1170 1171 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \ 1172 MLX5_GET(port_selection_cap, \ 1173 mdev->hca_caps_cur[MLX5_CAP_PORT_SELECTION], cap) 1174 1175 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \ 1176 MLX5_GET(port_selection_cap, \ 1177 mdev->hca_caps_max[MLX5_CAP_PORT_SELECTION], cap) 1178 1179 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ 1180 MLX5_GET(adv_virtualization_cap, \ 1181 mdev->hca_caps_cur[MLX5_CAP_ADV_VIRTUALIZATION], cap) 1182 1183 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \ 1184 MLX5_GET(adv_virtualization_cap, \ 1185 mdev->hca_caps_max[MLX5_CAP_ADV_VIRTUALIZATION], cap) 1186 1187 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ 1188 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) 1189 1190 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \ 1191 MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap) 1192 1193 #define MLX5_CAP_ODP(mdev, cap)\ 1194 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1195 1196 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1197 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1198 1199 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1200 MLX5_GET(snapshot_cap, \ 1201 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1202 1203 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1204 MLX5_GET(snapshot_cap, \ 1205 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1206 1207 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1208 MLX5_GET(per_protocol_networking_offload_caps,\ 1209 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1210 1211 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1212 MLX5_GET(per_protocol_networking_offload_caps,\ 1213 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1214 1215 #define MLX5_CAP_DEBUG(mdev, cap) \ 1216 MLX5_GET(debug_cap, \ 1217 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1218 1219 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1220 MLX5_GET(debug_cap, \ 1221 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1222 1223 #define MLX5_CAP_QOS(mdev, cap) \ 1224 MLX5_GET(qos_cap,\ 1225 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1226 1227 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 1228 MLX5_GET(qos_cap,\ 1229 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1230 1231 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1232 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1233 1234 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1235 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1236 1237 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1238 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1239 1240 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1241 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1242 1243 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1244 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1245 1246 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1247 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1248 1249 #define MLX5_CAP_FPGA(mdev, cap) \ 1250 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1251 1252 #define MLX5_CAP64_FPGA(mdev, cap) \ 1253 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1254 1255 #define MLX5_CAP_TLS(mdev, cap) \ 1256 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap) 1257 1258 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1259 MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap) 1260 1261 #define MLX5_CAP_IPSEC(mdev, cap) \ 1262 MLX5_GET(ipsec_cap, (mdev)->hca_caps_cur[MLX5_CAP_IPSEC], cap) 1263 1264 enum { 1265 MLX5_CMD_STAT_OK = 0x0, 1266 MLX5_CMD_STAT_INT_ERR = 0x1, 1267 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1268 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1269 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1270 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1271 MLX5_CMD_STAT_RES_BUSY = 0x6, 1272 MLX5_CMD_STAT_LIM_ERR = 0x8, 1273 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1274 MLX5_CMD_STAT_IX_ERR = 0xa, 1275 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1276 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1277 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1278 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1279 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1280 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1281 }; 1282 1283 enum { 1284 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1285 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1286 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1287 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1288 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1289 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1290 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1291 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1292 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1293 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1294 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1295 }; 1296 1297 enum { 1298 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1299 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1300 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1301 }; 1302 1303 enum { 1304 MLX5_CAP_PORT_TYPE_IB = 0x0, 1305 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1306 }; 1307 1308 enum { 1309 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1310 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1311 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1312 }; 1313 1314 enum mlx5_inline_modes { 1315 MLX5_INLINE_MODE_NONE, 1316 MLX5_INLINE_MODE_L2, 1317 MLX5_INLINE_MODE_IP, 1318 MLX5_INLINE_MODE_TCP_UDP, 1319 }; 1320 1321 enum { 1322 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1323 }; 1324 1325 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1326 { 1327 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1328 return 0; 1329 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1330 } 1331 1332 struct mlx5_ifc_mcia_reg_bits { 1333 u8 l[0x1]; 1334 u8 reserved_0[0x7]; 1335 u8 module[0x8]; 1336 u8 reserved_1[0x8]; 1337 u8 status[0x8]; 1338 1339 u8 i2c_device_address[0x8]; 1340 u8 page_number[0x8]; 1341 u8 device_address[0x10]; 1342 1343 u8 reserved_2[0x10]; 1344 u8 size[0x10]; 1345 1346 u8 reserved_3[0x20]; 1347 1348 u8 dword_0[0x20]; 1349 u8 dword_1[0x20]; 1350 u8 dword_2[0x20]; 1351 u8 dword_3[0x20]; 1352 u8 dword_4[0x20]; 1353 u8 dword_5[0x20]; 1354 u8 dword_6[0x20]; 1355 u8 dword_7[0x20]; 1356 u8 dword_8[0x20]; 1357 u8 dword_9[0x20]; 1358 u8 dword_10[0x20]; 1359 u8 dword_11[0x20]; 1360 }; 1361 1362 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1363 1364 struct mlx5_mini_cqe8 { 1365 union { 1366 __be32 rx_hash_result; 1367 __be16 checksum; 1368 __be16 rsvd; 1369 struct { 1370 __be16 wqe_counter; 1371 u8 s_wqe_opcode; 1372 u8 reserved; 1373 } s_wqe_info; 1374 }; 1375 __be32 byte_cnt; 1376 }; 1377 1378 enum { 1379 MLX5_NO_INLINE_DATA, 1380 MLX5_INLINE_DATA32_SEG, 1381 MLX5_INLINE_DATA64_SEG, 1382 MLX5_COMPRESSED, 1383 }; 1384 1385 enum mlx5_exp_cqe_zip_recv_type { 1386 MLX5_CQE_FORMAT_HASH, 1387 MLX5_CQE_FORMAT_CSUM, 1388 }; 1389 1390 #define MLX5E_CQE_FORMAT_MASK 0xc 1391 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1392 { 1393 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1394 } 1395 1396 enum { 1397 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1398 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 1399 }; 1400 1401 enum { 1402 MLX5_FRL_LEVEL3 = 0x8, 1403 MLX5_FRL_LEVEL6 = 0x40, 1404 }; 1405 1406 /* 8 regular priorities + 1 for multicast */ 1407 #define MLX5_NUM_BYPASS_FTS 9 1408 1409 #endif /* MLX5_DEVICE_H */ 1410