1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DEVICE_H 29 #define MLX5_DEVICE_H 30 31 #include <linux/types.h> 32 #include <rdma/ib_verbs.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define FW_INIT_TIMEOUT_MILI 2000 36 #define FW_INIT_WAIT_MS 2 37 38 #if defined(__LITTLE_ENDIAN) 39 #define MLX5_SET_HOST_ENDIANNESS 0 40 #elif defined(__BIG_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0x80 42 #else 43 #error Host endianness not defined 44 #endif 45 46 /* helper macros */ 47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 51 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 52 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 53 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 54 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 55 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 56 57 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 58 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 59 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 60 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 61 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 62 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 63 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 64 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 65 66 /* insert a value to a struct */ 67 #define MLX5_SET(typ, p, fld, v) do { \ 68 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 69 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73 << __mlx5_dw_bit_off(typ, fld))); \ 74 } while (0) 75 76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 82 << __mlx5_dw_bit_off(typ, fld))); \ 83 } while (0) 84 85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 87 __mlx5_mask(typ, fld)) 88 89 #define MLX5_GET_PR(typ, p, fld) ({ \ 90 u32 ___t = MLX5_GET(typ, p, fld); \ 91 pr_debug(#fld " = 0x%x\n", ___t); \ 92 ___t; \ 93 }) 94 95 #define MLX5_SET64(typ, p, fld, v) do { \ 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 99 } while (0) 100 101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 102 103 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 104 __mlx5_64_off(typ, fld))) 105 106 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 107 type_t tmp; \ 108 switch (sizeof(tmp)) { \ 109 case sizeof(u8): \ 110 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 111 break; \ 112 case sizeof(u16): \ 113 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 114 break; \ 115 case sizeof(u32): \ 116 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 117 break; \ 118 case sizeof(u64): \ 119 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 120 break; \ 121 } \ 122 tmp; \ 123 }) 124 125 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 126 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 127 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 128 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 129 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 130 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 131 132 enum { 133 MLX5_MAX_COMMANDS = 32, 134 MLX5_CMD_DATA_BLOCK_SIZE = 512, 135 MLX5_CMD_MBOX_SIZE = 1024, 136 MLX5_PCI_CMD_XPORT = 7, 137 MLX5_MKEY_BSF_OCTO_SIZE = 4, 138 MLX5_MAX_PSVS = 4, 139 }; 140 141 enum { 142 MLX5_EXTENDED_UD_AV = 0x80000000, 143 }; 144 145 enum { 146 MLX5_CQ_FLAGS_OI = 2, 147 }; 148 149 enum { 150 MLX5_STAT_RATE_OFFSET = 5, 151 }; 152 153 enum { 154 MLX5_INLINE_SEG = 0x80000000, 155 }; 156 157 enum { 158 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 159 }; 160 161 enum { 162 MLX5_MIN_PKEY_TABLE_SIZE = 128, 163 MLX5_MAX_LOG_PKEY_TABLE = 5, 164 }; 165 166 enum { 167 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 168 }; 169 170 enum { 171 MLX5_PERM_LOCAL_READ = 1 << 2, 172 MLX5_PERM_LOCAL_WRITE = 1 << 3, 173 MLX5_PERM_REMOTE_READ = 1 << 4, 174 MLX5_PERM_REMOTE_WRITE = 1 << 5, 175 MLX5_PERM_ATOMIC = 1 << 6, 176 MLX5_PERM_UMR_EN = 1 << 7, 177 }; 178 179 enum { 180 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 181 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 182 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 183 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 184 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 185 }; 186 187 enum { 188 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 189 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 190 MLX5_MKEY_BSF_EN = 1 << 30, 191 MLX5_MKEY_LEN64 = 1 << 31, 192 }; 193 194 enum { 195 MLX5_EN_RD = (u64)1, 196 MLX5_EN_WR = (u64)2 197 }; 198 199 enum { 200 MLX5_BF_REGS_PER_PAGE = 4, 201 MLX5_MAX_UAR_PAGES = 1 << 8, 202 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 203 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 204 }; 205 206 enum { 207 MLX5_MKEY_MASK_LEN = 1ull << 0, 208 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 209 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 210 MLX5_MKEY_MASK_PD = 1ull << 7, 211 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 212 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 213 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 214 MLX5_MKEY_MASK_KEY = 1ull << 13, 215 MLX5_MKEY_MASK_QPN = 1ull << 14, 216 MLX5_MKEY_MASK_LR = 1ull << 17, 217 MLX5_MKEY_MASK_LW = 1ull << 18, 218 MLX5_MKEY_MASK_RR = 1ull << 19, 219 MLX5_MKEY_MASK_RW = 1ull << 20, 220 MLX5_MKEY_MASK_A = 1ull << 21, 221 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 222 MLX5_MKEY_MASK_FREE = 1ull << 29, 223 }; 224 225 enum { 226 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 227 228 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 229 MLX5_UMR_CHECK_FREE = (2 << 5), 230 231 MLX5_UMR_INLINE = (1 << 7), 232 }; 233 234 #define MLX5_UMR_MTT_ALIGNMENT 0x40 235 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 236 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 237 238 enum { 239 MLX5_EVENT_QUEUE_TYPE_QP = 0, 240 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 241 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 242 }; 243 244 enum { 245 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 246 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 247 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 248 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 249 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 250 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 251 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 252 }; 253 254 enum { 255 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 256 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 257 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 258 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 259 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 260 }; 261 262 enum { 263 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 264 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 265 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 266 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 267 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 268 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 269 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 270 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 272 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 273 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 274 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 275 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 276 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 277 }; 278 279 enum { 280 MLX5_ROCE_VERSION_1 = 0, 281 MLX5_ROCE_VERSION_1_5 = 1, 282 MLX5_ROCE_VERSION_2 = 2, 283 }; 284 285 enum { 286 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 287 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 288 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 289 }; 290 291 enum { 292 MLX5_ROCE_L3_TYPE_IPV4 = 0, 293 MLX5_ROCE_L3_TYPE_IPV6 = 1, 294 }; 295 296 enum { 297 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 298 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 299 }; 300 301 enum { 302 MLX5_OPCODE_NOP = 0x00, 303 MLX5_OPCODE_SEND_INVAL = 0x01, 304 MLX5_OPCODE_RDMA_WRITE = 0x08, 305 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 306 MLX5_OPCODE_SEND = 0x0a, 307 MLX5_OPCODE_SEND_IMM = 0x0b, 308 MLX5_OPCODE_LSO = 0x0e, 309 MLX5_OPCODE_RDMA_READ = 0x10, 310 MLX5_OPCODE_ATOMIC_CS = 0x11, 311 MLX5_OPCODE_ATOMIC_FA = 0x12, 312 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 313 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 314 MLX5_OPCODE_BIND_MW = 0x18, 315 MLX5_OPCODE_CONFIG_CMD = 0x1f, 316 317 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 318 MLX5_RECV_OPCODE_SEND = 0x01, 319 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 320 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 321 322 MLX5_CQE_OPCODE_ERROR = 0x1e, 323 MLX5_CQE_OPCODE_RESIZE = 0x16, 324 325 MLX5_OPCODE_SET_PSV = 0x20, 326 MLX5_OPCODE_GET_PSV = 0x21, 327 MLX5_OPCODE_CHECK_PSV = 0x22, 328 MLX5_OPCODE_RGET_PSV = 0x26, 329 MLX5_OPCODE_RCHECK_PSV = 0x27, 330 331 MLX5_OPCODE_UMR = 0x25, 332 333 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 334 }; 335 336 enum { 337 MLX5_SET_PORT_RESET_QKEY = 0, 338 MLX5_SET_PORT_GUID0 = 16, 339 MLX5_SET_PORT_NODE_GUID = 17, 340 MLX5_SET_PORT_SYS_GUID = 18, 341 MLX5_SET_PORT_GID_TABLE = 19, 342 MLX5_SET_PORT_PKEY_TABLE = 20, 343 }; 344 345 enum { 346 MLX5_MAX_PAGE_SHIFT = 31 347 }; 348 349 enum { 350 MLX5_ADAPTER_PAGE_SHIFT = 12, 351 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 352 }; 353 354 enum { 355 MLX5_CAP_OFF_CMDIF_CSUM = 46, 356 }; 357 358 enum { 359 /* 360 * Max wqe size for rdma read is 512 bytes, so this 361 * limits our max_sge_rd as the wqe needs to fit: 362 * - ctrl segment (16 bytes) 363 * - rdma segment (16 bytes) 364 * - scatter elements (16 bytes each) 365 */ 366 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 367 }; 368 369 struct mlx5_inbox_hdr { 370 __be16 opcode; 371 u8 rsvd[4]; 372 __be16 opmod; 373 }; 374 375 struct mlx5_outbox_hdr { 376 u8 status; 377 u8 rsvd[3]; 378 __be32 syndrome; 379 }; 380 381 struct mlx5_cmd_set_dc_cnak_mbox_in { 382 struct mlx5_inbox_hdr hdr; 383 u8 enable; 384 u8 reserved[47]; 385 __be64 pa; 386 }; 387 388 struct mlx5_cmd_set_dc_cnak_mbox_out { 389 struct mlx5_outbox_hdr hdr; 390 u8 rsvd[8]; 391 }; 392 393 struct mlx5_cmd_layout { 394 u8 type; 395 u8 rsvd0[3]; 396 __be32 inlen; 397 __be64 in_ptr; 398 __be32 in[4]; 399 __be32 out[4]; 400 __be64 out_ptr; 401 __be32 outlen; 402 u8 token; 403 u8 sig; 404 u8 rsvd1; 405 u8 status_own; 406 }; 407 408 409 struct mlx5_health_buffer { 410 __be32 assert_var[5]; 411 __be32 rsvd0[3]; 412 __be32 assert_exit_ptr; 413 __be32 assert_callra; 414 __be32 rsvd1[2]; 415 __be32 fw_ver; 416 __be32 hw_id; 417 __be32 rsvd2; 418 u8 irisc_index; 419 u8 synd; 420 __be16 ext_sync; 421 }; 422 423 struct mlx5_init_seg { 424 __be32 fw_rev; 425 __be32 cmdif_rev_fw_sub; 426 __be32 rsvd0[2]; 427 __be32 cmdq_addr_h; 428 __be32 cmdq_addr_l_sz; 429 __be32 cmd_dbell; 430 __be32 rsvd1[120]; 431 __be32 initializing; 432 struct mlx5_health_buffer health; 433 __be32 rsvd2[880]; 434 __be32 internal_timer_h; 435 __be32 internal_timer_l; 436 __be32 rsvd3[2]; 437 __be32 health_counter; 438 __be32 rsvd4[1019]; 439 __be64 ieee1588_clk; 440 __be32 ieee1588_clk_type; 441 __be32 clr_intx; 442 }; 443 444 struct mlx5_eqe_comp { 445 __be32 reserved[6]; 446 __be32 cqn; 447 }; 448 449 struct mlx5_eqe_qp_srq { 450 __be32 reserved[6]; 451 __be32 qp_srq_n; 452 }; 453 454 struct mlx5_eqe_cq_err { 455 __be32 cqn; 456 u8 reserved1[7]; 457 u8 syndrome; 458 }; 459 460 struct mlx5_eqe_port_state { 461 u8 reserved0[8]; 462 u8 port; 463 }; 464 465 struct mlx5_eqe_gpio { 466 __be32 reserved0[2]; 467 __be64 gpio_event; 468 }; 469 470 struct mlx5_eqe_congestion { 471 u8 type; 472 u8 rsvd0; 473 u8 congestion_level; 474 }; 475 476 struct mlx5_eqe_stall_vl { 477 u8 rsvd0[3]; 478 u8 port_vl; 479 }; 480 481 struct mlx5_eqe_cmd { 482 __be32 vector; 483 __be32 rsvd[6]; 484 }; 485 486 struct mlx5_eqe_page_req { 487 u8 rsvd0[2]; 488 __be16 func_id; 489 __be32 num_pages; 490 __be32 rsvd1[5]; 491 }; 492 493 struct mlx5_eqe_vport_change { 494 u8 rsvd0[2]; 495 __be16 vport_num; 496 __be32 rsvd1[6]; 497 }; 498 499 500 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 501 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 502 503 enum { 504 MLX5_MODULE_STATUS_PLUGGED = 0x1, 505 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 506 MLX5_MODULE_STATUS_ERROR = 0x3, 507 }; 508 509 enum { 510 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 511 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 512 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 513 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 514 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 515 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 0x5, 516 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 517 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 518 }; 519 520 struct mlx5_eqe_port_module_event { 521 u8 rsvd0; 522 u8 module; 523 u8 rsvd1; 524 u8 module_status; 525 u8 rsvd2[2]; 526 u8 error_type; 527 }; 528 529 struct mlx5_eqe_general_notification_event { 530 u32 rq_user_index_delay_drop; 531 u32 rsvd0[6]; 532 }; 533 534 union ev_data { 535 __be32 raw[7]; 536 struct mlx5_eqe_cmd cmd; 537 struct mlx5_eqe_comp comp; 538 struct mlx5_eqe_qp_srq qp_srq; 539 struct mlx5_eqe_cq_err cq_err; 540 struct mlx5_eqe_port_state port; 541 struct mlx5_eqe_gpio gpio; 542 struct mlx5_eqe_congestion cong; 543 struct mlx5_eqe_stall_vl stall_vl; 544 struct mlx5_eqe_page_req req_pages; 545 struct mlx5_eqe_port_module_event port_module_event; 546 struct mlx5_eqe_vport_change vport_change; 547 struct mlx5_eqe_general_notification_event general_notifications; 548 } __packed; 549 550 struct mlx5_eqe { 551 u8 rsvd0; 552 u8 type; 553 u8 rsvd1; 554 u8 sub_type; 555 __be32 rsvd2[7]; 556 union ev_data data; 557 __be16 rsvd3; 558 u8 signature; 559 u8 owner; 560 } __packed; 561 562 struct mlx5_cmd_prot_block { 563 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 564 u8 rsvd0[48]; 565 __be64 next; 566 __be32 block_num; 567 u8 rsvd1; 568 u8 token; 569 u8 ctrl_sig; 570 u8 sig; 571 }; 572 573 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 574 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 575 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 576 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 577 578 enum { 579 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 580 }; 581 582 struct mlx5_err_cqe { 583 u8 rsvd0[32]; 584 __be32 srqn; 585 u8 rsvd1[18]; 586 u8 vendor_err_synd; 587 u8 syndrome; 588 __be32 s_wqe_opcode_qpn; 589 __be16 wqe_counter; 590 u8 signature; 591 u8 op_own; 592 }; 593 594 struct mlx5_cqe64 { 595 u8 tunneled_etc; 596 u8 rsvd0[3]; 597 u8 lro_tcppsh_abort_dupack; 598 u8 lro_min_ttl; 599 __be16 lro_tcp_win; 600 __be32 lro_ack_seq_num; 601 __be32 rss_hash_result; 602 u8 rss_hash_type; 603 u8 ml_path; 604 u8 rsvd20[2]; 605 __be16 check_sum; 606 __be16 slid; 607 __be32 flags_rqpn; 608 u8 hds_ip_ext; 609 u8 l4_hdr_type_etc; 610 __be16 vlan_info; 611 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 612 __be32 imm_inval_pkey; 613 u8 rsvd40[4]; 614 __be32 byte_cnt; 615 __be64 timestamp; 616 __be32 sop_drop_qpn; 617 __be16 wqe_counter; 618 u8 signature; 619 u8 op_own; 620 }; 621 622 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 623 { 624 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 625 } 626 627 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 628 { 629 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 630 } 631 632 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 633 { 634 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 635 } 636 637 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 638 { 639 return be16_to_cpu(cqe->vlan_info) & 0xfff; 640 } 641 642 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 643 { 644 memcpy(smac, &cqe->rss_hash_type , 4); 645 memcpy(smac + 4, &cqe->slid , 2); 646 } 647 648 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 649 { 650 return cqe->l4_hdr_type_etc & 0x1; 651 } 652 653 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 654 { 655 return cqe->tunneled_etc & 0x1; 656 } 657 658 enum { 659 CQE_L4_HDR_TYPE_NONE = 0x0, 660 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 661 CQE_L4_HDR_TYPE_UDP = 0x2, 662 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 663 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 664 }; 665 666 enum { 667 /* source L3 hash types */ 668 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 669 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 670 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 671 672 /* destination L3 hash types */ 673 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 674 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 675 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 676 677 /* source L4 hash types */ 678 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 679 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 680 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 681 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 682 683 /* destination L4 hash types */ 684 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 685 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 686 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 687 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 688 }; 689 690 enum { 691 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 692 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 693 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 694 }; 695 696 enum { 697 CQE_L2_OK = 1 << 0, 698 CQE_L3_OK = 1 << 1, 699 CQE_L4_OK = 1 << 2, 700 }; 701 702 struct mlx5_sig_err_cqe { 703 u8 rsvd0[16]; 704 __be32 expected_trans_sig; 705 __be32 actual_trans_sig; 706 __be32 expected_reftag; 707 __be32 actual_reftag; 708 __be16 syndrome; 709 u8 rsvd22[2]; 710 __be32 mkey; 711 __be64 err_offset; 712 u8 rsvd30[8]; 713 __be32 qpn; 714 u8 rsvd38[2]; 715 u8 signature; 716 u8 op_own; 717 }; 718 719 struct mlx5_wqe_srq_next_seg { 720 u8 rsvd0[2]; 721 __be16 next_wqe_index; 722 u8 signature; 723 u8 rsvd1[11]; 724 }; 725 726 union mlx5_ext_cqe { 727 struct ib_grh grh; 728 u8 inl[64]; 729 }; 730 731 struct mlx5_cqe128 { 732 union mlx5_ext_cqe inl_grh; 733 struct mlx5_cqe64 cqe64; 734 }; 735 736 struct mlx5_srq_ctx { 737 u8 state_log_sz; 738 u8 rsvd0[3]; 739 __be32 flags_xrcd; 740 __be32 pgoff_cqn; 741 u8 rsvd1[4]; 742 u8 log_pg_sz; 743 u8 rsvd2[7]; 744 __be32 pd; 745 __be16 lwm; 746 __be16 wqe_cnt; 747 u8 rsvd3[8]; 748 __be64 db_record; 749 }; 750 751 struct mlx5_create_srq_mbox_in { 752 struct mlx5_inbox_hdr hdr; 753 __be32 input_srqn; 754 u8 rsvd0[4]; 755 struct mlx5_srq_ctx ctx; 756 u8 rsvd1[208]; 757 __be64 pas[0]; 758 }; 759 760 struct mlx5_create_srq_mbox_out { 761 struct mlx5_outbox_hdr hdr; 762 __be32 srqn; 763 u8 rsvd[4]; 764 }; 765 766 struct mlx5_destroy_srq_mbox_in { 767 struct mlx5_inbox_hdr hdr; 768 __be32 srqn; 769 u8 rsvd[4]; 770 }; 771 772 struct mlx5_destroy_srq_mbox_out { 773 struct mlx5_outbox_hdr hdr; 774 u8 rsvd[8]; 775 }; 776 777 struct mlx5_query_srq_mbox_in { 778 struct mlx5_inbox_hdr hdr; 779 __be32 srqn; 780 u8 rsvd0[4]; 781 }; 782 783 struct mlx5_query_srq_mbox_out { 784 struct mlx5_outbox_hdr hdr; 785 u8 rsvd0[8]; 786 struct mlx5_srq_ctx ctx; 787 u8 rsvd1[32]; 788 __be64 pas[0]; 789 }; 790 791 struct mlx5_arm_srq_mbox_in { 792 struct mlx5_inbox_hdr hdr; 793 __be32 srqn; 794 __be16 rsvd; 795 __be16 lwm; 796 }; 797 798 struct mlx5_arm_srq_mbox_out { 799 struct mlx5_outbox_hdr hdr; 800 u8 rsvd[8]; 801 }; 802 803 struct mlx5_cq_context { 804 u8 status; 805 u8 cqe_sz_flags; 806 u8 st; 807 u8 rsvd3; 808 u8 rsvd4[6]; 809 __be16 page_offset; 810 __be32 log_sz_usr_page; 811 __be16 cq_period; 812 __be16 cq_max_count; 813 __be16 rsvd20; 814 __be16 c_eqn; 815 u8 log_pg_sz; 816 u8 rsvd25[7]; 817 __be32 last_notified_index; 818 __be32 solicit_producer_index; 819 __be32 consumer_counter; 820 __be32 producer_counter; 821 u8 rsvd48[8]; 822 __be64 db_record_addr; 823 }; 824 825 struct mlx5_create_cq_mbox_in { 826 struct mlx5_inbox_hdr hdr; 827 __be32 input_cqn; 828 u8 rsvdx[4]; 829 struct mlx5_cq_context ctx; 830 u8 rsvd6[192]; 831 __be64 pas[0]; 832 }; 833 834 struct mlx5_create_cq_mbox_out { 835 struct mlx5_outbox_hdr hdr; 836 __be32 cqn; 837 u8 rsvd0[4]; 838 }; 839 840 struct mlx5_destroy_cq_mbox_in { 841 struct mlx5_inbox_hdr hdr; 842 __be32 cqn; 843 u8 rsvd0[4]; 844 }; 845 846 struct mlx5_destroy_cq_mbox_out { 847 struct mlx5_outbox_hdr hdr; 848 u8 rsvd0[8]; 849 }; 850 851 struct mlx5_query_cq_mbox_in { 852 struct mlx5_inbox_hdr hdr; 853 __be32 cqn; 854 u8 rsvd0[4]; 855 }; 856 857 struct mlx5_query_cq_mbox_out { 858 struct mlx5_outbox_hdr hdr; 859 u8 rsvd0[8]; 860 struct mlx5_cq_context ctx; 861 u8 rsvd6[16]; 862 __be64 pas[0]; 863 }; 864 865 struct mlx5_modify_cq_mbox_in { 866 struct mlx5_inbox_hdr hdr; 867 __be32 cqn; 868 __be32 field_select; 869 struct mlx5_cq_context ctx; 870 u8 rsvd[192]; 871 __be64 pas[0]; 872 }; 873 874 struct mlx5_modify_cq_mbox_out { 875 struct mlx5_outbox_hdr hdr; 876 u8 rsvd[8]; 877 }; 878 879 struct mlx5_eq_context { 880 u8 status; 881 u8 ec_oi; 882 u8 st; 883 u8 rsvd2[7]; 884 __be16 page_pffset; 885 __be32 log_sz_usr_page; 886 u8 rsvd3[7]; 887 u8 intr; 888 u8 log_page_size; 889 u8 rsvd4[15]; 890 __be32 consumer_counter; 891 __be32 produser_counter; 892 u8 rsvd5[16]; 893 }; 894 895 struct mlx5_create_eq_mbox_in { 896 struct mlx5_inbox_hdr hdr; 897 u8 rsvd0[3]; 898 u8 input_eqn; 899 u8 rsvd1[4]; 900 struct mlx5_eq_context ctx; 901 u8 rsvd2[8]; 902 __be64 events_mask; 903 u8 rsvd3[176]; 904 __be64 pas[0]; 905 }; 906 907 struct mlx5_create_eq_mbox_out { 908 struct mlx5_outbox_hdr hdr; 909 u8 rsvd0[3]; 910 u8 eq_number; 911 u8 rsvd1[4]; 912 }; 913 914 struct mlx5_map_eq_mbox_in { 915 struct mlx5_inbox_hdr hdr; 916 __be64 mask; 917 u8 mu; 918 u8 rsvd0[2]; 919 u8 eqn; 920 u8 rsvd1[24]; 921 }; 922 923 struct mlx5_map_eq_mbox_out { 924 struct mlx5_outbox_hdr hdr; 925 u8 rsvd[8]; 926 }; 927 928 struct mlx5_query_eq_mbox_in { 929 struct mlx5_inbox_hdr hdr; 930 u8 rsvd0[3]; 931 u8 eqn; 932 u8 rsvd1[4]; 933 }; 934 935 struct mlx5_query_eq_mbox_out { 936 struct mlx5_outbox_hdr hdr; 937 u8 rsvd[8]; 938 struct mlx5_eq_context ctx; 939 }; 940 941 enum { 942 MLX5_MKEY_STATUS_FREE = 1 << 6, 943 }; 944 945 struct mlx5_mkey_seg { 946 /* This is a two bit field occupying bits 31-30. 947 * bit 31 is always 0, 948 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 949 */ 950 u8 status; 951 u8 pcie_control; 952 u8 flags; 953 u8 version; 954 __be32 qpn_mkey7_0; 955 u8 rsvd1[4]; 956 __be32 flags_pd; 957 __be64 start_addr; 958 __be64 len; 959 __be32 bsfs_octo_size; 960 u8 rsvd2[16]; 961 __be32 xlt_oct_size; 962 u8 rsvd3[3]; 963 u8 log2_page_size; 964 u8 rsvd4[4]; 965 }; 966 967 struct mlx5_query_special_ctxs_mbox_in { 968 struct mlx5_inbox_hdr hdr; 969 u8 rsvd[8]; 970 }; 971 972 struct mlx5_query_special_ctxs_mbox_out { 973 struct mlx5_outbox_hdr hdr; 974 __be32 dump_fill_mkey; 975 __be32 reserved_lkey; 976 }; 977 978 struct mlx5_create_mkey_mbox_in { 979 struct mlx5_inbox_hdr hdr; 980 __be32 input_mkey_index; 981 __be32 flags; 982 struct mlx5_mkey_seg seg; 983 u8 rsvd1[16]; 984 __be32 xlat_oct_act_size; 985 __be32 rsvd2; 986 u8 rsvd3[168]; 987 __be64 pas[0]; 988 }; 989 990 struct mlx5_create_mkey_mbox_out { 991 struct mlx5_outbox_hdr hdr; 992 __be32 mkey; 993 u8 rsvd[4]; 994 }; 995 996 struct mlx5_query_mkey_mbox_in { 997 struct mlx5_inbox_hdr hdr; 998 __be32 mkey; 999 }; 1000 1001 struct mlx5_query_mkey_mbox_out { 1002 struct mlx5_outbox_hdr hdr; 1003 __be64 pas[0]; 1004 }; 1005 1006 struct mlx5_modify_mkey_mbox_in { 1007 struct mlx5_inbox_hdr hdr; 1008 __be32 mkey; 1009 __be64 pas[0]; 1010 }; 1011 1012 struct mlx5_modify_mkey_mbox_out { 1013 struct mlx5_outbox_hdr hdr; 1014 u8 rsvd[8]; 1015 }; 1016 1017 struct mlx5_dump_mkey_mbox_in { 1018 struct mlx5_inbox_hdr hdr; 1019 }; 1020 1021 struct mlx5_dump_mkey_mbox_out { 1022 struct mlx5_outbox_hdr hdr; 1023 __be32 mkey; 1024 }; 1025 1026 struct mlx5_mad_ifc_mbox_in { 1027 struct mlx5_inbox_hdr hdr; 1028 __be16 remote_lid; 1029 u8 rsvd0; 1030 u8 port; 1031 u8 rsvd1[4]; 1032 u8 data[256]; 1033 }; 1034 1035 struct mlx5_mad_ifc_mbox_out { 1036 struct mlx5_outbox_hdr hdr; 1037 u8 rsvd[8]; 1038 u8 data[256]; 1039 }; 1040 1041 struct mlx5_access_reg_mbox_in { 1042 struct mlx5_inbox_hdr hdr; 1043 u8 rsvd0[2]; 1044 __be16 register_id; 1045 __be32 arg; 1046 __be32 data[0]; 1047 }; 1048 1049 struct mlx5_access_reg_mbox_out { 1050 struct mlx5_outbox_hdr hdr; 1051 u8 rsvd[8]; 1052 __be32 data[0]; 1053 }; 1054 1055 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1056 1057 enum { 1058 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1059 }; 1060 1061 struct mlx5_allocate_psv_in { 1062 struct mlx5_inbox_hdr hdr; 1063 __be32 npsv_pd; 1064 __be32 rsvd_psv0; 1065 }; 1066 1067 struct mlx5_allocate_psv_out { 1068 struct mlx5_outbox_hdr hdr; 1069 u8 rsvd[8]; 1070 __be32 psv_idx[4]; 1071 }; 1072 1073 struct mlx5_destroy_psv_in { 1074 struct mlx5_inbox_hdr hdr; 1075 __be32 psv_number; 1076 u8 rsvd[4]; 1077 }; 1078 1079 struct mlx5_destroy_psv_out { 1080 struct mlx5_outbox_hdr hdr; 1081 u8 rsvd[8]; 1082 }; 1083 1084 static inline int mlx5_host_is_le(void) 1085 { 1086 #if defined(__LITTLE_ENDIAN) 1087 return 1; 1088 #elif defined(__BIG_ENDIAN) 1089 return 0; 1090 #else 1091 #error Host endianness not defined 1092 #endif 1093 } 1094 1095 #define MLX5_CMD_OP_MAX 0x939 1096 1097 enum { 1098 VPORT_STATE_DOWN = 0x0, 1099 VPORT_STATE_UP = 0x1, 1100 }; 1101 1102 enum { 1103 MLX5_L3_PROT_TYPE_IPV4 = 0, 1104 MLX5_L3_PROT_TYPE_IPV6 = 1, 1105 }; 1106 1107 enum { 1108 MLX5_L4_PROT_TYPE_TCP = 0, 1109 MLX5_L4_PROT_TYPE_UDP = 1, 1110 }; 1111 1112 enum { 1113 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1114 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1115 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1116 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1117 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1118 }; 1119 1120 enum { 1121 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1122 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1123 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1124 1125 }; 1126 1127 enum { 1128 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1129 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 1130 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 1131 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1132 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 1133 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 1134 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 1135 }; 1136 1137 enum { 1138 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 1139 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 1140 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 1141 }; 1142 1143 enum { 1144 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 1145 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 1146 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 1147 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 1148 }; 1149 1150 enum { 1151 MLX5_UC_ADDR_CHANGE = (1 << 0), 1152 MLX5_MC_ADDR_CHANGE = (1 << 1), 1153 MLX5_VLAN_CHANGE = (1 << 2), 1154 MLX5_PROMISC_CHANGE = (1 << 3), 1155 MLX5_MTU_CHANGE = (1 << 4), 1156 }; 1157 1158 enum mlx5_list_type { 1159 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 1160 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 1161 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 1162 }; 1163 1164 enum { 1165 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 1166 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 1167 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 1168 }; 1169 1170 /* MLX5 DEV CAPs */ 1171 1172 /* TODO: EAT.ME */ 1173 enum mlx5_cap_mode { 1174 HCA_CAP_OPMOD_GET_MAX = 0, 1175 HCA_CAP_OPMOD_GET_CUR = 1, 1176 }; 1177 1178 enum mlx5_cap_type { 1179 MLX5_CAP_GENERAL = 0, 1180 MLX5_CAP_ETHERNET_OFFLOADS, 1181 MLX5_CAP_ODP, 1182 MLX5_CAP_ATOMIC, 1183 MLX5_CAP_ROCE, 1184 MLX5_CAP_IPOIB_OFFLOADS, 1185 MLX5_CAP_EOIB_OFFLOADS, 1186 MLX5_CAP_FLOW_TABLE, 1187 MLX5_CAP_ESWITCH_FLOW_TABLE, 1188 MLX5_CAP_ESWITCH, 1189 MLX5_CAP_SNAPSHOT, 1190 MLX5_CAP_VECTOR_CALC, 1191 MLX5_CAP_QOS, 1192 MLX5_CAP_DEBUG, 1193 /* NUM OF CAP Types */ 1194 MLX5_CAP_NUM 1195 }; 1196 1197 /* GET Dev Caps macros */ 1198 #define MLX5_CAP_GEN(mdev, cap) \ 1199 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1200 1201 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1202 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1203 1204 #define MLX5_CAP_ETH(mdev, cap) \ 1205 MLX5_GET(per_protocol_networking_offload_caps,\ 1206 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1207 1208 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1209 MLX5_GET(per_protocol_networking_offload_caps,\ 1210 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1211 1212 #define MLX5_CAP_ROCE(mdev, cap) \ 1213 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1214 1215 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1216 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1217 1218 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1219 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1220 1221 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1222 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1223 1224 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1225 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1226 1227 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1228 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1229 1230 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1231 MLX5_GET(flow_table_eswitch_cap, \ 1232 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1233 1234 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1235 MLX5_GET(flow_table_eswitch_cap, \ 1236 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1237 1238 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1239 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1240 1241 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1242 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1243 1244 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1245 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1246 1247 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1248 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1249 1250 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1251 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1252 1253 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1254 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1255 1256 #define MLX5_CAP_ESW(mdev, cap) \ 1257 MLX5_GET(e_switch_cap, \ 1258 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1259 1260 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1261 MLX5_GET(e_switch_cap, \ 1262 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1263 1264 #define MLX5_CAP_ODP(mdev, cap)\ 1265 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1266 1267 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1268 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1269 1270 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1271 MLX5_GET(snapshot_cap, \ 1272 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1273 1274 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1275 MLX5_GET(snapshot_cap, \ 1276 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1277 1278 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1279 MLX5_GET(per_protocol_networking_offload_caps,\ 1280 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1281 1282 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1283 MLX5_GET(per_protocol_networking_offload_caps,\ 1284 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1285 1286 #define MLX5_CAP_DEBUG(mdev, cap) \ 1287 MLX5_GET(debug_cap, \ 1288 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1289 1290 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1291 MLX5_GET(debug_cap, \ 1292 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1293 1294 #define MLX5_CAP_QOS(mdev, cap) \ 1295 MLX5_GET(qos_cap,\ 1296 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1297 1298 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 1299 MLX5_GET(qos_cap,\ 1300 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1301 1302 enum { 1303 MLX5_CMD_STAT_OK = 0x0, 1304 MLX5_CMD_STAT_INT_ERR = 0x1, 1305 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1306 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1307 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1308 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1309 MLX5_CMD_STAT_RES_BUSY = 0x6, 1310 MLX5_CMD_STAT_LIM_ERR = 0x8, 1311 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1312 MLX5_CMD_STAT_IX_ERR = 0xa, 1313 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1314 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1315 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1316 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1317 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1318 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1319 }; 1320 1321 enum { 1322 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1323 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1324 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1325 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1326 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1327 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1328 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1329 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1330 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1331 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1332 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1333 }; 1334 1335 enum { 1336 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1337 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1338 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1339 }; 1340 1341 enum { 1342 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1343 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1344 }; 1345 1346 enum { 1347 NUM_DRIVER_UARS = 4, 1348 NUM_LOW_LAT_UUARS = 4, 1349 }; 1350 1351 enum { 1352 MLX5_CAP_PORT_TYPE_IB = 0x0, 1353 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1354 }; 1355 1356 enum { 1357 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1358 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1359 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1360 }; 1361 1362 enum { 1363 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1364 }; 1365 1366 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1367 { 1368 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1369 return 0; 1370 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1371 } 1372 1373 struct mlx5_ifc_mcia_reg_bits { 1374 u8 l[0x1]; 1375 u8 reserved_0[0x7]; 1376 u8 module[0x8]; 1377 u8 reserved_1[0x8]; 1378 u8 status[0x8]; 1379 1380 u8 i2c_device_address[0x8]; 1381 u8 page_number[0x8]; 1382 u8 device_address[0x10]; 1383 1384 u8 reserved_2[0x10]; 1385 u8 size[0x10]; 1386 1387 u8 reserved_3[0x20]; 1388 1389 u8 dword_0[0x20]; 1390 u8 dword_1[0x20]; 1391 u8 dword_2[0x20]; 1392 u8 dword_3[0x20]; 1393 u8 dword_4[0x20]; 1394 u8 dword_5[0x20]; 1395 u8 dword_6[0x20]; 1396 u8 dword_7[0x20]; 1397 u8 dword_8[0x20]; 1398 u8 dword_9[0x20]; 1399 u8 dword_10[0x20]; 1400 u8 dword_11[0x20]; 1401 }; 1402 1403 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1404 1405 struct mlx5_mini_cqe8 { 1406 union { 1407 __be32 rx_hash_result; 1408 __be16 checksum; 1409 __be16 rsvd; 1410 struct { 1411 __be16 wqe_counter; 1412 u8 s_wqe_opcode; 1413 u8 reserved; 1414 } s_wqe_info; 1415 }; 1416 __be32 byte_cnt; 1417 }; 1418 1419 enum { 1420 MLX5_NO_INLINE_DATA, 1421 MLX5_INLINE_DATA32_SEG, 1422 MLX5_INLINE_DATA64_SEG, 1423 MLX5_COMPRESSED, 1424 }; 1425 1426 enum mlx5_exp_cqe_zip_recv_type { 1427 MLX5_CQE_FORMAT_HASH, 1428 MLX5_CQE_FORMAT_CSUM, 1429 }; 1430 1431 #define MLX5E_CQE_FORMAT_MASK 0xc 1432 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1433 { 1434 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1435 } 1436 1437 enum { 1438 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1439 }; 1440 1441 /* 8 regular priorities + 1 for multicast */ 1442 #define MLX5_NUM_BYPASS_FTS 9 1443 1444 #endif /* MLX5_DEVICE_H */ 1445