1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DEVICE_H 29 #define MLX5_DEVICE_H 30 31 #include <linux/types.h> 32 #include <rdma/ib_verbs.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define FW_INIT_TIMEOUT_MILI 2000 36 #define FW_INIT_WAIT_MS 2 37 #define FW_PRE_INIT_TIMEOUT_MILI 120000 38 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 75 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 85 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 86 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 87 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 88 << __mlx5_dw_bit_off(typ, fld))); \ 89 } while (0) 90 91 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 92 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 93 __mlx5_mask(typ, fld)) 94 95 #define MLX5_GET_PR(typ, p, fld) ({ \ 96 u32 ___t = MLX5_GET(typ, p, fld); \ 97 pr_debug(#fld " = 0x%x\n", ___t); \ 98 ___t; \ 99 }) 100 101 #define __MLX5_SET64(typ, p, fld, v) do { \ 102 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 103 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 104 } while (0) 105 106 #define MLX5_SET64(typ, p, fld, v) do { \ 107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 108 __MLX5_SET64(typ, p, fld, v); \ 109 } while (0) 110 111 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 113 __MLX5_SET64(typ, p, fld[idx], v); \ 114 } while (0) 115 116 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 117 118 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 119 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 120 __mlx5_mask16(typ, fld)) 121 122 #define MLX5_SET16(typ, p, fld, v) do { \ 123 u16 _v = v; \ 124 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 125 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 126 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 127 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 128 << __mlx5_16_bit_off(typ, fld))); \ 129 } while (0) 130 131 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 132 __mlx5_64_off(typ, fld))) 133 134 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 135 type_t tmp; \ 136 switch (sizeof(tmp)) { \ 137 case sizeof(u8): \ 138 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 139 break; \ 140 case sizeof(u16): \ 141 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 142 break; \ 143 case sizeof(u32): \ 144 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 145 break; \ 146 case sizeof(u64): \ 147 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 148 break; \ 149 } \ 150 tmp; \ 151 }) 152 153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 159 160 /* insert a value to a struct */ 161 #define MLX5_VSC_SET(typ, p, fld, v) do { \ 162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 167 << __mlx5_dw_bit_off(typ, fld))); \ 168 } while (0) 169 170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 172 __mlx5_mask(typ, fld)) 173 174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 176 pr_debug(#fld " = 0x%x\n", ___t); \ 177 ___t; \ 178 }) 179 180 enum { 181 MLX5_MAX_COMMANDS = 32, 182 MLX5_CMD_DATA_BLOCK_SIZE = 512, 183 MLX5_CMD_MBOX_SIZE = 1024, 184 MLX5_PCI_CMD_XPORT = 7, 185 MLX5_MKEY_BSF_OCTO_SIZE = 4, 186 MLX5_MAX_PSVS = 4, 187 }; 188 189 enum { 190 MLX5_EXTENDED_UD_AV = 0x80000000, 191 }; 192 193 enum { 194 MLX5_CQ_FLAGS_OI = 2, 195 }; 196 197 enum { 198 MLX5_STAT_RATE_OFFSET = 5, 199 }; 200 201 enum { 202 MLX5_INLINE_SEG = 0x80000000, 203 }; 204 205 enum { 206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 207 }; 208 209 enum { 210 MLX5_MIN_PKEY_TABLE_SIZE = 128, 211 MLX5_MAX_LOG_PKEY_TABLE = 5, 212 }; 213 214 enum { 215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31 216 }; 217 218 enum { 219 MLX5_PERM_LOCAL_READ = 1 << 2, 220 MLX5_PERM_LOCAL_WRITE = 1 << 3, 221 MLX5_PERM_REMOTE_READ = 1 << 4, 222 MLX5_PERM_REMOTE_WRITE = 1 << 5, 223 MLX5_PERM_ATOMIC = 1 << 6, 224 MLX5_PERM_UMR_EN = 1 << 7, 225 }; 226 227 enum { 228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 233 }; 234 235 enum { 236 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 238 MLX5_MKEY_BSF_EN = 1 << 30, 239 MLX5_MKEY_LEN64 = 1U << 31, 240 }; 241 242 enum { 243 MLX5_EN_RD = (u64)1, 244 MLX5_EN_WR = (u64)2 245 }; 246 247 enum { 248 MLX5_BF_REGS_PER_PAGE = 4, 249 MLX5_MAX_UAR_PAGES = 1 << 8, 250 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 251 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 252 }; 253 254 enum { 255 MLX5_MKEY_MASK_LEN = 1ull << 0, 256 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 257 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 258 MLX5_MKEY_MASK_PD = 1ull << 7, 259 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 260 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 261 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 262 MLX5_MKEY_MASK_KEY = 1ull << 13, 263 MLX5_MKEY_MASK_QPN = 1ull << 14, 264 MLX5_MKEY_MASK_LR = 1ull << 17, 265 MLX5_MKEY_MASK_LW = 1ull << 18, 266 MLX5_MKEY_MASK_RR = 1ull << 19, 267 MLX5_MKEY_MASK_RW = 1ull << 20, 268 MLX5_MKEY_MASK_A = 1ull << 21, 269 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 270 MLX5_MKEY_MASK_FREE = 1ull << 29, 271 }; 272 273 enum { 274 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 275 276 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 277 MLX5_UMR_CHECK_FREE = (2 << 5), 278 279 MLX5_UMR_INLINE = (1 << 7), 280 }; 281 282 #define MLX5_UMR_MTT_ALIGNMENT 0x40 283 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 284 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 285 286 enum { 287 MLX5_EVENT_QUEUE_TYPE_QP = 0, 288 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 289 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 290 }; 291 292 enum { 293 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 294 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 295 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 296 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 297 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 298 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 299 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 300 }; 301 302 enum { 303 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 304 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 305 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 306 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 307 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 308 }; 309 310 enum { 311 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 312 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 313 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 314 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 315 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 316 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 317 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 318 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 319 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 320 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 321 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 322 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 323 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 324 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 325 }; 326 327 enum { 328 MLX5_ROCE_VERSION_1 = 0, 329 MLX5_ROCE_VERSION_1_5 = 1, 330 MLX5_ROCE_VERSION_2 = 2, 331 }; 332 333 enum { 334 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 335 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 336 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 337 }; 338 339 enum { 340 MLX5_ROCE_L3_TYPE_IPV4 = 0, 341 MLX5_ROCE_L3_TYPE_IPV6 = 1, 342 }; 343 344 enum { 345 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 346 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 347 }; 348 349 enum { 350 MLX5_OPCODE_NOP = 0x00, 351 MLX5_OPCODE_SEND_INVAL = 0x01, 352 MLX5_OPCODE_RDMA_WRITE = 0x08, 353 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 354 MLX5_OPCODE_SEND = 0x0a, 355 MLX5_OPCODE_SEND_IMM = 0x0b, 356 MLX5_OPCODE_LSO = 0x0e, 357 MLX5_OPCODE_RDMA_READ = 0x10, 358 MLX5_OPCODE_ATOMIC_CS = 0x11, 359 MLX5_OPCODE_ATOMIC_FA = 0x12, 360 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 361 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 362 MLX5_OPCODE_BIND_MW = 0x18, 363 MLX5_OPCODE_CONFIG_CMD = 0x1f, 364 365 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 366 MLX5_RECV_OPCODE_SEND = 0x01, 367 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 368 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 369 370 MLX5_CQE_OPCODE_ERROR = 0x1e, 371 MLX5_CQE_OPCODE_RESIZE = 0x16, 372 373 MLX5_OPCODE_SET_PSV = 0x20, 374 MLX5_OPCODE_GET_PSV = 0x21, 375 MLX5_OPCODE_CHECK_PSV = 0x22, 376 MLX5_OPCODE_RGET_PSV = 0x26, 377 MLX5_OPCODE_RCHECK_PSV = 0x27, 378 379 MLX5_OPCODE_UMR = 0x25, 380 381 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 382 }; 383 384 enum { 385 MLX5_OPCODE_MOD_UMR_UMR = 0x0, 386 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1, 387 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2, 388 }; 389 390 enum { 391 MLX5_OPCODE_MOD_PSV_PSV = 0x0, 392 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1, 393 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2, 394 }; 395 396 enum { 397 MLX5_SET_PORT_RESET_QKEY = 0, 398 MLX5_SET_PORT_GUID0 = 16, 399 MLX5_SET_PORT_NODE_GUID = 17, 400 MLX5_SET_PORT_SYS_GUID = 18, 401 MLX5_SET_PORT_GID_TABLE = 19, 402 MLX5_SET_PORT_PKEY_TABLE = 20, 403 }; 404 405 enum { 406 MLX5_MAX_PAGE_SHIFT = 31 407 }; 408 409 enum { 410 MLX5_ADAPTER_PAGE_SHIFT = 12, 411 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 412 }; 413 414 enum { 415 MLX5_CAP_OFF_CMDIF_CSUM = 46, 416 }; 417 418 enum { 419 /* 420 * Max wqe size for rdma read is 512 bytes, so this 421 * limits our max_sge_rd as the wqe needs to fit: 422 * - ctrl segment (16 bytes) 423 * - rdma segment (16 bytes) 424 * - scatter elements (16 bytes each) 425 */ 426 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 427 }; 428 429 struct mlx5_cmd_layout { 430 u8 type; 431 u8 rsvd0[3]; 432 __be32 inlen; 433 __be64 in_ptr; 434 __be32 in[4]; 435 __be32 out[4]; 436 __be64 out_ptr; 437 __be32 outlen; 438 u8 token; 439 u8 sig; 440 u8 rsvd1; 441 u8 status_own; 442 }; 443 444 enum mlx5_fatal_assert_bit_offsets { 445 MLX5_RFR_OFFSET = 31, 446 }; 447 448 struct mlx5_health_buffer { 449 __be32 assert_var[5]; 450 __be32 rsvd0[3]; 451 __be32 assert_exit_ptr; 452 __be32 assert_callra; 453 __be32 rsvd1[2]; 454 __be32 fw_ver; 455 __be32 hw_id; 456 __be32 rfr; 457 u8 irisc_index; 458 u8 synd; 459 __be16 ext_synd; 460 }; 461 462 enum mlx5_initializing_bit_offsets { 463 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 464 }; 465 466 enum mlx5_cmd_addr_l_sz_offset { 467 MLX5_NIC_IFC_OFFSET = 8, 468 }; 469 470 struct mlx5_init_seg { 471 __be32 fw_rev; 472 __be32 cmdif_rev_fw_sub; 473 __be32 rsvd0[2]; 474 __be32 cmdq_addr_h; 475 __be32 cmdq_addr_l_sz; 476 __be32 cmd_dbell; 477 __be32 rsvd1[120]; 478 __be32 initializing; 479 struct mlx5_health_buffer health; 480 __be32 rsvd2[880]; 481 __be32 internal_timer_h; 482 __be32 internal_timer_l; 483 __be32 rsvd3[2]; 484 __be32 health_counter; 485 __be32 rsvd4[1019]; 486 __be64 ieee1588_clk; 487 __be32 ieee1588_clk_type; 488 __be32 clr_intx; 489 }; 490 491 struct mlx5_eqe_comp { 492 __be32 reserved[6]; 493 __be32 cqn; 494 }; 495 496 struct mlx5_eqe_qp_srq { 497 __be32 reserved[6]; 498 __be32 qp_srq_n; 499 }; 500 501 struct mlx5_eqe_cq_err { 502 __be32 cqn; 503 u8 reserved1[7]; 504 u8 syndrome; 505 }; 506 507 struct mlx5_eqe_port_state { 508 u8 reserved0[8]; 509 u8 port; 510 }; 511 512 struct mlx5_eqe_gpio { 513 __be32 reserved0[2]; 514 __be64 gpio_event; 515 }; 516 517 struct mlx5_eqe_congestion { 518 u8 type; 519 u8 rsvd0; 520 u8 congestion_level; 521 }; 522 523 struct mlx5_eqe_stall_vl { 524 u8 rsvd0[3]; 525 u8 port_vl; 526 }; 527 528 struct mlx5_eqe_cmd { 529 __be32 vector; 530 __be32 rsvd[6]; 531 }; 532 533 struct mlx5_eqe_page_req { 534 u8 rsvd0[2]; 535 __be16 func_id; 536 __be32 num_pages; 537 __be32 rsvd1[5]; 538 }; 539 540 struct mlx5_eqe_vport_change { 541 u8 rsvd0[2]; 542 __be16 vport_num; 543 __be32 rsvd1[6]; 544 }; 545 546 547 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 548 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 549 550 enum { 551 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 552 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 553 MLX5_MODULE_STATUS_ERROR = 0x3, 554 MLX5_MODULE_STATUS_NUM , 555 }; 556 557 enum { 558 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 559 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 560 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 561 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 562 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 563 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 564 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 565 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 566 MLX5_MODULE_EVENT_ERROR_NUM , 567 }; 568 569 struct mlx5_eqe_port_module_event { 570 u8 rsvd0; 571 u8 module; 572 u8 rsvd1; 573 u8 module_status; 574 u8 rsvd2[2]; 575 u8 error_type; 576 }; 577 578 struct mlx5_eqe_general_notification_event { 579 u32 rq_user_index_delay_drop; 580 u32 rsvd0[6]; 581 }; 582 583 struct mlx5_eqe_temp_warning { 584 __be64 sensor_warning_msb; 585 __be64 sensor_warning_lsb; 586 } __packed; 587 588 union ev_data { 589 __be32 raw[7]; 590 struct mlx5_eqe_cmd cmd; 591 struct mlx5_eqe_comp comp; 592 struct mlx5_eqe_qp_srq qp_srq; 593 struct mlx5_eqe_cq_err cq_err; 594 struct mlx5_eqe_port_state port; 595 struct mlx5_eqe_gpio gpio; 596 struct mlx5_eqe_congestion cong; 597 struct mlx5_eqe_stall_vl stall_vl; 598 struct mlx5_eqe_page_req req_pages; 599 struct mlx5_eqe_port_module_event port_module_event; 600 struct mlx5_eqe_vport_change vport_change; 601 struct mlx5_eqe_general_notification_event general_notifications; 602 struct mlx5_eqe_temp_warning temp_warning; 603 } __packed; 604 605 struct mlx5_eqe { 606 u8 rsvd0; 607 u8 type; 608 u8 rsvd1; 609 u8 sub_type; 610 __be32 rsvd2[7]; 611 union ev_data data; 612 __be16 rsvd3; 613 u8 signature; 614 u8 owner; 615 } __packed; 616 617 struct mlx5_cmd_prot_block { 618 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 619 u8 rsvd0[48]; 620 __be64 next; 621 __be32 block_num; 622 u8 rsvd1; 623 u8 token; 624 u8 ctrl_sig; 625 u8 sig; 626 }; 627 628 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 629 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 630 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 631 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 632 633 enum { 634 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 635 }; 636 637 struct mlx5_err_cqe { 638 u8 rsvd0[32]; 639 __be32 srqn; 640 u8 rsvd1[18]; 641 u8 vendor_err_synd; 642 u8 syndrome; 643 __be32 s_wqe_opcode_qpn; 644 __be16 wqe_counter; 645 u8 signature; 646 u8 op_own; 647 }; 648 649 struct mlx5_cqe64 { 650 u8 tunneled_etc; 651 u8 rsvd0[3]; 652 u8 lro_tcppsh_abort_dupack; 653 u8 lro_min_ttl; 654 __be16 lro_tcp_win; 655 __be32 lro_ack_seq_num; 656 __be32 rss_hash_result; 657 u8 rss_hash_type; 658 u8 ml_path; 659 u8 rsvd20[2]; 660 __be16 check_sum; 661 __be16 slid; 662 __be32 flags_rqpn; 663 u8 hds_ip_ext; 664 u8 l4_hdr_type_etc; 665 __be16 vlan_info; 666 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 667 __be32 imm_inval_pkey; 668 u8 rsvd40[4]; 669 __be32 byte_cnt; 670 __be64 timestamp; 671 __be32 sop_drop_qpn; 672 __be16 wqe_counter; 673 u8 signature; 674 u8 op_own; 675 }; 676 677 #define MLX5_CQE_TSTMP_PTP (1ULL << 63) 678 679 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 680 { 681 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 682 } 683 684 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 685 { 686 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 687 } 688 689 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 690 { 691 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 692 } 693 694 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 695 { 696 return be16_to_cpu(cqe->vlan_info) & 0xfff; 697 } 698 699 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 700 { 701 memcpy(smac, &cqe->rss_hash_type , 4); 702 memcpy(smac + 4, &cqe->slid , 2); 703 } 704 705 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 706 { 707 return cqe->l4_hdr_type_etc & 0x1; 708 } 709 710 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 711 { 712 return cqe->tunneled_etc & 0x1; 713 } 714 715 enum { 716 CQE_L4_HDR_TYPE_NONE = 0x0, 717 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 718 CQE_L4_HDR_TYPE_UDP = 0x2, 719 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 720 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 721 }; 722 723 enum { 724 /* source L3 hash types */ 725 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 726 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 727 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 728 729 /* destination L3 hash types */ 730 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 731 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 732 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 733 734 /* source L4 hash types */ 735 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 736 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 737 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 738 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 739 740 /* destination L4 hash types */ 741 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 742 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 743 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 744 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 745 }; 746 747 enum { 748 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 749 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 750 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 751 }; 752 753 enum { 754 CQE_L2_OK = 1 << 0, 755 CQE_L3_OK = 1 << 1, 756 CQE_L4_OK = 1 << 2, 757 }; 758 759 struct mlx5_sig_err_cqe { 760 u8 rsvd0[16]; 761 __be32 expected_trans_sig; 762 __be32 actual_trans_sig; 763 __be32 expected_reftag; 764 __be32 actual_reftag; 765 __be16 syndrome; 766 u8 rsvd22[2]; 767 __be32 mkey; 768 __be64 err_offset; 769 u8 rsvd30[8]; 770 __be32 qpn; 771 u8 rsvd38[2]; 772 u8 signature; 773 u8 op_own; 774 }; 775 776 struct mlx5_wqe_srq_next_seg { 777 u8 rsvd0[2]; 778 __be16 next_wqe_index; 779 u8 signature; 780 u8 rsvd1[11]; 781 }; 782 783 union mlx5_ext_cqe { 784 struct ib_grh grh; 785 u8 inl[64]; 786 }; 787 788 struct mlx5_cqe128 { 789 union mlx5_ext_cqe inl_grh; 790 struct mlx5_cqe64 cqe64; 791 }; 792 793 enum { 794 MLX5_MKEY_STATUS_FREE = 1 << 6, 795 }; 796 797 struct mlx5_mkey_seg { 798 /* This is a two bit field occupying bits 31-30. 799 * bit 31 is always 0, 800 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 801 */ 802 u8 status; 803 u8 pcie_control; 804 u8 flags; 805 u8 version; 806 __be32 qpn_mkey7_0; 807 u8 rsvd1[4]; 808 __be32 flags_pd; 809 __be64 start_addr; 810 __be64 len; 811 __be32 bsfs_octo_size; 812 u8 rsvd2[16]; 813 __be32 xlt_oct_size; 814 u8 rsvd3[3]; 815 u8 log2_page_size; 816 u8 rsvd4[4]; 817 }; 818 819 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 820 821 enum { 822 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 823 }; 824 825 static inline int mlx5_host_is_le(void) 826 { 827 #if defined(__LITTLE_ENDIAN) 828 return 1; 829 #elif defined(__BIG_ENDIAN) 830 return 0; 831 #else 832 #error Host endianness not defined 833 #endif 834 } 835 836 #define MLX5_CMD_OP_MAX 0x939 837 838 enum { 839 VPORT_STATE_DOWN = 0x0, 840 VPORT_STATE_UP = 0x1, 841 }; 842 843 enum { 844 MLX5_L3_PROT_TYPE_IPV4 = 0, 845 MLX5_L3_PROT_TYPE_IPV6 = 1, 846 }; 847 848 enum { 849 MLX5_L4_PROT_TYPE_TCP = 0, 850 MLX5_L4_PROT_TYPE_UDP = 1, 851 }; 852 853 enum { 854 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 855 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 856 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 857 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 858 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 859 }; 860 861 enum { 862 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 863 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 864 MLX5_MATCH_INNER_HEADERS = 1 << 2, 865 866 }; 867 868 enum { 869 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 870 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 871 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 872 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 873 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 874 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 875 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 876 }; 877 878 enum { 879 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 880 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 881 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 882 }; 883 884 enum { 885 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 886 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 887 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 888 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 889 }; 890 891 enum { 892 MLX5_UC_ADDR_CHANGE = (1 << 0), 893 MLX5_MC_ADDR_CHANGE = (1 << 1), 894 MLX5_VLAN_CHANGE = (1 << 2), 895 MLX5_PROMISC_CHANGE = (1 << 3), 896 MLX5_MTU_CHANGE = (1 << 4), 897 }; 898 899 enum mlx5_list_type { 900 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 901 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 902 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 903 }; 904 905 enum { 906 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 907 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 908 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 909 }; 910 911 /* MLX5 DEV CAPs */ 912 913 /* TODO: EAT.ME */ 914 enum mlx5_cap_mode { 915 HCA_CAP_OPMOD_GET_MAX = 0, 916 HCA_CAP_OPMOD_GET_CUR = 1, 917 }; 918 919 enum mlx5_cap_type { 920 MLX5_CAP_GENERAL = 0, 921 MLX5_CAP_ETHERNET_OFFLOADS, 922 MLX5_CAP_ODP, 923 MLX5_CAP_ATOMIC, 924 MLX5_CAP_ROCE, 925 MLX5_CAP_IPOIB_OFFLOADS, 926 MLX5_CAP_EOIB_OFFLOADS, 927 MLX5_CAP_FLOW_TABLE, 928 MLX5_CAP_ESWITCH_FLOW_TABLE, 929 MLX5_CAP_ESWITCH, 930 MLX5_CAP_SNAPSHOT, 931 MLX5_CAP_VECTOR_CALC, 932 MLX5_CAP_QOS, 933 MLX5_CAP_DEBUG, 934 MLX5_CAP_NVME, 935 MLX5_CAP_DMC, 936 MLX5_CAP_DEC, 937 MLX5_CAP_TLS, 938 /* NUM OF CAP Types */ 939 MLX5_CAP_NUM 940 }; 941 942 enum mlx5_qcam_reg_groups { 943 MLX5_QCAM_REGS_FIRST_128 = 0x0, 944 }; 945 946 enum mlx5_qcam_feature_groups { 947 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 948 }; 949 950 enum mlx5_pcam_reg_groups { 951 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 952 }; 953 954 enum mlx5_pcam_feature_groups { 955 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 956 }; 957 958 enum mlx5_mcam_reg_groups { 959 MLX5_MCAM_REGS_FIRST_128 = 0x0, 960 }; 961 962 enum mlx5_mcam_feature_groups { 963 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 964 }; 965 966 /* GET Dev Caps macros */ 967 #define MLX5_CAP_GEN(mdev, cap) \ 968 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 969 970 #define MLX5_CAP_GEN_64(mdev, cap) \ 971 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 972 973 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 974 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 975 976 #define MLX5_CAP_ETH(mdev, cap) \ 977 MLX5_GET(per_protocol_networking_offload_caps,\ 978 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 979 980 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 981 MLX5_GET(per_protocol_networking_offload_caps,\ 982 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 983 984 #define MLX5_CAP_ROCE(mdev, cap) \ 985 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 986 987 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 988 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 989 990 #define MLX5_CAP_ATOMIC(mdev, cap) \ 991 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 992 993 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 994 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 995 996 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 997 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 998 999 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1000 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1001 1002 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1003 MLX5_GET(flow_table_eswitch_cap, \ 1004 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1005 1006 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1007 MLX5_GET(flow_table_eswitch_cap, \ 1008 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1009 1010 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1011 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1012 1013 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1014 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1015 1016 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1017 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1018 1019 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1020 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1021 1022 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1023 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1024 1025 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1026 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1027 1028 #define MLX5_CAP_ESW(mdev, cap) \ 1029 MLX5_GET(e_switch_cap, \ 1030 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1031 1032 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1033 MLX5_GET(e_switch_cap, \ 1034 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1035 1036 #define MLX5_CAP_ODP(mdev, cap)\ 1037 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1038 1039 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1040 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1041 1042 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1043 MLX5_GET(snapshot_cap, \ 1044 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1045 1046 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1047 MLX5_GET(snapshot_cap, \ 1048 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1049 1050 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1051 MLX5_GET(per_protocol_networking_offload_caps,\ 1052 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1053 1054 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1055 MLX5_GET(per_protocol_networking_offload_caps,\ 1056 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1057 1058 #define MLX5_CAP_DEBUG(mdev, cap) \ 1059 MLX5_GET(debug_cap, \ 1060 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1061 1062 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1063 MLX5_GET(debug_cap, \ 1064 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1065 1066 #define MLX5_CAP_QOS(mdev, cap) \ 1067 MLX5_GET(qos_cap,\ 1068 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1069 1070 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 1071 MLX5_GET(qos_cap,\ 1072 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1073 1074 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1075 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1076 1077 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1078 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1079 1080 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1081 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1082 1083 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1084 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1085 1086 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1087 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1088 1089 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1090 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1091 1092 #define MLX5_CAP_FPGA(mdev, cap) \ 1093 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1094 1095 #define MLX5_CAP64_FPGA(mdev, cap) \ 1096 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1097 1098 #define MLX5_CAP_TLS(mdev, cap) \ 1099 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap) 1100 1101 enum { 1102 MLX5_CMD_STAT_OK = 0x0, 1103 MLX5_CMD_STAT_INT_ERR = 0x1, 1104 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1105 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1106 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1107 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1108 MLX5_CMD_STAT_RES_BUSY = 0x6, 1109 MLX5_CMD_STAT_LIM_ERR = 0x8, 1110 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1111 MLX5_CMD_STAT_IX_ERR = 0xa, 1112 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1113 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1114 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1115 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1116 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1117 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1118 }; 1119 1120 enum { 1121 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1122 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1123 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1124 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1125 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1126 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1127 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1128 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1129 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1130 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1131 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1132 }; 1133 1134 enum { 1135 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1136 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1137 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1138 }; 1139 1140 enum { 1141 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1142 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1143 }; 1144 1145 enum { 1146 NUM_DRIVER_UARS = 4, 1147 NUM_LOW_LAT_UUARS = 4, 1148 }; 1149 1150 enum { 1151 MLX5_CAP_PORT_TYPE_IB = 0x0, 1152 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1153 }; 1154 1155 enum { 1156 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1157 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1158 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1159 }; 1160 1161 enum mlx5_inline_modes { 1162 MLX5_INLINE_MODE_NONE, 1163 MLX5_INLINE_MODE_L2, 1164 MLX5_INLINE_MODE_IP, 1165 MLX5_INLINE_MODE_TCP_UDP, 1166 }; 1167 1168 enum { 1169 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1170 }; 1171 1172 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1173 { 1174 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1175 return 0; 1176 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1177 } 1178 1179 struct mlx5_ifc_mcia_reg_bits { 1180 u8 l[0x1]; 1181 u8 reserved_0[0x7]; 1182 u8 module[0x8]; 1183 u8 reserved_1[0x8]; 1184 u8 status[0x8]; 1185 1186 u8 i2c_device_address[0x8]; 1187 u8 page_number[0x8]; 1188 u8 device_address[0x10]; 1189 1190 u8 reserved_2[0x10]; 1191 u8 size[0x10]; 1192 1193 u8 reserved_3[0x20]; 1194 1195 u8 dword_0[0x20]; 1196 u8 dword_1[0x20]; 1197 u8 dword_2[0x20]; 1198 u8 dword_3[0x20]; 1199 u8 dword_4[0x20]; 1200 u8 dword_5[0x20]; 1201 u8 dword_6[0x20]; 1202 u8 dword_7[0x20]; 1203 u8 dword_8[0x20]; 1204 u8 dword_9[0x20]; 1205 u8 dword_10[0x20]; 1206 u8 dword_11[0x20]; 1207 }; 1208 1209 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1210 1211 struct mlx5_mini_cqe8 { 1212 union { 1213 __be32 rx_hash_result; 1214 __be16 checksum; 1215 __be16 rsvd; 1216 struct { 1217 __be16 wqe_counter; 1218 u8 s_wqe_opcode; 1219 u8 reserved; 1220 } s_wqe_info; 1221 }; 1222 __be32 byte_cnt; 1223 }; 1224 1225 enum { 1226 MLX5_NO_INLINE_DATA, 1227 MLX5_INLINE_DATA32_SEG, 1228 MLX5_INLINE_DATA64_SEG, 1229 MLX5_COMPRESSED, 1230 }; 1231 1232 enum mlx5_exp_cqe_zip_recv_type { 1233 MLX5_CQE_FORMAT_HASH, 1234 MLX5_CQE_FORMAT_CSUM, 1235 }; 1236 1237 #define MLX5E_CQE_FORMAT_MASK 0xc 1238 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1239 { 1240 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1241 } 1242 1243 enum { 1244 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1245 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 1246 }; 1247 1248 enum { 1249 MLX5_FRL_LEVEL3 = 0x8, 1250 MLX5_FRL_LEVEL6 = 0x40, 1251 }; 1252 1253 /* 8 regular priorities + 1 for multicast */ 1254 #define MLX5_NUM_BYPASS_FTS 9 1255 1256 #endif /* MLX5_DEVICE_H */ 1257