1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DEVICE_H 29 #define MLX5_DEVICE_H 30 31 #include <linux/types.h> 32 #include <rdma/ib_verbs.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define FW_INIT_TIMEOUT_MILI 2000 36 #define FW_INIT_WAIT_MS 2 37 38 #if defined(__LITTLE_ENDIAN) 39 #define MLX5_SET_HOST_ENDIANNESS 0 40 #elif defined(__BIG_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0x80 42 #else 43 #error Host endianness not defined 44 #endif 45 46 /* helper macros */ 47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 51 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 52 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 53 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 54 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 55 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 56 57 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 58 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 59 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 60 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 61 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 62 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 63 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 64 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 65 66 /* insert a value to a struct */ 67 #define MLX5_SET(typ, p, fld, v) do { \ 68 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 69 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73 << __mlx5_dw_bit_off(typ, fld))); \ 74 } while (0) 75 76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 82 << __mlx5_dw_bit_off(typ, fld))); \ 83 } while (0) 84 85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 87 __mlx5_mask(typ, fld)) 88 89 #define MLX5_GET_PR(typ, p, fld) ({ \ 90 u32 ___t = MLX5_GET(typ, p, fld); \ 91 pr_debug(#fld " = 0x%x\n", ___t); \ 92 ___t; \ 93 }) 94 95 #define __MLX5_SET64(typ, p, fld, v) do { \ 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 98 } while (0) 99 100 #define MLX5_SET64(typ, p, fld, v) do { \ 101 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 102 __MLX5_SET64(typ, p, fld, v); \ 103 } while (0) 104 105 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 107 __MLX5_SET64(typ, p, fld[idx], v); \ 108 } while (0) 109 110 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 111 112 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 113 __mlx5_64_off(typ, fld))) 114 115 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 116 type_t tmp; \ 117 switch (sizeof(tmp)) { \ 118 case sizeof(u8): \ 119 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 120 break; \ 121 case sizeof(u16): \ 122 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 123 break; \ 124 case sizeof(u32): \ 125 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 126 break; \ 127 case sizeof(u64): \ 128 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 129 break; \ 130 } \ 131 tmp; \ 132 }) 133 134 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 135 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 136 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 137 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 138 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 139 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 140 141 enum { 142 MLX5_MAX_COMMANDS = 32, 143 MLX5_CMD_DATA_BLOCK_SIZE = 512, 144 MLX5_CMD_MBOX_SIZE = 1024, 145 MLX5_PCI_CMD_XPORT = 7, 146 MLX5_MKEY_BSF_OCTO_SIZE = 4, 147 MLX5_MAX_PSVS = 4, 148 }; 149 150 enum { 151 MLX5_EXTENDED_UD_AV = 0x80000000, 152 }; 153 154 enum { 155 MLX5_CQ_FLAGS_OI = 2, 156 }; 157 158 enum { 159 MLX5_STAT_RATE_OFFSET = 5, 160 }; 161 162 enum { 163 MLX5_INLINE_SEG = 0x80000000, 164 }; 165 166 enum { 167 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 168 }; 169 170 enum { 171 MLX5_MIN_PKEY_TABLE_SIZE = 128, 172 MLX5_MAX_LOG_PKEY_TABLE = 5, 173 }; 174 175 enum { 176 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31 177 }; 178 179 enum { 180 MLX5_PERM_LOCAL_READ = 1 << 2, 181 MLX5_PERM_LOCAL_WRITE = 1 << 3, 182 MLX5_PERM_REMOTE_READ = 1 << 4, 183 MLX5_PERM_REMOTE_WRITE = 1 << 5, 184 MLX5_PERM_ATOMIC = 1 << 6, 185 MLX5_PERM_UMR_EN = 1 << 7, 186 }; 187 188 enum { 189 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 190 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 191 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 192 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 193 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 194 }; 195 196 enum { 197 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 198 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 199 MLX5_MKEY_BSF_EN = 1 << 30, 200 MLX5_MKEY_LEN64 = 1U << 31, 201 }; 202 203 enum { 204 MLX5_EN_RD = (u64)1, 205 MLX5_EN_WR = (u64)2 206 }; 207 208 enum { 209 MLX5_BF_REGS_PER_PAGE = 4, 210 MLX5_MAX_UAR_PAGES = 1 << 8, 211 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 212 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 213 }; 214 215 enum { 216 MLX5_MKEY_MASK_LEN = 1ull << 0, 217 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 218 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 219 MLX5_MKEY_MASK_PD = 1ull << 7, 220 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 221 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 222 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 223 MLX5_MKEY_MASK_KEY = 1ull << 13, 224 MLX5_MKEY_MASK_QPN = 1ull << 14, 225 MLX5_MKEY_MASK_LR = 1ull << 17, 226 MLX5_MKEY_MASK_LW = 1ull << 18, 227 MLX5_MKEY_MASK_RR = 1ull << 19, 228 MLX5_MKEY_MASK_RW = 1ull << 20, 229 MLX5_MKEY_MASK_A = 1ull << 21, 230 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 231 MLX5_MKEY_MASK_FREE = 1ull << 29, 232 }; 233 234 enum { 235 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 236 237 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 238 MLX5_UMR_CHECK_FREE = (2 << 5), 239 240 MLX5_UMR_INLINE = (1 << 7), 241 }; 242 243 #define MLX5_UMR_MTT_ALIGNMENT 0x40 244 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 245 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 246 247 enum { 248 MLX5_EVENT_QUEUE_TYPE_QP = 0, 249 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 250 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 251 }; 252 253 enum { 254 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 255 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 256 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 257 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 258 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 259 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 260 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 261 }; 262 263 enum { 264 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 265 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 266 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 267 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 268 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 269 }; 270 271 enum { 272 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 273 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 274 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 275 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 276 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 277 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 278 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 279 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 280 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 281 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 282 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 283 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 284 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 285 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 286 }; 287 288 enum { 289 MLX5_ROCE_VERSION_1 = 0, 290 MLX5_ROCE_VERSION_1_5 = 1, 291 MLX5_ROCE_VERSION_2 = 2, 292 }; 293 294 enum { 295 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 296 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 297 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 298 }; 299 300 enum { 301 MLX5_ROCE_L3_TYPE_IPV4 = 0, 302 MLX5_ROCE_L3_TYPE_IPV6 = 1, 303 }; 304 305 enum { 306 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 307 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 308 }; 309 310 enum { 311 MLX5_OPCODE_NOP = 0x00, 312 MLX5_OPCODE_SEND_INVAL = 0x01, 313 MLX5_OPCODE_RDMA_WRITE = 0x08, 314 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 315 MLX5_OPCODE_SEND = 0x0a, 316 MLX5_OPCODE_SEND_IMM = 0x0b, 317 MLX5_OPCODE_LSO = 0x0e, 318 MLX5_OPCODE_RDMA_READ = 0x10, 319 MLX5_OPCODE_ATOMIC_CS = 0x11, 320 MLX5_OPCODE_ATOMIC_FA = 0x12, 321 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 322 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 323 MLX5_OPCODE_BIND_MW = 0x18, 324 MLX5_OPCODE_CONFIG_CMD = 0x1f, 325 326 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 327 MLX5_RECV_OPCODE_SEND = 0x01, 328 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 329 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 330 331 MLX5_CQE_OPCODE_ERROR = 0x1e, 332 MLX5_CQE_OPCODE_RESIZE = 0x16, 333 334 MLX5_OPCODE_SET_PSV = 0x20, 335 MLX5_OPCODE_GET_PSV = 0x21, 336 MLX5_OPCODE_CHECK_PSV = 0x22, 337 MLX5_OPCODE_RGET_PSV = 0x26, 338 MLX5_OPCODE_RCHECK_PSV = 0x27, 339 340 MLX5_OPCODE_UMR = 0x25, 341 342 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 343 }; 344 345 enum { 346 MLX5_SET_PORT_RESET_QKEY = 0, 347 MLX5_SET_PORT_GUID0 = 16, 348 MLX5_SET_PORT_NODE_GUID = 17, 349 MLX5_SET_PORT_SYS_GUID = 18, 350 MLX5_SET_PORT_GID_TABLE = 19, 351 MLX5_SET_PORT_PKEY_TABLE = 20, 352 }; 353 354 enum { 355 MLX5_MAX_PAGE_SHIFT = 31 356 }; 357 358 enum { 359 MLX5_ADAPTER_PAGE_SHIFT = 12, 360 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 361 }; 362 363 enum { 364 MLX5_CAP_OFF_CMDIF_CSUM = 46, 365 }; 366 367 enum { 368 /* 369 * Max wqe size for rdma read is 512 bytes, so this 370 * limits our max_sge_rd as the wqe needs to fit: 371 * - ctrl segment (16 bytes) 372 * - rdma segment (16 bytes) 373 * - scatter elements (16 bytes each) 374 */ 375 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 376 }; 377 378 struct mlx5_cmd_layout { 379 u8 type; 380 u8 rsvd0[3]; 381 __be32 inlen; 382 __be64 in_ptr; 383 __be32 in[4]; 384 __be32 out[4]; 385 __be64 out_ptr; 386 __be32 outlen; 387 u8 token; 388 u8 sig; 389 u8 rsvd1; 390 u8 status_own; 391 }; 392 393 struct mlx5_health_buffer { 394 __be32 assert_var[5]; 395 __be32 rsvd0[3]; 396 __be32 assert_exit_ptr; 397 __be32 assert_callra; 398 __be32 rsvd1[2]; 399 __be32 fw_ver; 400 __be32 hw_id; 401 __be32 rsvd2; 402 u8 irisc_index; 403 u8 synd; 404 __be16 ext_synd; 405 }; 406 407 struct mlx5_init_seg { 408 __be32 fw_rev; 409 __be32 cmdif_rev_fw_sub; 410 __be32 rsvd0[2]; 411 __be32 cmdq_addr_h; 412 __be32 cmdq_addr_l_sz; 413 __be32 cmd_dbell; 414 __be32 rsvd1[120]; 415 __be32 initializing; 416 struct mlx5_health_buffer health; 417 __be32 rsvd2[880]; 418 __be32 internal_timer_h; 419 __be32 internal_timer_l; 420 __be32 rsvd3[2]; 421 __be32 health_counter; 422 __be32 rsvd4[1019]; 423 __be64 ieee1588_clk; 424 __be32 ieee1588_clk_type; 425 __be32 clr_intx; 426 }; 427 428 struct mlx5_eqe_comp { 429 __be32 reserved[6]; 430 __be32 cqn; 431 }; 432 433 struct mlx5_eqe_qp_srq { 434 __be32 reserved[6]; 435 __be32 qp_srq_n; 436 }; 437 438 struct mlx5_eqe_cq_err { 439 __be32 cqn; 440 u8 reserved1[7]; 441 u8 syndrome; 442 }; 443 444 struct mlx5_eqe_port_state { 445 u8 reserved0[8]; 446 u8 port; 447 }; 448 449 struct mlx5_eqe_gpio { 450 __be32 reserved0[2]; 451 __be64 gpio_event; 452 }; 453 454 struct mlx5_eqe_congestion { 455 u8 type; 456 u8 rsvd0; 457 u8 congestion_level; 458 }; 459 460 struct mlx5_eqe_stall_vl { 461 u8 rsvd0[3]; 462 u8 port_vl; 463 }; 464 465 struct mlx5_eqe_cmd { 466 __be32 vector; 467 __be32 rsvd[6]; 468 }; 469 470 struct mlx5_eqe_page_req { 471 u8 rsvd0[2]; 472 __be16 func_id; 473 __be32 num_pages; 474 __be32 rsvd1[5]; 475 }; 476 477 struct mlx5_eqe_vport_change { 478 u8 rsvd0[2]; 479 __be16 vport_num; 480 __be32 rsvd1[6]; 481 }; 482 483 484 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 485 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 486 487 enum { 488 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 489 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 490 MLX5_MODULE_STATUS_ERROR = 0x3, 491 MLX5_MODULE_STATUS_PLUGGED_DISABLED = 0x4, 492 }; 493 494 enum { 495 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 496 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 497 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 498 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 499 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 500 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 501 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 502 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 503 }; 504 505 struct mlx5_eqe_port_module_event { 506 u8 rsvd0; 507 u8 module; 508 u8 rsvd1; 509 u8 module_status; 510 u8 rsvd2[2]; 511 u8 error_type; 512 }; 513 514 struct mlx5_eqe_general_notification_event { 515 u32 rq_user_index_delay_drop; 516 u32 rsvd0[6]; 517 }; 518 519 union ev_data { 520 __be32 raw[7]; 521 struct mlx5_eqe_cmd cmd; 522 struct mlx5_eqe_comp comp; 523 struct mlx5_eqe_qp_srq qp_srq; 524 struct mlx5_eqe_cq_err cq_err; 525 struct mlx5_eqe_port_state port; 526 struct mlx5_eqe_gpio gpio; 527 struct mlx5_eqe_congestion cong; 528 struct mlx5_eqe_stall_vl stall_vl; 529 struct mlx5_eqe_page_req req_pages; 530 struct mlx5_eqe_port_module_event port_module_event; 531 struct mlx5_eqe_vport_change vport_change; 532 struct mlx5_eqe_general_notification_event general_notifications; 533 } __packed; 534 535 struct mlx5_eqe { 536 u8 rsvd0; 537 u8 type; 538 u8 rsvd1; 539 u8 sub_type; 540 __be32 rsvd2[7]; 541 union ev_data data; 542 __be16 rsvd3; 543 u8 signature; 544 u8 owner; 545 } __packed; 546 547 struct mlx5_cmd_prot_block { 548 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 549 u8 rsvd0[48]; 550 __be64 next; 551 __be32 block_num; 552 u8 rsvd1; 553 u8 token; 554 u8 ctrl_sig; 555 u8 sig; 556 }; 557 558 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 559 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 560 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 561 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 562 563 enum { 564 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 565 }; 566 567 struct mlx5_err_cqe { 568 u8 rsvd0[32]; 569 __be32 srqn; 570 u8 rsvd1[18]; 571 u8 vendor_err_synd; 572 u8 syndrome; 573 __be32 s_wqe_opcode_qpn; 574 __be16 wqe_counter; 575 u8 signature; 576 u8 op_own; 577 }; 578 579 struct mlx5_cqe64 { 580 u8 tunneled_etc; 581 u8 rsvd0[3]; 582 u8 lro_tcppsh_abort_dupack; 583 u8 lro_min_ttl; 584 __be16 lro_tcp_win; 585 __be32 lro_ack_seq_num; 586 __be32 rss_hash_result; 587 u8 rss_hash_type; 588 u8 ml_path; 589 u8 rsvd20[2]; 590 __be16 check_sum; 591 __be16 slid; 592 __be32 flags_rqpn; 593 u8 hds_ip_ext; 594 u8 l4_hdr_type_etc; 595 __be16 vlan_info; 596 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 597 __be32 imm_inval_pkey; 598 u8 rsvd40[4]; 599 __be32 byte_cnt; 600 __be64 timestamp; 601 __be32 sop_drop_qpn; 602 __be16 wqe_counter; 603 u8 signature; 604 u8 op_own; 605 }; 606 607 #define MLX5_CQE_TSTMP_PTP (1ULL << 63) 608 609 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 610 { 611 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 612 } 613 614 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 615 { 616 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 617 } 618 619 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 620 { 621 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 622 } 623 624 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 625 { 626 return be16_to_cpu(cqe->vlan_info) & 0xfff; 627 } 628 629 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 630 { 631 memcpy(smac, &cqe->rss_hash_type , 4); 632 memcpy(smac + 4, &cqe->slid , 2); 633 } 634 635 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 636 { 637 return cqe->l4_hdr_type_etc & 0x1; 638 } 639 640 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 641 { 642 return cqe->tunneled_etc & 0x1; 643 } 644 645 enum { 646 CQE_L4_HDR_TYPE_NONE = 0x0, 647 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 648 CQE_L4_HDR_TYPE_UDP = 0x2, 649 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 650 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 651 }; 652 653 enum { 654 /* source L3 hash types */ 655 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 656 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 657 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 658 659 /* destination L3 hash types */ 660 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 661 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 662 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 663 664 /* source L4 hash types */ 665 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 666 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 667 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 668 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 669 670 /* destination L4 hash types */ 671 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 672 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 673 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 674 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 675 }; 676 677 enum { 678 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 679 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 680 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 681 }; 682 683 enum { 684 CQE_L2_OK = 1 << 0, 685 CQE_L3_OK = 1 << 1, 686 CQE_L4_OK = 1 << 2, 687 }; 688 689 struct mlx5_sig_err_cqe { 690 u8 rsvd0[16]; 691 __be32 expected_trans_sig; 692 __be32 actual_trans_sig; 693 __be32 expected_reftag; 694 __be32 actual_reftag; 695 __be16 syndrome; 696 u8 rsvd22[2]; 697 __be32 mkey; 698 __be64 err_offset; 699 u8 rsvd30[8]; 700 __be32 qpn; 701 u8 rsvd38[2]; 702 u8 signature; 703 u8 op_own; 704 }; 705 706 struct mlx5_wqe_srq_next_seg { 707 u8 rsvd0[2]; 708 __be16 next_wqe_index; 709 u8 signature; 710 u8 rsvd1[11]; 711 }; 712 713 union mlx5_ext_cqe { 714 struct ib_grh grh; 715 u8 inl[64]; 716 }; 717 718 struct mlx5_cqe128 { 719 union mlx5_ext_cqe inl_grh; 720 struct mlx5_cqe64 cqe64; 721 }; 722 723 enum { 724 MLX5_MKEY_STATUS_FREE = 1 << 6, 725 }; 726 727 struct mlx5_mkey_seg { 728 /* This is a two bit field occupying bits 31-30. 729 * bit 31 is always 0, 730 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 731 */ 732 u8 status; 733 u8 pcie_control; 734 u8 flags; 735 u8 version; 736 __be32 qpn_mkey7_0; 737 u8 rsvd1[4]; 738 __be32 flags_pd; 739 __be64 start_addr; 740 __be64 len; 741 __be32 bsfs_octo_size; 742 u8 rsvd2[16]; 743 __be32 xlt_oct_size; 744 u8 rsvd3[3]; 745 u8 log2_page_size; 746 u8 rsvd4[4]; 747 }; 748 749 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 750 751 enum { 752 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 753 }; 754 755 static inline int mlx5_host_is_le(void) 756 { 757 #if defined(__LITTLE_ENDIAN) 758 return 1; 759 #elif defined(__BIG_ENDIAN) 760 return 0; 761 #else 762 #error Host endianness not defined 763 #endif 764 } 765 766 #define MLX5_CMD_OP_MAX 0x939 767 768 enum { 769 VPORT_STATE_DOWN = 0x0, 770 VPORT_STATE_UP = 0x1, 771 }; 772 773 enum { 774 MLX5_L3_PROT_TYPE_IPV4 = 0, 775 MLX5_L3_PROT_TYPE_IPV6 = 1, 776 }; 777 778 enum { 779 MLX5_L4_PROT_TYPE_TCP = 0, 780 MLX5_L4_PROT_TYPE_UDP = 1, 781 }; 782 783 enum { 784 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 785 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 786 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 787 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 788 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 789 }; 790 791 enum { 792 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 793 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 794 MLX5_MATCH_INNER_HEADERS = 1 << 2, 795 796 }; 797 798 enum { 799 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 800 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 801 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 802 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 803 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 804 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 805 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 806 }; 807 808 enum { 809 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 810 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 811 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 812 }; 813 814 enum { 815 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 816 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 817 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 818 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 819 }; 820 821 enum { 822 MLX5_UC_ADDR_CHANGE = (1 << 0), 823 MLX5_MC_ADDR_CHANGE = (1 << 1), 824 MLX5_VLAN_CHANGE = (1 << 2), 825 MLX5_PROMISC_CHANGE = (1 << 3), 826 MLX5_MTU_CHANGE = (1 << 4), 827 }; 828 829 enum mlx5_list_type { 830 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 831 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 832 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 833 }; 834 835 enum { 836 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 837 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 838 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 839 }; 840 841 /* MLX5 DEV CAPs */ 842 843 /* TODO: EAT.ME */ 844 enum mlx5_cap_mode { 845 HCA_CAP_OPMOD_GET_MAX = 0, 846 HCA_CAP_OPMOD_GET_CUR = 1, 847 }; 848 849 enum mlx5_cap_type { 850 MLX5_CAP_GENERAL = 0, 851 MLX5_CAP_ETHERNET_OFFLOADS, 852 MLX5_CAP_ODP, 853 MLX5_CAP_ATOMIC, 854 MLX5_CAP_ROCE, 855 MLX5_CAP_IPOIB_OFFLOADS, 856 MLX5_CAP_EOIB_OFFLOADS, 857 MLX5_CAP_FLOW_TABLE, 858 MLX5_CAP_ESWITCH_FLOW_TABLE, 859 MLX5_CAP_ESWITCH, 860 MLX5_CAP_SNAPSHOT, 861 MLX5_CAP_VECTOR_CALC, 862 MLX5_CAP_QOS, 863 MLX5_CAP_DEBUG, 864 /* NUM OF CAP Types */ 865 MLX5_CAP_NUM 866 }; 867 868 /* GET Dev Caps macros */ 869 #define MLX5_CAP_GEN(mdev, cap) \ 870 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 871 872 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 873 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 874 875 #define MLX5_CAP_ETH(mdev, cap) \ 876 MLX5_GET(per_protocol_networking_offload_caps,\ 877 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 878 879 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 880 MLX5_GET(per_protocol_networking_offload_caps,\ 881 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 882 883 #define MLX5_CAP_ROCE(mdev, cap) \ 884 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 885 886 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 887 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 888 889 #define MLX5_CAP_ATOMIC(mdev, cap) \ 890 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 891 892 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 893 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 894 895 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 896 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 897 898 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 899 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 900 901 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 902 MLX5_GET(flow_table_eswitch_cap, \ 903 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 904 905 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 906 MLX5_GET(flow_table_eswitch_cap, \ 907 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 908 909 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 910 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 911 912 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 913 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 914 915 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 916 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 917 918 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 919 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 920 921 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 922 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 923 924 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 925 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 926 927 #define MLX5_CAP_ESW(mdev, cap) \ 928 MLX5_GET(e_switch_cap, \ 929 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 930 931 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 932 MLX5_GET(e_switch_cap, \ 933 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 934 935 #define MLX5_CAP_ODP(mdev, cap)\ 936 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 937 938 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 939 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 940 941 #define MLX5_CAP_SNAPSHOT(mdev, cap) \ 942 MLX5_GET(snapshot_cap, \ 943 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 944 945 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 946 MLX5_GET(snapshot_cap, \ 947 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 948 949 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 950 MLX5_GET(per_protocol_networking_offload_caps,\ 951 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 952 953 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 954 MLX5_GET(per_protocol_networking_offload_caps,\ 955 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 956 957 #define MLX5_CAP_DEBUG(mdev, cap) \ 958 MLX5_GET(debug_cap, \ 959 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 960 961 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 962 MLX5_GET(debug_cap, \ 963 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 964 965 #define MLX5_CAP_QOS(mdev, cap) \ 966 MLX5_GET(qos_cap,\ 967 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 968 969 #define MLX5_CAP_QOS_MAX(mdev, cap) \ 970 MLX5_GET(qos_cap,\ 971 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 972 973 enum { 974 MLX5_CMD_STAT_OK = 0x0, 975 MLX5_CMD_STAT_INT_ERR = 0x1, 976 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 977 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 978 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 979 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 980 MLX5_CMD_STAT_RES_BUSY = 0x6, 981 MLX5_CMD_STAT_LIM_ERR = 0x8, 982 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 983 MLX5_CMD_STAT_IX_ERR = 0xa, 984 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 985 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 986 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 987 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 988 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 989 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 990 }; 991 992 enum { 993 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 994 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 995 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 996 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 997 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 998 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 999 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1000 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1001 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1002 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1003 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1004 }; 1005 1006 enum { 1007 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1008 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1009 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1010 }; 1011 1012 enum { 1013 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1014 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1015 }; 1016 1017 enum { 1018 NUM_DRIVER_UARS = 4, 1019 NUM_LOW_LAT_UUARS = 4, 1020 }; 1021 1022 enum { 1023 MLX5_CAP_PORT_TYPE_IB = 0x0, 1024 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1025 }; 1026 1027 enum { 1028 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1029 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1030 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1031 }; 1032 1033 enum { 1034 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1035 }; 1036 1037 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1038 { 1039 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1040 return 0; 1041 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1042 } 1043 1044 struct mlx5_ifc_mcia_reg_bits { 1045 u8 l[0x1]; 1046 u8 reserved_0[0x7]; 1047 u8 module[0x8]; 1048 u8 reserved_1[0x8]; 1049 u8 status[0x8]; 1050 1051 u8 i2c_device_address[0x8]; 1052 u8 page_number[0x8]; 1053 u8 device_address[0x10]; 1054 1055 u8 reserved_2[0x10]; 1056 u8 size[0x10]; 1057 1058 u8 reserved_3[0x20]; 1059 1060 u8 dword_0[0x20]; 1061 u8 dword_1[0x20]; 1062 u8 dword_2[0x20]; 1063 u8 dword_3[0x20]; 1064 u8 dword_4[0x20]; 1065 u8 dword_5[0x20]; 1066 u8 dword_6[0x20]; 1067 u8 dword_7[0x20]; 1068 u8 dword_8[0x20]; 1069 u8 dword_9[0x20]; 1070 u8 dword_10[0x20]; 1071 u8 dword_11[0x20]; 1072 }; 1073 1074 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1075 1076 struct mlx5_mini_cqe8 { 1077 union { 1078 __be32 rx_hash_result; 1079 __be16 checksum; 1080 __be16 rsvd; 1081 struct { 1082 __be16 wqe_counter; 1083 u8 s_wqe_opcode; 1084 u8 reserved; 1085 } s_wqe_info; 1086 }; 1087 __be32 byte_cnt; 1088 }; 1089 1090 enum { 1091 MLX5_NO_INLINE_DATA, 1092 MLX5_INLINE_DATA32_SEG, 1093 MLX5_INLINE_DATA64_SEG, 1094 MLX5_COMPRESSED, 1095 }; 1096 1097 enum mlx5_exp_cqe_zip_recv_type { 1098 MLX5_CQE_FORMAT_HASH, 1099 MLX5_CQE_FORMAT_CSUM, 1100 }; 1101 1102 #define MLX5E_CQE_FORMAT_MASK 0xc 1103 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1104 { 1105 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1106 } 1107 1108 enum { 1109 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1110 }; 1111 1112 /* 8 regular priorities + 1 for multicast */ 1113 #define MLX5_NUM_BYPASS_FTS 9 1114 1115 #endif /* MLX5_DEVICE_H */ 1116