xref: /freebsd/sys/dev/mlx5/device.h (revision f8f5b459d21ec9dd1ca5d9de319d8b440fef84a8)
1dc7e38acSHans Petter Selasky /*-
204f1690bSHans Petter Selasky  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3dc7e38acSHans Petter Selasky  *
4dc7e38acSHans Petter Selasky  * Redistribution and use in source and binary forms, with or without
5dc7e38acSHans Petter Selasky  * modification, are permitted provided that the following conditions
6dc7e38acSHans Petter Selasky  * are met:
7dc7e38acSHans Petter Selasky  * 1. Redistributions of source code must retain the above copyright
8dc7e38acSHans Petter Selasky  *    notice, this list of conditions and the following disclaimer.
9dc7e38acSHans Petter Selasky  * 2. Redistributions in binary form must reproduce the above copyright
10dc7e38acSHans Petter Selasky  *    notice, this list of conditions and the following disclaimer in the
11dc7e38acSHans Petter Selasky  *    documentation and/or other materials provided with the distribution.
12dc7e38acSHans Petter Selasky  *
13dc7e38acSHans Petter Selasky  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14dc7e38acSHans Petter Selasky  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15dc7e38acSHans Petter Selasky  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16dc7e38acSHans Petter Selasky  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17dc7e38acSHans Petter Selasky  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18dc7e38acSHans Petter Selasky  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19dc7e38acSHans Petter Selasky  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20dc7e38acSHans Petter Selasky  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21dc7e38acSHans Petter Selasky  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22dc7e38acSHans Petter Selasky  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23dc7e38acSHans Petter Selasky  * SUCH DAMAGE.
24dc7e38acSHans Petter Selasky  *
25dc7e38acSHans Petter Selasky  * $FreeBSD$
26dc7e38acSHans Petter Selasky  */
27dc7e38acSHans Petter Selasky 
28dc7e38acSHans Petter Selasky #ifndef MLX5_DEVICE_H
29dc7e38acSHans Petter Selasky #define MLX5_DEVICE_H
30dc7e38acSHans Petter Selasky 
31dc7e38acSHans Petter Selasky #include <linux/types.h>
32dc7e38acSHans Petter Selasky #include <rdma/ib_verbs.h>
33dc7e38acSHans Petter Selasky #include <dev/mlx5/mlx5_ifc.h>
34dc7e38acSHans Petter Selasky 
35dc7e38acSHans Petter Selasky #define	FW_INIT_TIMEOUT_MILI		2000
36dc7e38acSHans Petter Selasky #define	FW_INIT_WAIT_MS			2
3759efbf79SHans Petter Selasky #define	FW_PRE_INIT_TIMEOUT_MILI	120000
3859efbf79SHans Petter Selasky #define	FW_INIT_WARN_MESSAGE_INTERVAL	20000
39dc7e38acSHans Petter Selasky 
40dc7e38acSHans Petter Selasky #if defined(__LITTLE_ENDIAN)
41dc7e38acSHans Petter Selasky #define MLX5_SET_HOST_ENDIANNESS	0
42dc7e38acSHans Petter Selasky #elif defined(__BIG_ENDIAN)
43dc7e38acSHans Petter Selasky #define MLX5_SET_HOST_ENDIANNESS	0x80
44dc7e38acSHans Petter Selasky #else
45dc7e38acSHans Petter Selasky #error Host endianness not defined
46dc7e38acSHans Petter Selasky #endif
47dc7e38acSHans Petter Selasky 
48dc7e38acSHans Petter Selasky /* helper macros */
49dc7e38acSHans Petter Selasky #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50dc7e38acSHans Petter Selasky #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51dc7e38acSHans Petter Selasky #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
52ed0cee0bSHans Petter Selasky #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53dc7e38acSHans Petter Selasky #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54dc7e38acSHans Petter Selasky #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55ed0cee0bSHans Petter Selasky #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56dc7e38acSHans Petter Selasky #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57dc7e38acSHans Petter Selasky #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58dc7e38acSHans Petter Selasky #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59ed0cee0bSHans Petter Selasky #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60ed0cee0bSHans Petter Selasky #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61dc7e38acSHans Petter Selasky #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62dc7e38acSHans Petter Selasky 
63dc7e38acSHans Petter Selasky #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64dc7e38acSHans Petter Selasky #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65dc7e38acSHans Petter Selasky #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66cb4e4a6eSHans Petter Selasky #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67dc7e38acSHans Petter Selasky #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68dc7e38acSHans Petter Selasky #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69dc7e38acSHans Petter Selasky #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70dc7e38acSHans Petter Selasky #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71dc7e38acSHans Petter Selasky 
72dc7e38acSHans Petter Selasky /* insert a value to a struct */
73dc7e38acSHans Petter Selasky #define MLX5_SET(typ, p, fld, v) do { \
74dc7e38acSHans Petter Selasky 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
75dc7e38acSHans Petter Selasky 	BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
76dc7e38acSHans Petter Selasky 	*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77dc7e38acSHans Petter Selasky 	cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78dc7e38acSHans Petter Selasky 		     (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
79dc7e38acSHans Petter Selasky 		     << __mlx5_dw_bit_off(typ, fld))); \
80dc7e38acSHans Petter Selasky } while (0)
81dc7e38acSHans Petter Selasky 
82dc7e38acSHans Petter Selasky #define MLX5_SET_TO_ONES(typ, p, fld) do { \
83dc7e38acSHans Petter Selasky 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
84dc7e38acSHans Petter Selasky 	BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
85dc7e38acSHans Petter Selasky 	*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
86dc7e38acSHans Petter Selasky 	cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
87dc7e38acSHans Petter Selasky 		     (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
88dc7e38acSHans Petter Selasky 		     << __mlx5_dw_bit_off(typ, fld))); \
89dc7e38acSHans Petter Selasky } while (0)
90dc7e38acSHans Petter Selasky 
91dc7e38acSHans Petter Selasky #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
92dc7e38acSHans Petter Selasky __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
93dc7e38acSHans Petter Selasky __mlx5_mask(typ, fld))
94dc7e38acSHans Petter Selasky 
95dc7e38acSHans Petter Selasky #define MLX5_GET_PR(typ, p, fld) ({ \
96dc7e38acSHans Petter Selasky 	u32 ___t = MLX5_GET(typ, p, fld); \
97dc7e38acSHans Petter Selasky 	pr_debug(#fld " = 0x%x\n", ___t); \
98dc7e38acSHans Petter Selasky 	___t; \
99dc7e38acSHans Petter Selasky })
100dc7e38acSHans Petter Selasky 
101788333d9SHans Petter Selasky #define __MLX5_SET64(typ, p, fld, v) do { \
102dc7e38acSHans Petter Selasky 	BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
103dc7e38acSHans Petter Selasky 	*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
104dc7e38acSHans Petter Selasky } while (0)
105dc7e38acSHans Petter Selasky 
106788333d9SHans Petter Selasky #define MLX5_SET64(typ, p, fld, v) do { \
107788333d9SHans Petter Selasky 	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108788333d9SHans Petter Selasky 	__MLX5_SET64(typ, p, fld, v); \
109788333d9SHans Petter Selasky } while (0)
110788333d9SHans Petter Selasky 
111788333d9SHans Petter Selasky #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
112788333d9SHans Petter Selasky 	BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113788333d9SHans Petter Selasky 	__MLX5_SET64(typ, p, fld[idx], v); \
114788333d9SHans Petter Selasky } while (0)
115788333d9SHans Petter Selasky 
116dc7e38acSHans Petter Selasky #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
117dc7e38acSHans Petter Selasky 
118ed0cee0bSHans Petter Selasky #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
119ed0cee0bSHans Petter Selasky __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
120ed0cee0bSHans Petter Selasky __mlx5_mask16(typ, fld))
121ed0cee0bSHans Petter Selasky 
122ed0cee0bSHans Petter Selasky #define MLX5_SET16(typ, p, fld, v) do { \
123ed0cee0bSHans Petter Selasky 	u16 _v = v; \
124ed0cee0bSHans Petter Selasky 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16);             \
125ed0cee0bSHans Petter Selasky 	*((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
126ed0cee0bSHans Petter Selasky 	cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
127ed0cee0bSHans Petter Selasky 		     (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
128ed0cee0bSHans Petter Selasky 		     << __mlx5_16_bit_off(typ, fld))); \
129ed0cee0bSHans Petter Selasky } while (0)
130ed0cee0bSHans Petter Selasky 
1314b109912SHans Petter Selasky #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
1324b109912SHans Petter Selasky 	__mlx5_64_off(typ, fld)))
1334b109912SHans Petter Selasky 
1344b109912SHans Petter Selasky #define MLX5_GET_BE(type_t, typ, p, fld) ({				  \
1354b109912SHans Petter Selasky 		type_t tmp;						  \
1364b109912SHans Petter Selasky 		switch (sizeof(tmp)) {					  \
1374b109912SHans Petter Selasky 		case sizeof(u8):					  \
1384b109912SHans Petter Selasky 			tmp = (__force type_t)MLX5_GET(typ, p, fld);	  \
1394b109912SHans Petter Selasky 			break;						  \
1404b109912SHans Petter Selasky 		case sizeof(u16):					  \
1414b109912SHans Petter Selasky 			tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
1424b109912SHans Petter Selasky 			break;						  \
1434b109912SHans Petter Selasky 		case sizeof(u32):					  \
1444b109912SHans Petter Selasky 			tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
1454b109912SHans Petter Selasky 			break;						  \
1464b109912SHans Petter Selasky 		case sizeof(u64):					  \
1474b109912SHans Petter Selasky 			tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
1484b109912SHans Petter Selasky 			break;						  \
1494b109912SHans Petter Selasky 			}						  \
1504b109912SHans Petter Selasky 		tmp;							  \
1514b109912SHans Petter Selasky 		})
1524b109912SHans Petter Selasky 
1534b109912SHans Petter Selasky #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1544b109912SHans Petter Selasky #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1554b109912SHans Petter Selasky #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1564b109912SHans Petter Selasky #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1574b109912SHans Petter Selasky                                     MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1584b109912SHans Petter Selasky                                     MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1594b109912SHans Petter Selasky 
1604b95c665SHans Petter Selasky /* insert a value to a struct */
1614b95c665SHans Petter Selasky #define MLX5_VSC_SET(typ, p, fld, v) do { \
1624b95c665SHans Petter Selasky 	BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);	       \
1634b95c665SHans Petter Selasky 	BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
1644b95c665SHans Petter Selasky 	*((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
1654b95c665SHans Petter Selasky 	cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
1664b95c665SHans Petter Selasky 		     (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
1674b95c665SHans Petter Selasky 		     << __mlx5_dw_bit_off(typ, fld))); \
1684b95c665SHans Petter Selasky } while (0)
1694b95c665SHans Petter Selasky 
1704b95c665SHans Petter Selasky #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
1714b95c665SHans Petter Selasky __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
1724b95c665SHans Petter Selasky __mlx5_mask(typ, fld))
1734b95c665SHans Petter Selasky 
1744b95c665SHans Petter Selasky #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
1754b95c665SHans Petter Selasky 	u32 ___t = MLX5_VSC_GET(typ, p, fld); \
1764b95c665SHans Petter Selasky 	pr_debug(#fld " = 0x%x\n", ___t); \
1774b95c665SHans Petter Selasky 	___t; \
1784b95c665SHans Petter Selasky })
1794b95c665SHans Petter Selasky 
180dc7e38acSHans Petter Selasky enum {
181dc7e38acSHans Petter Selasky 	MLX5_MAX_COMMANDS		= 32,
182dc7e38acSHans Petter Selasky 	MLX5_CMD_DATA_BLOCK_SIZE	= 512,
1831c807f67SHans Petter Selasky 	MLX5_CMD_MBOX_SIZE		= 1024,
184dc7e38acSHans Petter Selasky 	MLX5_PCI_CMD_XPORT		= 7,
185dc7e38acSHans Petter Selasky 	MLX5_MKEY_BSF_OCTO_SIZE		= 4,
186dc7e38acSHans Petter Selasky 	MLX5_MAX_PSVS			= 4,
187dc7e38acSHans Petter Selasky };
188dc7e38acSHans Petter Selasky 
189dc7e38acSHans Petter Selasky enum {
190dc7e38acSHans Petter Selasky 	MLX5_EXTENDED_UD_AV		= 0x80000000,
191dc7e38acSHans Petter Selasky };
192dc7e38acSHans Petter Selasky 
193dc7e38acSHans Petter Selasky enum {
194cb4e4a6eSHans Petter Selasky 	MLX5_CQ_FLAGS_OI	= 2,
195cb4e4a6eSHans Petter Selasky };
196cb4e4a6eSHans Petter Selasky 
197cb4e4a6eSHans Petter Selasky enum {
198dc7e38acSHans Petter Selasky 	MLX5_STAT_RATE_OFFSET	= 5,
199dc7e38acSHans Petter Selasky };
200dc7e38acSHans Petter Selasky 
201dc7e38acSHans Petter Selasky enum {
202dc7e38acSHans Petter Selasky 	MLX5_INLINE_SEG = 0x80000000,
203dc7e38acSHans Petter Selasky };
204dc7e38acSHans Petter Selasky 
205dc7e38acSHans Petter Selasky enum {
206dc7e38acSHans Petter Selasky 	MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
207dc7e38acSHans Petter Selasky };
208dc7e38acSHans Petter Selasky 
209dc7e38acSHans Petter Selasky enum {
210dc7e38acSHans Petter Selasky 	MLX5_MIN_PKEY_TABLE_SIZE = 128,
211dc7e38acSHans Petter Selasky 	MLX5_MAX_LOG_PKEY_TABLE  = 5,
212dc7e38acSHans Petter Selasky };
213dc7e38acSHans Petter Selasky 
214dc7e38acSHans Petter Selasky enum {
21502ca39cfSEitan Adler 	MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
216cb4e4a6eSHans Petter Selasky };
217cb4e4a6eSHans Petter Selasky 
218cb4e4a6eSHans Petter Selasky enum {
219dc7e38acSHans Petter Selasky 	MLX5_PERM_LOCAL_READ	= 1 << 2,
220dc7e38acSHans Petter Selasky 	MLX5_PERM_LOCAL_WRITE	= 1 << 3,
221dc7e38acSHans Petter Selasky 	MLX5_PERM_REMOTE_READ	= 1 << 4,
222dc7e38acSHans Petter Selasky 	MLX5_PERM_REMOTE_WRITE	= 1 << 5,
223dc7e38acSHans Petter Selasky 	MLX5_PERM_ATOMIC	= 1 << 6,
224dc7e38acSHans Petter Selasky 	MLX5_PERM_UMR_EN	= 1 << 7,
225dc7e38acSHans Petter Selasky };
226dc7e38acSHans Petter Selasky 
227dc7e38acSHans Petter Selasky enum {
228dc7e38acSHans Petter Selasky 	MLX5_PCIE_CTRL_SMALL_FENCE	= 1 << 0,
229dc7e38acSHans Petter Selasky 	MLX5_PCIE_CTRL_RELAXED_ORDERING	= 1 << 2,
230dc7e38acSHans Petter Selasky 	MLX5_PCIE_CTRL_NO_SNOOP		= 1 << 3,
231dc7e38acSHans Petter Selasky 	MLX5_PCIE_CTRL_TLP_PROCE_EN	= 1 << 6,
232dc7e38acSHans Petter Selasky 	MLX5_PCIE_CTRL_TPH_MASK		= 3 << 4,
233dc7e38acSHans Petter Selasky };
234dc7e38acSHans Petter Selasky 
235dc7e38acSHans Petter Selasky enum {
236dc7e38acSHans Petter Selasky 	MLX5_MKEY_REMOTE_INVAL	= 1 << 24,
237dc7e38acSHans Petter Selasky 	MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
238dc7e38acSHans Petter Selasky 	MLX5_MKEY_BSF_EN	= 1 << 30,
23902ca39cfSEitan Adler 	MLX5_MKEY_LEN64		= 1U << 31,
240dc7e38acSHans Petter Selasky };
241dc7e38acSHans Petter Selasky 
242dc7e38acSHans Petter Selasky enum {
243dc7e38acSHans Petter Selasky 	MLX5_EN_RD	= (u64)1,
244dc7e38acSHans Petter Selasky 	MLX5_EN_WR	= (u64)2
245dc7e38acSHans Petter Selasky };
246dc7e38acSHans Petter Selasky 
247dc7e38acSHans Petter Selasky enum {
248*f8f5b459SHans Petter Selasky 	MLX5_ADAPTER_PAGE_SHIFT		= 12,
249*f8f5b459SHans Petter Selasky 	MLX5_ADAPTER_PAGE_SIZE		= 1 << MLX5_ADAPTER_PAGE_SHIFT,
250*f8f5b459SHans Petter Selasky };
251*f8f5b459SHans Petter Selasky 
252*f8f5b459SHans Petter Selasky enum {
253*f8f5b459SHans Petter Selasky 	MLX5_BFREGS_PER_UAR		= 4,
254*f8f5b459SHans Petter Selasky 	MLX5_MAX_UARS			= 1 << 8,
255*f8f5b459SHans Petter Selasky 	MLX5_NON_FP_BFREGS_PER_UAR	= 2,
256*f8f5b459SHans Petter Selasky 	MLX5_FP_BFREGS_PER_UAR		= MLX5_BFREGS_PER_UAR -
257*f8f5b459SHans Petter Selasky 					  MLX5_NON_FP_BFREGS_PER_UAR,
258*f8f5b459SHans Petter Selasky 	MLX5_MAX_BFREGS			= MLX5_MAX_UARS *
259*f8f5b459SHans Petter Selasky 					  MLX5_NON_FP_BFREGS_PER_UAR,
260*f8f5b459SHans Petter Selasky 	MLX5_UARS_IN_PAGE		= PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
261*f8f5b459SHans Petter Selasky 	MLX5_NON_FP_BFREGS_IN_PAGE	= MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
262*f8f5b459SHans Petter Selasky 	MLX5_MIN_DYN_BFREGS		= 512,
263*f8f5b459SHans Petter Selasky 	MLX5_MAX_DYN_BFREGS		= 1024,
264dc7e38acSHans Petter Selasky };
265dc7e38acSHans Petter Selasky 
266dc7e38acSHans Petter Selasky enum {
267dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_LEN		= 1ull << 0,
268dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_PAGE_SIZE	= 1ull << 1,
269dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_START_ADDR	= 1ull << 6,
270dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_PD		= 1ull << 7,
271dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_EN_RINVAL	= 1ull << 8,
272dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_EN_SIGERR	= 1ull << 9,
273dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_BSF_EN		= 1ull << 12,
274dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_KEY		= 1ull << 13,
275dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_QPN		= 1ull << 14,
276dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_LR		= 1ull << 17,
277dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_LW		= 1ull << 18,
278dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_RR		= 1ull << 19,
279dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_RW		= 1ull << 20,
280dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_A		= 1ull << 21,
281dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_SMALL_FENCE	= 1ull << 23,
282dc7e38acSHans Petter Selasky 	MLX5_MKEY_MASK_FREE		= 1ull << 29,
283dc7e38acSHans Petter Selasky };
284dc7e38acSHans Petter Selasky 
285dc7e38acSHans Petter Selasky enum {
286cb4e4a6eSHans Petter Selasky 	MLX5_UMR_TRANSLATION_OFFSET_EN	= (1 << 4),
287cb4e4a6eSHans Petter Selasky 
288cb4e4a6eSHans Petter Selasky 	MLX5_UMR_CHECK_NOT_FREE		= (1 << 5),
289cb4e4a6eSHans Petter Selasky 	MLX5_UMR_CHECK_FREE		= (2 << 5),
290cb4e4a6eSHans Petter Selasky 
291cb4e4a6eSHans Petter Selasky 	MLX5_UMR_INLINE			= (1 << 7),
292cb4e4a6eSHans Petter Selasky };
293cb4e4a6eSHans Petter Selasky 
294cb4e4a6eSHans Petter Selasky #define MLX5_UMR_MTT_ALIGNMENT 0x40
295cb4e4a6eSHans Petter Selasky #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
296cb4e4a6eSHans Petter Selasky #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
297cb4e4a6eSHans Petter Selasky 
298cb4e4a6eSHans Petter Selasky enum {
299cb4e4a6eSHans Petter Selasky 	MLX5_EVENT_QUEUE_TYPE_QP = 0,
300cb4e4a6eSHans Petter Selasky 	MLX5_EVENT_QUEUE_TYPE_RQ = 1,
301cb4e4a6eSHans Petter Selasky 	MLX5_EVENT_QUEUE_TYPE_SQ = 2,
302cb4e4a6eSHans Petter Selasky };
303cb4e4a6eSHans Petter Selasky 
304cb4e4a6eSHans Petter Selasky enum {
305dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_DOWN		= 1,
306dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_ACTIVE		= 4,
307dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED	= 5,
308dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_LID		= 6,
309dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_PKEY		= 7,
310dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_GUID		= 8,
311dc7e38acSHans Petter Selasky 	MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG	= 9,
312dc7e38acSHans Petter Selasky };
313dc7e38acSHans Petter Selasky 
314dc7e38acSHans Petter Selasky enum {
315cb4e4a6eSHans Petter Selasky 	MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
316cb4e4a6eSHans Petter Selasky 	MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
317cb4e4a6eSHans Petter Selasky 	MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
318cb4e4a6eSHans Petter Selasky 	MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
319cb4e4a6eSHans Petter Selasky 	MLX5_MAX_INLINE_RECEIVE_SIZE		= 64
320cb4e4a6eSHans Petter Selasky };
321cb4e4a6eSHans Petter Selasky 
322cb4e4a6eSHans Petter Selasky enum {
323dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_XRC		= 1LL <<  3,
324dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1LL <<  8,
325dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1LL <<  9,
326dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_APM		= 1LL << 17,
327dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD	= 1LL << 21,
328dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_BLOCK_MCAST	= 1LL << 23,
329dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_CQ_MODER	= 1LL << 29,
330dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_RESIZE_CQ	= 1LL << 30,
331cb4e4a6eSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_ATOMIC	= 1LL << 33,
332dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_ROCE          = 1LL << 34,
333dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_DCT		= 1LL << 37,
334dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_SIG_HAND_OVER	= 1LL << 40,
335dc7e38acSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_CMDIF_CSUM	= 3LL << 46,
336cb4e4a6eSHans Petter Selasky 	MLX5_DEV_CAP_FLAG_DRAIN_SIGERR	= 1LL << 48,
337dc7e38acSHans Petter Selasky };
338dc7e38acSHans Petter Selasky 
339dc7e38acSHans Petter Selasky enum {
340dc7e38acSHans Petter Selasky 	MLX5_ROCE_VERSION_1		= 0,
341dc7e38acSHans Petter Selasky 	MLX5_ROCE_VERSION_1_5		= 1,
342dc7e38acSHans Petter Selasky 	MLX5_ROCE_VERSION_2		= 2,
343dc7e38acSHans Petter Selasky };
344dc7e38acSHans Petter Selasky 
345dc7e38acSHans Petter Selasky enum {
346dc7e38acSHans Petter Selasky 	MLX5_ROCE_VERSION_1_CAP		= 1 << MLX5_ROCE_VERSION_1,
347dc7e38acSHans Petter Selasky 	MLX5_ROCE_VERSION_1_5_CAP	= 1 << MLX5_ROCE_VERSION_1_5,
348dc7e38acSHans Petter Selasky 	MLX5_ROCE_VERSION_2_CAP		= 1 << MLX5_ROCE_VERSION_2,
349dc7e38acSHans Petter Selasky };
350dc7e38acSHans Petter Selasky 
351dc7e38acSHans Petter Selasky enum {
352dc7e38acSHans Petter Selasky 	MLX5_ROCE_L3_TYPE_IPV4		= 0,
353dc7e38acSHans Petter Selasky 	MLX5_ROCE_L3_TYPE_IPV6		= 1,
354dc7e38acSHans Petter Selasky };
355dc7e38acSHans Petter Selasky 
356dc7e38acSHans Petter Selasky enum {
357dc7e38acSHans Petter Selasky 	MLX5_ROCE_L3_TYPE_IPV4_CAP	= 1 << 1,
358dc7e38acSHans Petter Selasky 	MLX5_ROCE_L3_TYPE_IPV6_CAP	= 1 << 2,
359dc7e38acSHans Petter Selasky };
360dc7e38acSHans Petter Selasky 
361dc7e38acSHans Petter Selasky enum {
362dc7e38acSHans Petter Selasky 	MLX5_OPCODE_NOP			= 0x00,
363dc7e38acSHans Petter Selasky 	MLX5_OPCODE_SEND_INVAL		= 0x01,
364dc7e38acSHans Petter Selasky 	MLX5_OPCODE_RDMA_WRITE		= 0x08,
365dc7e38acSHans Petter Selasky 	MLX5_OPCODE_RDMA_WRITE_IMM	= 0x09,
366dc7e38acSHans Petter Selasky 	MLX5_OPCODE_SEND		= 0x0a,
367dc7e38acSHans Petter Selasky 	MLX5_OPCODE_SEND_IMM		= 0x0b,
368dc7e38acSHans Petter Selasky 	MLX5_OPCODE_LSO			= 0x0e,
369dc7e38acSHans Petter Selasky 	MLX5_OPCODE_RDMA_READ		= 0x10,
370dc7e38acSHans Petter Selasky 	MLX5_OPCODE_ATOMIC_CS		= 0x11,
371dc7e38acSHans Petter Selasky 	MLX5_OPCODE_ATOMIC_FA		= 0x12,
372dc7e38acSHans Petter Selasky 	MLX5_OPCODE_ATOMIC_MASKED_CS	= 0x14,
373dc7e38acSHans Petter Selasky 	MLX5_OPCODE_ATOMIC_MASKED_FA	= 0x15,
374dc7e38acSHans Petter Selasky 	MLX5_OPCODE_BIND_MW		= 0x18,
375dc7e38acSHans Petter Selasky 	MLX5_OPCODE_CONFIG_CMD		= 0x1f,
3767272f9cdSHans Petter Selasky 	MLX5_OPCODE_DUMP		= 0x23,
377dc7e38acSHans Petter Selasky 
378dc7e38acSHans Petter Selasky 	MLX5_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
379dc7e38acSHans Petter Selasky 	MLX5_RECV_OPCODE_SEND		= 0x01,
380dc7e38acSHans Petter Selasky 	MLX5_RECV_OPCODE_SEND_IMM	= 0x02,
381dc7e38acSHans Petter Selasky 	MLX5_RECV_OPCODE_SEND_INVAL	= 0x03,
382dc7e38acSHans Petter Selasky 
383dc7e38acSHans Petter Selasky 	MLX5_CQE_OPCODE_ERROR		= 0x1e,
384dc7e38acSHans Petter Selasky 	MLX5_CQE_OPCODE_RESIZE		= 0x16,
385dc7e38acSHans Petter Selasky 
386dc7e38acSHans Petter Selasky 	MLX5_OPCODE_SET_PSV		= 0x20,
387dc7e38acSHans Petter Selasky 	MLX5_OPCODE_GET_PSV		= 0x21,
388dc7e38acSHans Petter Selasky 	MLX5_OPCODE_CHECK_PSV		= 0x22,
389dc7e38acSHans Petter Selasky 	MLX5_OPCODE_RGET_PSV		= 0x26,
390dc7e38acSHans Petter Selasky 	MLX5_OPCODE_RCHECK_PSV		= 0x27,
391dc7e38acSHans Petter Selasky 
392dc7e38acSHans Petter Selasky 	MLX5_OPCODE_UMR			= 0x25,
393dc7e38acSHans Petter Selasky 
394cb4e4a6eSHans Petter Selasky 	MLX5_OPCODE_SIGNATURE_CANCELED	= (1 << 15),
395dc7e38acSHans Petter Selasky };
396dc7e38acSHans Petter Selasky 
397dc7e38acSHans Petter Selasky enum {
39804f1690bSHans Petter Selasky 	MLX5_OPCODE_MOD_UMR_UMR = 0x0,
39904f1690bSHans Petter Selasky 	MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1,
40004f1690bSHans Petter Selasky 	MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2,
40104f1690bSHans Petter Selasky };
40204f1690bSHans Petter Selasky 
40304f1690bSHans Petter Selasky enum {
40404f1690bSHans Petter Selasky 	MLX5_OPCODE_MOD_PSV_PSV = 0x0,
40504f1690bSHans Petter Selasky 	MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1,
40604f1690bSHans Petter Selasky 	MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2,
40704f1690bSHans Petter Selasky };
40804f1690bSHans Petter Selasky 
40904f1690bSHans Petter Selasky enum {
410dc7e38acSHans Petter Selasky 	MLX5_SET_PORT_RESET_QKEY	= 0,
411dc7e38acSHans Petter Selasky 	MLX5_SET_PORT_GUID0		= 16,
412dc7e38acSHans Petter Selasky 	MLX5_SET_PORT_NODE_GUID		= 17,
413dc7e38acSHans Petter Selasky 	MLX5_SET_PORT_SYS_GUID		= 18,
414dc7e38acSHans Petter Selasky 	MLX5_SET_PORT_GID_TABLE		= 19,
415dc7e38acSHans Petter Selasky 	MLX5_SET_PORT_PKEY_TABLE	= 20,
416dc7e38acSHans Petter Selasky };
417dc7e38acSHans Petter Selasky 
418dc7e38acSHans Petter Selasky enum {
419dc7e38acSHans Petter Selasky 	MLX5_MAX_PAGE_SHIFT		= 31
420dc7e38acSHans Petter Selasky };
421dc7e38acSHans Petter Selasky 
422dc7e38acSHans Petter Selasky enum {
423dc7e38acSHans Petter Selasky 	MLX5_CAP_OFF_CMDIF_CSUM		= 46,
424dc7e38acSHans Petter Selasky };
425dc7e38acSHans Petter Selasky 
4264b109912SHans Petter Selasky enum {
4274b109912SHans Petter Selasky 	/*
4284b109912SHans Petter Selasky 	 * Max wqe size for rdma read is 512 bytes, so this
4294b109912SHans Petter Selasky 	 * limits our max_sge_rd as the wqe needs to fit:
4304b109912SHans Petter Selasky 	 * - ctrl segment (16 bytes)
4314b109912SHans Petter Selasky 	 * - rdma segment (16 bytes)
4324b109912SHans Petter Selasky 	 * - scatter elements (16 bytes each)
4334b109912SHans Petter Selasky 	 */
4344b109912SHans Petter Selasky 	MLX5_MAX_SGE_RD	= (512 - 16 - 16) / 16
4354b109912SHans Petter Selasky };
4364b109912SHans Petter Selasky 
437dc7e38acSHans Petter Selasky struct mlx5_cmd_layout {
438dc7e38acSHans Petter Selasky 	u8		type;
439dc7e38acSHans Petter Selasky 	u8		rsvd0[3];
440dc7e38acSHans Petter Selasky 	__be32		inlen;
441dc7e38acSHans Petter Selasky 	__be64		in_ptr;
442dc7e38acSHans Petter Selasky 	__be32		in[4];
443dc7e38acSHans Petter Selasky 	__be32		out[4];
444dc7e38acSHans Petter Selasky 	__be64		out_ptr;
445dc7e38acSHans Petter Selasky 	__be32		outlen;
446dc7e38acSHans Petter Selasky 	u8		token;
447dc7e38acSHans Petter Selasky 	u8		sig;
448dc7e38acSHans Petter Selasky 	u8		rsvd1;
449dc7e38acSHans Petter Selasky 	u8		status_own;
450dc7e38acSHans Petter Selasky };
451dc7e38acSHans Petter Selasky 
452fe242ba7SHans Petter Selasky enum mlx5_fatal_assert_bit_offsets {
453fe242ba7SHans Petter Selasky 	MLX5_RFR_OFFSET = 31,
454fe242ba7SHans Petter Selasky };
455fe242ba7SHans Petter Selasky 
456dc7e38acSHans Petter Selasky struct mlx5_health_buffer {
457dc7e38acSHans Petter Selasky 	__be32		assert_var[5];
458dc7e38acSHans Petter Selasky 	__be32		rsvd0[3];
459dc7e38acSHans Petter Selasky 	__be32		assert_exit_ptr;
460dc7e38acSHans Petter Selasky 	__be32		assert_callra;
461dc7e38acSHans Petter Selasky 	__be32		rsvd1[2];
462dc7e38acSHans Petter Selasky 	__be32		fw_ver;
463dc7e38acSHans Petter Selasky 	__be32		hw_id;
464fe242ba7SHans Petter Selasky 	__be32		rfr;
465dc7e38acSHans Petter Selasky 	u8		irisc_index;
466dc7e38acSHans Petter Selasky 	u8		synd;
467a2485fe5SHans Petter Selasky 	__be16		ext_synd;
468dc7e38acSHans Petter Selasky };
469dc7e38acSHans Petter Selasky 
470fe242ba7SHans Petter Selasky enum mlx5_initializing_bit_offsets {
471fe242ba7SHans Petter Selasky 	MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
472fe242ba7SHans Petter Selasky };
473fe242ba7SHans Petter Selasky 
474fe242ba7SHans Petter Selasky enum mlx5_cmd_addr_l_sz_offset {
475fe242ba7SHans Petter Selasky 	MLX5_NIC_IFC_OFFSET = 8,
476fe242ba7SHans Petter Selasky };
477fe242ba7SHans Petter Selasky 
478dc7e38acSHans Petter Selasky struct mlx5_init_seg {
479dc7e38acSHans Petter Selasky 	__be32			fw_rev;
480dc7e38acSHans Petter Selasky 	__be32			cmdif_rev_fw_sub;
481dc7e38acSHans Petter Selasky 	__be32			rsvd0[2];
482dc7e38acSHans Petter Selasky 	__be32			cmdq_addr_h;
483dc7e38acSHans Petter Selasky 	__be32			cmdq_addr_l_sz;
484dc7e38acSHans Petter Selasky 	__be32			cmd_dbell;
485dc7e38acSHans Petter Selasky 	__be32			rsvd1[120];
486dc7e38acSHans Petter Selasky 	__be32			initializing;
487dc7e38acSHans Petter Selasky 	struct mlx5_health_buffer  health;
488cb4e4a6eSHans Petter Selasky 	__be32			rsvd2[880];
489cb4e4a6eSHans Petter Selasky 	__be32			internal_timer_h;
490cb4e4a6eSHans Petter Selasky 	__be32			internal_timer_l;
491cb4e4a6eSHans Petter Selasky 	__be32			rsvd3[2];
492dc7e38acSHans Petter Selasky 	__be32			health_counter;
493cb4e4a6eSHans Petter Selasky 	__be32			rsvd4[1019];
494dc7e38acSHans Petter Selasky 	__be64			ieee1588_clk;
495dc7e38acSHans Petter Selasky 	__be32			ieee1588_clk_type;
496dc7e38acSHans Petter Selasky 	__be32			clr_intx;
497dc7e38acSHans Petter Selasky };
498dc7e38acSHans Petter Selasky 
499dc7e38acSHans Petter Selasky struct mlx5_eqe_comp {
500dc7e38acSHans Petter Selasky 	__be32	reserved[6];
501dc7e38acSHans Petter Selasky 	__be32	cqn;
502dc7e38acSHans Petter Selasky };
503dc7e38acSHans Petter Selasky 
504dc7e38acSHans Petter Selasky struct mlx5_eqe_qp_srq {
505dc7e38acSHans Petter Selasky 	__be32	reserved[6];
506dc7e38acSHans Petter Selasky 	__be32	qp_srq_n;
507dc7e38acSHans Petter Selasky };
508dc7e38acSHans Petter Selasky 
509dc7e38acSHans Petter Selasky struct mlx5_eqe_cq_err {
510dc7e38acSHans Petter Selasky 	__be32	cqn;
511dc7e38acSHans Petter Selasky 	u8	reserved1[7];
512dc7e38acSHans Petter Selasky 	u8	syndrome;
513dc7e38acSHans Petter Selasky };
514dc7e38acSHans Petter Selasky 
515dc7e38acSHans Petter Selasky struct mlx5_eqe_port_state {
516dc7e38acSHans Petter Selasky 	u8	reserved0[8];
517dc7e38acSHans Petter Selasky 	u8	port;
518dc7e38acSHans Petter Selasky };
519dc7e38acSHans Petter Selasky 
520dc7e38acSHans Petter Selasky struct mlx5_eqe_gpio {
521dc7e38acSHans Petter Selasky 	__be32	reserved0[2];
522dc7e38acSHans Petter Selasky 	__be64	gpio_event;
523dc7e38acSHans Petter Selasky };
524dc7e38acSHans Petter Selasky 
525dc7e38acSHans Petter Selasky struct mlx5_eqe_congestion {
526dc7e38acSHans Petter Selasky 	u8	type;
527dc7e38acSHans Petter Selasky 	u8	rsvd0;
528dc7e38acSHans Petter Selasky 	u8	congestion_level;
529dc7e38acSHans Petter Selasky };
530dc7e38acSHans Petter Selasky 
531dc7e38acSHans Petter Selasky struct mlx5_eqe_stall_vl {
532dc7e38acSHans Petter Selasky 	u8	rsvd0[3];
533dc7e38acSHans Petter Selasky 	u8	port_vl;
534dc7e38acSHans Petter Selasky };
535dc7e38acSHans Petter Selasky 
536dc7e38acSHans Petter Selasky struct mlx5_eqe_cmd {
537dc7e38acSHans Petter Selasky 	__be32	vector;
538dc7e38acSHans Petter Selasky 	__be32	rsvd[6];
539dc7e38acSHans Petter Selasky };
540dc7e38acSHans Petter Selasky 
541dc7e38acSHans Petter Selasky struct mlx5_eqe_page_req {
542dc7e38acSHans Petter Selasky 	u8		rsvd0[2];
543dc7e38acSHans Petter Selasky 	__be16		func_id;
544dc7e38acSHans Petter Selasky 	__be32		num_pages;
545dc7e38acSHans Petter Selasky 	__be32		rsvd1[5];
546dc7e38acSHans Petter Selasky };
547dc7e38acSHans Petter Selasky 
548dc7e38acSHans Petter Selasky struct mlx5_eqe_vport_change {
549dc7e38acSHans Petter Selasky 	u8		rsvd0[2];
550dc7e38acSHans Petter Selasky 	__be16		vport_num;
551dc7e38acSHans Petter Selasky 	__be32		rsvd1[6];
552dc7e38acSHans Petter Selasky };
553dc7e38acSHans Petter Selasky 
554dc7e38acSHans Petter Selasky 
555dc7e38acSHans Petter Selasky #define PORT_MODULE_EVENT_MODULE_STATUS_MASK  0xF
556dc7e38acSHans Petter Selasky #define PORT_MODULE_EVENT_ERROR_TYPE_MASK     0xF
557dc7e38acSHans Petter Selasky 
558dc7e38acSHans Petter Selasky enum {
559ecb4fcc4SHans Petter Selasky 	MLX5_MODULE_STATUS_PLUGGED_ENABLED      = 0x1,
560dc7e38acSHans Petter Selasky 	MLX5_MODULE_STATUS_UNPLUGGED            = 0x2,
561dc7e38acSHans Petter Selasky 	MLX5_MODULE_STATUS_ERROR                = 0x3,
562111b57c3SHans Petter Selasky 	MLX5_MODULE_STATUS_NUM			,
563dc7e38acSHans Petter Selasky };
564dc7e38acSHans Petter Selasky 
565dc7e38acSHans Petter Selasky enum {
566dc7e38acSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED                 = 0x0,
567dc7e38acSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE  = 0x1,
568dc7e38acSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK                             = 0x2,
569dc7e38acSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT               = 0x3,
570dc7e38acSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST              = 0x4,
571ecb4fcc4SHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE                     = 0x5,
572dc7e38acSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE                      = 0x6,
573cb4e4a6eSHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED                      = 0x7,
5746418350cSKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED                  = 0x8,
575d0a40683SKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE                    = 0x9,
576d0a40683SKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT                          = 0xa,
577d0a40683SKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE                          = 0xb,
578d0a40683SKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED          = 0xc,
579d0a40683SKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_HIGH_POWER                            = 0xd,
580d0a40683SKonstantin Belousov 	MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT            = 0xe,
581111b57c3SHans Petter Selasky 	MLX5_MODULE_EVENT_ERROR_NUM		                      ,
582dc7e38acSHans Petter Selasky };
583dc7e38acSHans Petter Selasky 
584dc7e38acSHans Petter Selasky struct mlx5_eqe_port_module_event {
585dc7e38acSHans Petter Selasky 	u8        rsvd0;
586dc7e38acSHans Petter Selasky 	u8        module;
587dc7e38acSHans Petter Selasky 	u8        rsvd1;
588dc7e38acSHans Petter Selasky 	u8        module_status;
589dc7e38acSHans Petter Selasky 	u8        rsvd2[2];
590dc7e38acSHans Petter Selasky 	u8        error_type;
591dc7e38acSHans Petter Selasky };
592dc7e38acSHans Petter Selasky 
5936c7057f7SHans Petter Selasky struct mlx5_eqe_general_notification_event {
5946c7057f7SHans Petter Selasky 	u32       rq_user_index_delay_drop;
5956c7057f7SHans Petter Selasky 	u32       rsvd0[6];
5966c7057f7SHans Petter Selasky };
5976c7057f7SHans Petter Selasky 
598983026eaSHans Petter Selasky struct mlx5_eqe_temp_warning {
599983026eaSHans Petter Selasky 	__be64 sensor_warning_msb;
600983026eaSHans Petter Selasky 	__be64 sensor_warning_lsb;
601983026eaSHans Petter Selasky } __packed;
602983026eaSHans Petter Selasky 
603dc7e38acSHans Petter Selasky union ev_data {
604dc7e38acSHans Petter Selasky 	__be32				raw[7];
605dc7e38acSHans Petter Selasky 	struct mlx5_eqe_cmd		cmd;
606dc7e38acSHans Petter Selasky 	struct mlx5_eqe_comp		comp;
607dc7e38acSHans Petter Selasky 	struct mlx5_eqe_qp_srq		qp_srq;
608dc7e38acSHans Petter Selasky 	struct mlx5_eqe_cq_err		cq_err;
609dc7e38acSHans Petter Selasky 	struct mlx5_eqe_port_state	port;
610dc7e38acSHans Petter Selasky 	struct mlx5_eqe_gpio		gpio;
611dc7e38acSHans Petter Selasky 	struct mlx5_eqe_congestion	cong;
612dc7e38acSHans Petter Selasky 	struct mlx5_eqe_stall_vl	stall_vl;
613dc7e38acSHans Petter Selasky 	struct mlx5_eqe_page_req	req_pages;
614dc7e38acSHans Petter Selasky 	struct mlx5_eqe_port_module_event port_module_event;
615dc7e38acSHans Petter Selasky 	struct mlx5_eqe_vport_change	vport_change;
6166c7057f7SHans Petter Selasky 	struct mlx5_eqe_general_notification_event general_notifications;
617983026eaSHans Petter Selasky 	struct mlx5_eqe_temp_warning	temp_warning;
618dc7e38acSHans Petter Selasky } __packed;
619dc7e38acSHans Petter Selasky 
620dc7e38acSHans Petter Selasky struct mlx5_eqe {
621dc7e38acSHans Petter Selasky 	u8		rsvd0;
622dc7e38acSHans Petter Selasky 	u8		type;
623dc7e38acSHans Petter Selasky 	u8		rsvd1;
624dc7e38acSHans Petter Selasky 	u8		sub_type;
625dc7e38acSHans Petter Selasky 	__be32		rsvd2[7];
626dc7e38acSHans Petter Selasky 	union ev_data	data;
627dc7e38acSHans Petter Selasky 	__be16		rsvd3;
628dc7e38acSHans Petter Selasky 	u8		signature;
629dc7e38acSHans Petter Selasky 	u8		owner;
630dc7e38acSHans Petter Selasky } __packed;
631dc7e38acSHans Petter Selasky 
632dc7e38acSHans Petter Selasky struct mlx5_cmd_prot_block {
633dc7e38acSHans Petter Selasky 	u8		data[MLX5_CMD_DATA_BLOCK_SIZE];
634dc7e38acSHans Petter Selasky 	u8		rsvd0[48];
635dc7e38acSHans Petter Selasky 	__be64		next;
636dc7e38acSHans Petter Selasky 	__be32		block_num;
637dc7e38acSHans Petter Selasky 	u8		rsvd1;
638dc7e38acSHans Petter Selasky 	u8		token;
639dc7e38acSHans Petter Selasky 	u8		ctrl_sig;
640dc7e38acSHans Petter Selasky 	u8		sig;
641dc7e38acSHans Petter Selasky };
642dc7e38acSHans Petter Selasky 
6431c807f67SHans Petter Selasky #define	MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
6441c807f67SHans Petter Selasky 	(MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
6451c807f67SHans Petter Selasky CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
6461c807f67SHans Petter Selasky CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
6471c807f67SHans Petter Selasky 
648dc7e38acSHans Petter Selasky enum {
649dc7e38acSHans Petter Selasky 	MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
650dc7e38acSHans Petter Selasky };
651dc7e38acSHans Petter Selasky 
652dc7e38acSHans Petter Selasky struct mlx5_err_cqe {
653dc7e38acSHans Petter Selasky 	u8	rsvd0[32];
654dc7e38acSHans Petter Selasky 	__be32	srqn;
655dc7e38acSHans Petter Selasky 	u8	rsvd1[18];
656dc7e38acSHans Petter Selasky 	u8	vendor_err_synd;
657dc7e38acSHans Petter Selasky 	u8	syndrome;
658dc7e38acSHans Petter Selasky 	__be32	s_wqe_opcode_qpn;
659dc7e38acSHans Petter Selasky 	__be16	wqe_counter;
660dc7e38acSHans Petter Selasky 	u8	signature;
661dc7e38acSHans Petter Selasky 	u8	op_own;
662dc7e38acSHans Petter Selasky };
663dc7e38acSHans Petter Selasky 
664dc7e38acSHans Petter Selasky struct mlx5_cqe64 {
665dc7e38acSHans Petter Selasky 	u8		tunneled_etc;
666dc7e38acSHans Petter Selasky 	u8		rsvd0[3];
667dc7e38acSHans Petter Selasky 	u8		lro_tcppsh_abort_dupack;
668dc7e38acSHans Petter Selasky 	u8		lro_min_ttl;
669dc7e38acSHans Petter Selasky 	__be16		lro_tcp_win;
670dc7e38acSHans Petter Selasky 	__be32		lro_ack_seq_num;
671dc7e38acSHans Petter Selasky 	__be32		rss_hash_result;
672dc7e38acSHans Petter Selasky 	u8		rss_hash_type;
673dc7e38acSHans Petter Selasky 	u8		ml_path;
674dc7e38acSHans Petter Selasky 	u8		rsvd20[2];
675dc7e38acSHans Petter Selasky 	__be16		check_sum;
676dc7e38acSHans Petter Selasky 	__be16		slid;
677dc7e38acSHans Petter Selasky 	__be32		flags_rqpn;
678dc7e38acSHans Petter Selasky 	u8		hds_ip_ext;
679dc7e38acSHans Petter Selasky 	u8		l4_hdr_type_etc;
680dc7e38acSHans Petter Selasky 	__be16		vlan_info;
681dc7e38acSHans Petter Selasky 	__be32		srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
682dc7e38acSHans Petter Selasky 	__be32		imm_inval_pkey;
683dc7e38acSHans Petter Selasky 	u8		rsvd40[4];
684dc7e38acSHans Petter Selasky 	__be32		byte_cnt;
685dc7e38acSHans Petter Selasky 	__be64		timestamp;
686dc7e38acSHans Petter Selasky 	__be32		sop_drop_qpn;
687dc7e38acSHans Petter Selasky 	__be16		wqe_counter;
688dc7e38acSHans Petter Selasky 	u8		signature;
689dc7e38acSHans Petter Selasky 	u8		op_own;
690dc7e38acSHans Petter Selasky };
691dc7e38acSHans Petter Selasky 
692ef23f141SKonstantin Belousov #define	MLX5_CQE_TSTMP_PTP	(1ULL << 63)
693ef23f141SKonstantin Belousov 
694dc7e38acSHans Petter Selasky static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
695dc7e38acSHans Petter Selasky {
696dc7e38acSHans Petter Selasky 	return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
697dc7e38acSHans Petter Selasky }
698dc7e38acSHans Petter Selasky 
699dc7e38acSHans Petter Selasky static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
700dc7e38acSHans Petter Selasky {
701dc7e38acSHans Petter Selasky 	return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
702dc7e38acSHans Petter Selasky }
703dc7e38acSHans Petter Selasky 
704dc7e38acSHans Petter Selasky static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
705dc7e38acSHans Petter Selasky {
706dc7e38acSHans Petter Selasky 	return (cqe->l4_hdr_type_etc >> 4) & 0x7;
707dc7e38acSHans Petter Selasky }
708dc7e38acSHans Petter Selasky 
709dc7e38acSHans Petter Selasky static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
710dc7e38acSHans Petter Selasky {
711dc7e38acSHans Petter Selasky 	return be16_to_cpu(cqe->vlan_info) & 0xfff;
712dc7e38acSHans Petter Selasky }
713dc7e38acSHans Petter Selasky 
714dc7e38acSHans Petter Selasky static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
715dc7e38acSHans Petter Selasky {
716dc7e38acSHans Petter Selasky 	memcpy(smac, &cqe->rss_hash_type , 4);
717dc7e38acSHans Petter Selasky 	memcpy(smac + 4, &cqe->slid , 2);
718dc7e38acSHans Petter Selasky }
719dc7e38acSHans Petter Selasky 
720dc7e38acSHans Petter Selasky static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
721dc7e38acSHans Petter Selasky {
722dc7e38acSHans Petter Selasky 	return cqe->l4_hdr_type_etc & 0x1;
723dc7e38acSHans Petter Selasky }
724dc7e38acSHans Petter Selasky 
725dc7e38acSHans Petter Selasky static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
726dc7e38acSHans Petter Selasky {
727dc7e38acSHans Petter Selasky 	return cqe->tunneled_etc & 0x1;
728dc7e38acSHans Petter Selasky }
729dc7e38acSHans Petter Selasky 
730dc7e38acSHans Petter Selasky enum {
731dc7e38acSHans Petter Selasky 	CQE_L4_HDR_TYPE_NONE			= 0x0,
732dc7e38acSHans Petter Selasky 	CQE_L4_HDR_TYPE_TCP_NO_ACK		= 0x1,
733dc7e38acSHans Petter Selasky 	CQE_L4_HDR_TYPE_UDP			= 0x2,
734dc7e38acSHans Petter Selasky 	CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA		= 0x3,
735dc7e38acSHans Petter Selasky 	CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA	= 0x4,
736dc7e38acSHans Petter Selasky };
737dc7e38acSHans Petter Selasky 
738dc7e38acSHans Petter Selasky enum {
739dc7e38acSHans Petter Selasky 	/* source L3 hash types */
740dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_IP	= 0x3 << 0,
741dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_IPV4	= 0x1 << 0,
742dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_IPV6	= 0x2 << 0,
743dc7e38acSHans Petter Selasky 
744dc7e38acSHans Petter Selasky 	/* destination L3 hash types */
745dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_IP	= 0x3 << 2,
746dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_IPV4	= 0x1 << 2,
747dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_IPV6	= 0x2 << 2,
748dc7e38acSHans Petter Selasky 
749dc7e38acSHans Petter Selasky 	/* source L4 hash types */
750dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_L4	= 0x3 << 4,
751dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_TCP	= 0x1 << 4,
752dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_UDP	= 0x2 << 4,
753dc7e38acSHans Petter Selasky 	CQE_RSS_SRC_HTYPE_IPSEC	= 0x3 << 4,
754dc7e38acSHans Petter Selasky 
755dc7e38acSHans Petter Selasky 	/* destination L4 hash types */
756dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_L4	= 0x3 << 6,
757dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_TCP	= 0x1 << 6,
758dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_UDP	= 0x2 << 6,
759dc7e38acSHans Petter Selasky 	CQE_RSS_DST_HTYPE_IPSEC	= 0x3 << 6,
760dc7e38acSHans Petter Selasky };
761dc7e38acSHans Petter Selasky 
762dc7e38acSHans Petter Selasky enum {
7634b109912SHans Petter Selasky 	MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH	= 0x0,
7644b109912SHans Petter Selasky 	MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6	= 0x1,
7654b109912SHans Petter Selasky 	MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4	= 0x2,
766dc7e38acSHans Petter Selasky };
767dc7e38acSHans Petter Selasky 
768dc7e38acSHans Petter Selasky enum {
769dc7e38acSHans Petter Selasky 	CQE_L2_OK	= 1 << 0,
770dc7e38acSHans Petter Selasky 	CQE_L3_OK	= 1 << 1,
771dc7e38acSHans Petter Selasky 	CQE_L4_OK	= 1 << 2,
772dc7e38acSHans Petter Selasky };
773dc7e38acSHans Petter Selasky 
774dc7e38acSHans Petter Selasky struct mlx5_sig_err_cqe {
775dc7e38acSHans Petter Selasky 	u8		rsvd0[16];
776dc7e38acSHans Petter Selasky 	__be32		expected_trans_sig;
777dc7e38acSHans Petter Selasky 	__be32		actual_trans_sig;
778dc7e38acSHans Petter Selasky 	__be32		expected_reftag;
779dc7e38acSHans Petter Selasky 	__be32		actual_reftag;
780dc7e38acSHans Petter Selasky 	__be16		syndrome;
781dc7e38acSHans Petter Selasky 	u8		rsvd22[2];
782dc7e38acSHans Petter Selasky 	__be32		mkey;
783dc7e38acSHans Petter Selasky 	__be64		err_offset;
784dc7e38acSHans Petter Selasky 	u8		rsvd30[8];
785dc7e38acSHans Petter Selasky 	__be32		qpn;
786dc7e38acSHans Petter Selasky 	u8		rsvd38[2];
787dc7e38acSHans Petter Selasky 	u8		signature;
788dc7e38acSHans Petter Selasky 	u8		op_own;
789dc7e38acSHans Petter Selasky };
790dc7e38acSHans Petter Selasky 
791dc7e38acSHans Petter Selasky struct mlx5_wqe_srq_next_seg {
792dc7e38acSHans Petter Selasky 	u8			rsvd0[2];
793dc7e38acSHans Petter Selasky 	__be16			next_wqe_index;
794dc7e38acSHans Petter Selasky 	u8			signature;
795dc7e38acSHans Petter Selasky 	u8			rsvd1[11];
796dc7e38acSHans Petter Selasky };
797dc7e38acSHans Petter Selasky 
798dc7e38acSHans Petter Selasky union mlx5_ext_cqe {
799dc7e38acSHans Petter Selasky 	struct ib_grh	grh;
800dc7e38acSHans Petter Selasky 	u8		inl[64];
801dc7e38acSHans Petter Selasky };
802dc7e38acSHans Petter Selasky 
803dc7e38acSHans Petter Selasky struct mlx5_cqe128 {
804dc7e38acSHans Petter Selasky 	union mlx5_ext_cqe	inl_grh;
805dc7e38acSHans Petter Selasky 	struct mlx5_cqe64	cqe64;
806dc7e38acSHans Petter Selasky };
807dc7e38acSHans Petter Selasky 
808cb4e4a6eSHans Petter Selasky enum {
809cb4e4a6eSHans Petter Selasky 	MLX5_MKEY_STATUS_FREE = 1 << 6,
810cb4e4a6eSHans Petter Selasky };
811cb4e4a6eSHans Petter Selasky 
812dc7e38acSHans Petter Selasky struct mlx5_mkey_seg {
813dc7e38acSHans Petter Selasky 	/* This is a two bit field occupying bits 31-30.
814dc7e38acSHans Petter Selasky 	 * bit 31 is always 0,
815dc7e38acSHans Petter Selasky 	 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
816dc7e38acSHans Petter Selasky 	 */
817dc7e38acSHans Petter Selasky 	u8		status;
818dc7e38acSHans Petter Selasky 	u8		pcie_control;
819dc7e38acSHans Petter Selasky 	u8		flags;
820dc7e38acSHans Petter Selasky 	u8		version;
821dc7e38acSHans Petter Selasky 	__be32		qpn_mkey7_0;
822dc7e38acSHans Petter Selasky 	u8		rsvd1[4];
823dc7e38acSHans Petter Selasky 	__be32		flags_pd;
824dc7e38acSHans Petter Selasky 	__be64		start_addr;
825dc7e38acSHans Petter Selasky 	__be64		len;
826dc7e38acSHans Petter Selasky 	__be32		bsfs_octo_size;
827dc7e38acSHans Petter Selasky 	u8		rsvd2[16];
828dc7e38acSHans Petter Selasky 	__be32		xlt_oct_size;
829dc7e38acSHans Petter Selasky 	u8		rsvd3[3];
830dc7e38acSHans Petter Selasky 	u8		log2_page_size;
831dc7e38acSHans Petter Selasky 	u8		rsvd4[4];
832dc7e38acSHans Petter Selasky };
833dc7e38acSHans Petter Selasky 
834dc7e38acSHans Petter Selasky #define MLX5_ATTR_EXTENDED_PORT_INFO	cpu_to_be16(0xff90)
835dc7e38acSHans Petter Selasky 
836dc7e38acSHans Petter Selasky enum {
837dc7e38acSHans Petter Selasky 	MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO	= 1 <<  0
838dc7e38acSHans Petter Selasky };
839dc7e38acSHans Petter Selasky 
840cb4e4a6eSHans Petter Selasky static inline int mlx5_host_is_le(void)
841cb4e4a6eSHans Petter Selasky {
842cb4e4a6eSHans Petter Selasky #if defined(__LITTLE_ENDIAN)
843cb4e4a6eSHans Petter Selasky 	return 1;
844cb4e4a6eSHans Petter Selasky #elif defined(__BIG_ENDIAN)
845cb4e4a6eSHans Petter Selasky 	return 0;
846cb4e4a6eSHans Petter Selasky #else
847cb4e4a6eSHans Petter Selasky #error Host endianness not defined
848cb4e4a6eSHans Petter Selasky #endif
849cb4e4a6eSHans Petter Selasky }
850cb4e4a6eSHans Petter Selasky 
851dc7e38acSHans Petter Selasky #define MLX5_CMD_OP_MAX 0x939
852dc7e38acSHans Petter Selasky 
853dc7e38acSHans Petter Selasky enum {
854dc7e38acSHans Petter Selasky 	VPORT_STATE_DOWN		= 0x0,
855dc7e38acSHans Petter Selasky 	VPORT_STATE_UP			= 0x1,
8568982c800SKonstantin Belousov 	VPORT_STATE_FOLLOW		= 0x2,
857dc7e38acSHans Petter Selasky };
858dc7e38acSHans Petter Selasky 
859dc7e38acSHans Petter Selasky enum {
860dc7e38acSHans Petter Selasky 	MLX5_L3_PROT_TYPE_IPV4		= 0,
861dc7e38acSHans Petter Selasky 	MLX5_L3_PROT_TYPE_IPV6		= 1,
862dc7e38acSHans Petter Selasky };
863dc7e38acSHans Petter Selasky 
864dc7e38acSHans Petter Selasky enum {
865dc7e38acSHans Petter Selasky 	MLX5_L4_PROT_TYPE_TCP		= 0,
866dc7e38acSHans Petter Selasky 	MLX5_L4_PROT_TYPE_UDP		= 1,
867dc7e38acSHans Petter Selasky };
868dc7e38acSHans Petter Selasky 
869dc7e38acSHans Petter Selasky enum {
870dc7e38acSHans Petter Selasky 	MLX5_HASH_FIELD_SEL_SRC_IP	= 1 << 0,
871dc7e38acSHans Petter Selasky 	MLX5_HASH_FIELD_SEL_DST_IP	= 1 << 1,
872dc7e38acSHans Petter Selasky 	MLX5_HASH_FIELD_SEL_L4_SPORT	= 1 << 2,
873dc7e38acSHans Petter Selasky 	MLX5_HASH_FIELD_SEL_L4_DPORT	= 1 << 3,
874dc7e38acSHans Petter Selasky 	MLX5_HASH_FIELD_SEL_IPSEC_SPI	= 1 << 4,
875dc7e38acSHans Petter Selasky };
876dc7e38acSHans Petter Selasky 
877dc7e38acSHans Petter Selasky enum {
878dc7e38acSHans Petter Selasky 	MLX5_MATCH_OUTER_HEADERS	= 1 << 0,
879dc7e38acSHans Petter Selasky 	MLX5_MATCH_MISC_PARAMETERS	= 1 << 1,
880dc7e38acSHans Petter Selasky 	MLX5_MATCH_INNER_HEADERS	= 1 << 2,
881dc7e38acSHans Petter Selasky 
882dc7e38acSHans Petter Selasky };
883dc7e38acSHans Petter Selasky 
884dc7e38acSHans Petter Selasky enum {
885dc7e38acSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_NIC_RCV	 = 0,
886dc7e38acSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_EGRESS_ACL  = 2,
887dc7e38acSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
888dc7e38acSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_ESWITCH	 = 4,
889cb4e4a6eSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX	 = 5,
890cb4e4a6eSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX	 = 6,
8915a93b4cdSHans Petter Selasky 	MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
892dc7e38acSHans Petter Selasky };
893dc7e38acSHans Petter Selasky 
894dc7e38acSHans Petter Selasky enum {
895dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE	      = 0,
896dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
897dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE  = 2
898dc7e38acSHans Petter Selasky };
899dc7e38acSHans Petter Selasky 
900dc7e38acSHans Petter Selasky enum {
901dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP  = 1 << 0,
902dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP  = 1 << 1,
903dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
904dc7e38acSHans Petter Selasky 	MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
905dc7e38acSHans Petter Selasky };
906dc7e38acSHans Petter Selasky 
90798a998d5SHans Petter Selasky enum {
90898a998d5SHans Petter Selasky 	MLX5_UC_ADDR_CHANGE = (1 << 0),
90998a998d5SHans Petter Selasky 	MLX5_MC_ADDR_CHANGE = (1 << 1),
91098a998d5SHans Petter Selasky 	MLX5_VLAN_CHANGE    = (1 << 2),
91198a998d5SHans Petter Selasky 	MLX5_PROMISC_CHANGE = (1 << 3),
91298a998d5SHans Petter Selasky 	MLX5_MTU_CHANGE     = (1 << 4),
91398a998d5SHans Petter Selasky };
91498a998d5SHans Petter Selasky 
91598a998d5SHans Petter Selasky enum mlx5_list_type {
91698a998d5SHans Petter Selasky 	MLX5_NIC_VPORT_LIST_TYPE_UC   = 0x0,
91798a998d5SHans Petter Selasky 	MLX5_NIC_VPORT_LIST_TYPE_MC   = 0x1,
91898a998d5SHans Petter Selasky 	MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
91998a998d5SHans Petter Selasky };
92098a998d5SHans Petter Selasky 
92198a998d5SHans Petter Selasky enum {
92298a998d5SHans Petter Selasky 	MLX5_ESW_VPORT_ADMIN_STATE_DOWN  = 0x0,
92398a998d5SHans Petter Selasky 	MLX5_ESW_VPORT_ADMIN_STATE_UP    = 0x1,
92498a998d5SHans Petter Selasky 	MLX5_ESW_VPORT_ADMIN_STATE_AUTO  = 0x2,
92598a998d5SHans Petter Selasky };
92690cc1c77SHans Petter Selasky 
927dc7e38acSHans Petter Selasky /* MLX5 DEV CAPs */
928dc7e38acSHans Petter Selasky 
929dc7e38acSHans Petter Selasky /* TODO: EAT.ME */
930dc7e38acSHans Petter Selasky enum mlx5_cap_mode {
931dc7e38acSHans Petter Selasky 	HCA_CAP_OPMOD_GET_MAX	= 0,
932dc7e38acSHans Petter Selasky 	HCA_CAP_OPMOD_GET_CUR	= 1,
933dc7e38acSHans Petter Selasky };
934dc7e38acSHans Petter Selasky 
935dc7e38acSHans Petter Selasky enum mlx5_cap_type {
936dc7e38acSHans Petter Selasky 	MLX5_CAP_GENERAL = 0,
937dc7e38acSHans Petter Selasky 	MLX5_CAP_ETHERNET_OFFLOADS,
938dc7e38acSHans Petter Selasky 	MLX5_CAP_ODP,
939dc7e38acSHans Petter Selasky 	MLX5_CAP_ATOMIC,
940dc7e38acSHans Petter Selasky 	MLX5_CAP_ROCE,
941dc7e38acSHans Petter Selasky 	MLX5_CAP_IPOIB_OFFLOADS,
942dc7e38acSHans Petter Selasky 	MLX5_CAP_EOIB_OFFLOADS,
943dc7e38acSHans Petter Selasky 	MLX5_CAP_FLOW_TABLE,
944dc7e38acSHans Petter Selasky 	MLX5_CAP_ESWITCH_FLOW_TABLE,
945dc7e38acSHans Petter Selasky 	MLX5_CAP_ESWITCH,
946cb4e4a6eSHans Petter Selasky 	MLX5_CAP_SNAPSHOT,
947cb4e4a6eSHans Petter Selasky 	MLX5_CAP_VECTOR_CALC,
948cb4e4a6eSHans Petter Selasky 	MLX5_CAP_QOS,
949cb4e4a6eSHans Petter Selasky 	MLX5_CAP_DEBUG,
95004f1690bSHans Petter Selasky 	MLX5_CAP_NVME,
95104f1690bSHans Petter Selasky 	MLX5_CAP_DMC,
95204f1690bSHans Petter Selasky 	MLX5_CAP_DEC,
95304f1690bSHans Petter Selasky 	MLX5_CAP_TLS,
954dc7e38acSHans Petter Selasky 	/* NUM OF CAP Types */
955dc7e38acSHans Petter Selasky 	MLX5_CAP_NUM
956dc7e38acSHans Petter Selasky };
957dc7e38acSHans Petter Selasky 
958ed0cee0bSHans Petter Selasky enum mlx5_qcam_reg_groups {
959ed0cee0bSHans Petter Selasky 	MLX5_QCAM_REGS_FIRST_128 = 0x0,
960ed0cee0bSHans Petter Selasky };
961ed0cee0bSHans Petter Selasky 
962ed0cee0bSHans Petter Selasky enum mlx5_qcam_feature_groups {
963ed0cee0bSHans Petter Selasky 	MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
964ed0cee0bSHans Petter Selasky };
965ed0cee0bSHans Petter Selasky 
966ae73b041SHans Petter Selasky enum mlx5_pcam_reg_groups {
967ae73b041SHans Petter Selasky 	MLX5_PCAM_REGS_5000_TO_507F = 0x0,
968ae73b041SHans Petter Selasky };
969ae73b041SHans Petter Selasky 
970ae73b041SHans Petter Selasky enum mlx5_pcam_feature_groups {
971ae73b041SHans Petter Selasky 	MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
972ae73b041SHans Petter Selasky };
973ae73b041SHans Petter Selasky 
974ae73b041SHans Petter Selasky enum mlx5_mcam_reg_groups {
975ae73b041SHans Petter Selasky 	MLX5_MCAM_REGS_FIRST_128 = 0x0,
976ae73b041SHans Petter Selasky };
977ae73b041SHans Petter Selasky 
978ae73b041SHans Petter Selasky enum mlx5_mcam_feature_groups {
979ae73b041SHans Petter Selasky 	MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
980ae73b041SHans Petter Selasky };
981ae73b041SHans Petter Selasky 
982dc7e38acSHans Petter Selasky /* GET Dev Caps macros */
983dc7e38acSHans Petter Selasky #define MLX5_CAP_GEN(mdev, cap) \
984dc7e38acSHans Petter Selasky 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
985dc7e38acSHans Petter Selasky 
98604f1690bSHans Petter Selasky #define	MLX5_CAP_GEN_64(mdev, cap)					\
98704f1690bSHans Petter Selasky 	MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
98804f1690bSHans Petter Selasky 
989dc7e38acSHans Petter Selasky #define MLX5_CAP_GEN_MAX(mdev, cap) \
990dc7e38acSHans Petter Selasky 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
991dc7e38acSHans Petter Selasky 
992dc7e38acSHans Petter Selasky #define MLX5_CAP_ETH(mdev, cap) \
993dc7e38acSHans Petter Selasky 	MLX5_GET(per_protocol_networking_offload_caps,\
994dc7e38acSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
995dc7e38acSHans Petter Selasky 
996dc7e38acSHans Petter Selasky #define MLX5_CAP_ETH_MAX(mdev, cap) \
997dc7e38acSHans Petter Selasky 	MLX5_GET(per_protocol_networking_offload_caps,\
998dc7e38acSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
999dc7e38acSHans Petter Selasky 
1000dc7e38acSHans Petter Selasky #define MLX5_CAP_ROCE(mdev, cap) \
1001dc7e38acSHans Petter Selasky 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1002dc7e38acSHans Petter Selasky 
1003dc7e38acSHans Petter Selasky #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1004dc7e38acSHans Petter Selasky 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1005dc7e38acSHans Petter Selasky 
1006dc7e38acSHans Petter Selasky #define MLX5_CAP_ATOMIC(mdev, cap) \
1007dc7e38acSHans Petter Selasky 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1008dc7e38acSHans Petter Selasky 
1009dc7e38acSHans Petter Selasky #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1010dc7e38acSHans Petter Selasky 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1011dc7e38acSHans Petter Selasky 
1012dc7e38acSHans Petter Selasky #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1013dc7e38acSHans Petter Selasky 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1014dc7e38acSHans Petter Selasky 
1015dc7e38acSHans Petter Selasky #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1016dc7e38acSHans Petter Selasky 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1017dc7e38acSHans Petter Selasky 
1018dc7e38acSHans Petter Selasky #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1019dc7e38acSHans Petter Selasky 	MLX5_GET(flow_table_eswitch_cap, \
1020dc7e38acSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1021dc7e38acSHans Petter Selasky 
1022dc7e38acSHans Petter Selasky #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1023dc7e38acSHans Petter Selasky 	MLX5_GET(flow_table_eswitch_cap, \
1024dc7e38acSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1025dc7e38acSHans Petter Selasky 
1026cb4e4a6eSHans Petter Selasky #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1027cb4e4a6eSHans Petter Selasky 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
102898a998d5SHans Petter Selasky 
1029cb4e4a6eSHans Petter Selasky #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1030cb4e4a6eSHans Petter Selasky 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
103198a998d5SHans Petter Selasky 
1032cb4e4a6eSHans Petter Selasky #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1033cb4e4a6eSHans Petter Selasky 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
103498a998d5SHans Petter Selasky 
1035cb4e4a6eSHans Petter Selasky #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1036cb4e4a6eSHans Petter Selasky 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1037cb4e4a6eSHans Petter Selasky 
1038cb4e4a6eSHans Petter Selasky #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1039cb4e4a6eSHans Petter Selasky 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1040cb4e4a6eSHans Petter Selasky 
1041cb4e4a6eSHans Petter Selasky #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1042cb4e4a6eSHans Petter Selasky 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
104398a998d5SHans Petter Selasky 
1044dc7e38acSHans Petter Selasky #define MLX5_CAP_ESW(mdev, cap) \
1045dc7e38acSHans Petter Selasky 	MLX5_GET(e_switch_cap, \
1046dc7e38acSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1047dc7e38acSHans Petter Selasky 
1048dc7e38acSHans Petter Selasky #define MLX5_CAP_ESW_MAX(mdev, cap) \
1049dc7e38acSHans Petter Selasky 	MLX5_GET(e_switch_cap, \
1050dc7e38acSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1051dc7e38acSHans Petter Selasky 
1052dc7e38acSHans Petter Selasky #define MLX5_CAP_ODP(mdev, cap)\
1053dc7e38acSHans Petter Selasky 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1054dc7e38acSHans Petter Selasky 
1055dc7e38acSHans Petter Selasky #define MLX5_CAP_ODP_MAX(mdev, cap)\
1056dc7e38acSHans Petter Selasky 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1057dc7e38acSHans Petter Selasky 
1058cb4e4a6eSHans Petter Selasky #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1059cb4e4a6eSHans Petter Selasky 	MLX5_GET(snapshot_cap, \
1060cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1061cb4e4a6eSHans Petter Selasky 
1062cb4e4a6eSHans Petter Selasky #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1063cb4e4a6eSHans Petter Selasky 	MLX5_GET(snapshot_cap, \
1064cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1065cb4e4a6eSHans Petter Selasky 
1066cb4e4a6eSHans Petter Selasky #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1067cb4e4a6eSHans Petter Selasky 	MLX5_GET(per_protocol_networking_offload_caps,\
1068cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1069cb4e4a6eSHans Petter Selasky 
1070cb4e4a6eSHans Petter Selasky #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1071cb4e4a6eSHans Petter Selasky 	MLX5_GET(per_protocol_networking_offload_caps,\
1072cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1073cb4e4a6eSHans Petter Selasky 
1074cb4e4a6eSHans Petter Selasky #define MLX5_CAP_DEBUG(mdev, cap) \
1075cb4e4a6eSHans Petter Selasky 	MLX5_GET(debug_cap, \
1076cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1077cb4e4a6eSHans Petter Selasky 
1078cb4e4a6eSHans Petter Selasky #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1079cb4e4a6eSHans Petter Selasky 	MLX5_GET(debug_cap, \
1080cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1081cb4e4a6eSHans Petter Selasky 
1082cb4e4a6eSHans Petter Selasky #define MLX5_CAP_QOS(mdev, cap) \
1083cb4e4a6eSHans Petter Selasky 	MLX5_GET(qos_cap,\
1084cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1085cb4e4a6eSHans Petter Selasky 
1086cb4e4a6eSHans Petter Selasky #define MLX5_CAP_QOS_MAX(mdev, cap) \
1087cb4e4a6eSHans Petter Selasky 	MLX5_GET(qos_cap,\
1088cb4e4a6eSHans Petter Selasky 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1089cb4e4a6eSHans Petter Selasky 
10905a8145f6SHans Petter Selasky #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
10915a8145f6SHans Petter Selasky 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
10925a8145f6SHans Petter Selasky 
109396425f44SHans Petter Selasky #define	MLX5_CAP_PCAM_REG(mdev, reg) \
109496425f44SHans Petter Selasky 	MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
109596425f44SHans Petter Selasky 
10965a8145f6SHans Petter Selasky #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
10975a8145f6SHans Petter Selasky 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
10985a8145f6SHans Petter Selasky 
10999e3c0999SHans Petter Selasky #define	MLX5_CAP_MCAM_REG(mdev, reg) \
11009e3c0999SHans Petter Selasky 	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
11019e3c0999SHans Petter Selasky 
1102ed0cee0bSHans Petter Selasky #define	MLX5_CAP_QCAM_REG(mdev, fld) \
1103ed0cee0bSHans Petter Selasky 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1104ed0cee0bSHans Petter Selasky 
1105ed0cee0bSHans Petter Selasky #define	MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1106ed0cee0bSHans Petter Selasky 	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1107ed0cee0bSHans Petter Selasky 
1108e9dcd831SSlava Shwartsman #define MLX5_CAP_FPGA(mdev, cap) \
1109e9dcd831SSlava Shwartsman 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1110e9dcd831SSlava Shwartsman 
1111e9dcd831SSlava Shwartsman #define MLX5_CAP64_FPGA(mdev, cap) \
1112e9dcd831SSlava Shwartsman 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1113e9dcd831SSlava Shwartsman 
111404f1690bSHans Petter Selasky #define	MLX5_CAP_TLS(mdev, cap) \
111504f1690bSHans Petter Selasky 	MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
111604f1690bSHans Petter Selasky 
1117dc7e38acSHans Petter Selasky enum {
1118dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_OK			= 0x0,
1119dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_INT_ERR			= 0x1,
1120dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_OP_ERR		= 0x2,
1121dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_PARAM_ERR		= 0x3,
1122dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_SYS_STATE_ERR		= 0x4,
1123dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_RES_ERR		= 0x5,
1124dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_RES_BUSY			= 0x6,
1125dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_LIM_ERR			= 0x8,
1126dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_RES_STATE_ERR		= 0x9,
1127dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_IX_ERR			= 0xa,
1128dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_NO_RES_ERR		= 0xf,
1129dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_INP_LEN_ERR		= 0x50,
1130dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_OUTP_LEN_ERR		= 0x51,
1131dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_QP_STATE_ERR		= 0x10,
1132dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_PKT_ERR		= 0x30,
1133dc7e38acSHans Petter Selasky 	MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR	= 0x40,
1134dc7e38acSHans Petter Selasky };
1135dc7e38acSHans Petter Selasky 
1136dc7e38acSHans Petter Selasky enum {
1137dc7e38acSHans Petter Selasky 	MLX5_IEEE_802_3_COUNTERS_GROUP	      = 0x0,
1138dc7e38acSHans Petter Selasky 	MLX5_RFC_2863_COUNTERS_GROUP	      = 0x1,
1139dc7e38acSHans Petter Selasky 	MLX5_RFC_2819_COUNTERS_GROUP	      = 0x2,
1140dc7e38acSHans Petter Selasky 	MLX5_RFC_3635_COUNTERS_GROUP	      = 0x3,
1141dc7e38acSHans Petter Selasky 	MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1142cb022443SHans Petter Selasky 	MLX5_ETHERNET_DISCARD_COUNTERS_GROUP  = 0x6,
1143dc7e38acSHans Petter Selasky 	MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1144dc7e38acSHans Petter Selasky 	MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1145dc7e38acSHans Petter Selasky 	MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
11464b109912SHans Petter Selasky 	MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1147cb022443SHans Petter Selasky 	MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1148dc7e38acSHans Petter Selasky };
1149dc7e38acSHans Petter Selasky 
1150dc7e38acSHans Petter Selasky enum {
1151cb4e4a6eSHans Petter Selasky 	MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP       = 0x0,
1152cb4e4a6eSHans Petter Selasky 	MLX5_PCIE_LANE_COUNTERS_GROUP	      = 0x1,
1153cb4e4a6eSHans Petter Selasky 	MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1154cb4e4a6eSHans Petter Selasky };
1155cb4e4a6eSHans Petter Selasky 
1156cb4e4a6eSHans Petter Selasky enum {
1157dc7e38acSHans Petter Selasky 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1158dc7e38acSHans Petter Selasky 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1159dc7e38acSHans Petter Selasky };
1160dc7e38acSHans Petter Selasky 
1161dc7e38acSHans Petter Selasky enum {
1162dc7e38acSHans Petter Selasky 	MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2           = 0x0,
1163dc7e38acSHans Petter Selasky 	MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1164dc7e38acSHans Petter Selasky 	MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1165dc7e38acSHans Petter Selasky };
1166dc7e38acSHans Petter Selasky 
116705399002SHans Petter Selasky enum mlx5_inline_modes {
116805399002SHans Petter Selasky 	MLX5_INLINE_MODE_NONE,
116905399002SHans Petter Selasky 	MLX5_INLINE_MODE_L2,
117005399002SHans Petter Selasky 	MLX5_INLINE_MODE_IP,
117105399002SHans Petter Selasky 	MLX5_INLINE_MODE_TCP_UDP,
117205399002SHans Petter Selasky };
117305399002SHans Petter Selasky 
1174dc7e38acSHans Petter Selasky enum {
1175dc7e38acSHans Petter Selasky 	MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1176dc7e38acSHans Petter Selasky };
1177dc7e38acSHans Petter Selasky 
1178dc7e38acSHans Petter Selasky static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1179dc7e38acSHans Petter Selasky {
1180dc7e38acSHans Petter Selasky 	if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1181dc7e38acSHans Petter Selasky 		return 0;
1182dc7e38acSHans Petter Selasky 	return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1183dc7e38acSHans Petter Selasky }
1184dc7e38acSHans Petter Selasky 
1185dc7e38acSHans Petter Selasky struct mlx5_ifc_mcia_reg_bits {
1186dc7e38acSHans Petter Selasky 	u8         l[0x1];
1187dc7e38acSHans Petter Selasky 	u8         reserved_0[0x7];
1188dc7e38acSHans Petter Selasky 	u8         module[0x8];
1189dc7e38acSHans Petter Selasky 	u8         reserved_1[0x8];
1190dc7e38acSHans Petter Selasky 	u8         status[0x8];
1191dc7e38acSHans Petter Selasky 
1192dc7e38acSHans Petter Selasky 	u8         i2c_device_address[0x8];
1193dc7e38acSHans Petter Selasky 	u8         page_number[0x8];
1194dc7e38acSHans Petter Selasky 	u8         device_address[0x10];
1195dc7e38acSHans Petter Selasky 
1196dc7e38acSHans Petter Selasky 	u8         reserved_2[0x10];
1197dc7e38acSHans Petter Selasky 	u8         size[0x10];
1198dc7e38acSHans Petter Selasky 
1199dc7e38acSHans Petter Selasky 	u8         reserved_3[0x20];
1200dc7e38acSHans Petter Selasky 
1201dc7e38acSHans Petter Selasky 	u8         dword_0[0x20];
1202dc7e38acSHans Petter Selasky 	u8         dword_1[0x20];
1203dc7e38acSHans Petter Selasky 	u8         dword_2[0x20];
1204dc7e38acSHans Petter Selasky 	u8         dword_3[0x20];
1205dc7e38acSHans Petter Selasky 	u8         dword_4[0x20];
1206dc7e38acSHans Petter Selasky 	u8         dword_5[0x20];
1207dc7e38acSHans Petter Selasky 	u8         dword_6[0x20];
1208dc7e38acSHans Petter Selasky 	u8         dword_7[0x20];
1209dc7e38acSHans Petter Selasky 	u8         dword_8[0x20];
1210dc7e38acSHans Petter Selasky 	u8         dword_9[0x20];
1211dc7e38acSHans Petter Selasky 	u8         dword_10[0x20];
1212dc7e38acSHans Petter Selasky 	u8         dword_11[0x20];
1213dc7e38acSHans Petter Selasky };
1214dc7e38acSHans Petter Selasky 
1215dc7e38acSHans Petter Selasky #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
121690cc1c77SHans Petter Selasky 
121790cc1c77SHans Petter Selasky struct mlx5_mini_cqe8 {
121890cc1c77SHans Petter Selasky 	union {
1219adea303cSHans Petter Selasky 		__be32 rx_hash_result;
1220adea303cSHans Petter Selasky 		__be16 checksum;
1221adea303cSHans Petter Selasky 		__be16 rsvd;
122290cc1c77SHans Petter Selasky 		struct {
1223adea303cSHans Petter Selasky 			__be16 wqe_counter;
122490cc1c77SHans Petter Selasky 			u8  s_wqe_opcode;
122590cc1c77SHans Petter Selasky 			u8  reserved;
122690cc1c77SHans Petter Selasky 		} s_wqe_info;
122790cc1c77SHans Petter Selasky 	};
1228adea303cSHans Petter Selasky 	__be32 byte_cnt;
122990cc1c77SHans Petter Selasky };
123090cc1c77SHans Petter Selasky 
123190cc1c77SHans Petter Selasky enum {
123290cc1c77SHans Petter Selasky 	MLX5_NO_INLINE_DATA,
123390cc1c77SHans Petter Selasky 	MLX5_INLINE_DATA32_SEG,
123490cc1c77SHans Petter Selasky 	MLX5_INLINE_DATA64_SEG,
123590cc1c77SHans Petter Selasky 	MLX5_COMPRESSED,
123690cc1c77SHans Petter Selasky };
123790cc1c77SHans Petter Selasky 
123890cc1c77SHans Petter Selasky enum mlx5_exp_cqe_zip_recv_type {
123990cc1c77SHans Petter Selasky 	MLX5_CQE_FORMAT_HASH,
124090cc1c77SHans Petter Selasky 	MLX5_CQE_FORMAT_CSUM,
124190cc1c77SHans Petter Selasky };
124290cc1c77SHans Petter Selasky 
124390cc1c77SHans Petter Selasky #define MLX5E_CQE_FORMAT_MASK 0xc
124490cc1c77SHans Petter Selasky static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
124590cc1c77SHans Petter Selasky {
124690cc1c77SHans Petter Selasky 	return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
124790cc1c77SHans Petter Selasky }
124890cc1c77SHans Petter Selasky 
12496c7057f7SHans Petter Selasky enum {
12506c7057f7SHans Petter Selasky 	MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1251adb6fd50SHans Petter Selasky 	MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
12526c7057f7SHans Petter Selasky };
12536c7057f7SHans Petter Selasky 
1254939c79a2SHans Petter Selasky enum {
1255939c79a2SHans Petter Selasky 	MLX5_FRL_LEVEL3 = 0x8,
1256939c79a2SHans Petter Selasky 	MLX5_FRL_LEVEL6 = 0x40,
1257939c79a2SHans Petter Selasky };
1258939c79a2SHans Petter Selasky 
1259cb4e4a6eSHans Petter Selasky /* 8 regular priorities + 1 for multicast */
1260cb4e4a6eSHans Petter Selasky #define MLX5_NUM_BYPASS_FTS	9
1261cb4e4a6eSHans Petter Selasky 
1262dc7e38acSHans Petter Selasky #endif /* MLX5_DEVICE_H */
1263