1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 38 #include <dev/mlx4/device.h> 39 40 #define MLX4_INVALID_LKEY 0x100 41 42 #define DS_SIZE_ALIGNMENT 16 43 44 #define SET_BYTE_COUNT(byte_count) cpu_to_be32(byte_count) 45 #define SET_LSO_MSS(mss_hdr_size) cpu_to_be32(mss_hdr_size) 46 #define DS_BYTE_COUNT_MASK cpu_to_be32(0x7fffffff) 47 48 enum ib_m_qp_attr_mask { 49 IB_M_EXT_CLASS_1 = 1 << 28, 50 IB_M_EXT_CLASS_2 = 1 << 29, 51 IB_M_EXT_CLASS_3 = 1 << 30, 52 53 IB_M_QP_MOD_VEND_MASK = (IB_M_EXT_CLASS_1 | IB_M_EXT_CLASS_2 | 54 IB_M_EXT_CLASS_3) 55 }; 56 57 enum mlx4_qp_optpar { 58 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 59 MLX4_QP_OPTPAR_RRE = 1 << 1, 60 MLX4_QP_OPTPAR_RAE = 1 << 2, 61 MLX4_QP_OPTPAR_RWE = 1 << 3, 62 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 63 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 64 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 65 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 66 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 67 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 68 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 69 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 70 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 71 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 72 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 73 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 74 }; 75 76 enum mlx4_qp_state { 77 MLX4_QP_STATE_RST = 0, 78 MLX4_QP_STATE_INIT = 1, 79 MLX4_QP_STATE_RTR = 2, 80 MLX4_QP_STATE_RTS = 3, 81 MLX4_QP_STATE_SQER = 4, 82 MLX4_QP_STATE_SQD = 5, 83 MLX4_QP_STATE_ERR = 6, 84 MLX4_QP_STATE_SQ_DRAINING = 7, 85 MLX4_QP_NUM_STATE 86 }; 87 88 enum { 89 MLX4_QP_ST_RC = 0x0, 90 MLX4_QP_ST_UC = 0x1, 91 MLX4_QP_ST_RD = 0x2, 92 MLX4_QP_ST_UD = 0x3, 93 MLX4_QP_ST_XRC = 0x6, 94 MLX4_QP_ST_MLX = 0x7 95 }; 96 97 enum { 98 MLX4_QP_PM_MIGRATED = 0x3, 99 MLX4_QP_PM_ARMED = 0x0, 100 MLX4_QP_PM_REARM = 0x1 101 }; 102 103 enum { 104 /* params1 */ 105 MLX4_QP_BIT_SRE = 1 << 15, 106 MLX4_QP_BIT_SWE = 1 << 14, 107 MLX4_QP_BIT_SAE = 1 << 13, 108 /* params2 */ 109 MLX4_QP_BIT_RRE = 1 << 15, 110 MLX4_QP_BIT_RWE = 1 << 14, 111 MLX4_QP_BIT_RAE = 1 << 13, 112 MLX4_QP_BIT_RIC = 1 << 4, 113 MLX4_QP_BIT_COLL_SYNC_RQ = 1 << 2, 114 MLX4_QP_BIT_COLL_SYNC_SQ = 1 << 1, 115 MLX4_QP_BIT_COLL_MASTER = 1 << 0 116 }; 117 118 enum { 119 MLX4_RSS_HASH_XOR = 0, 120 MLX4_RSS_HASH_TOP = 1, 121 122 MLX4_RSS_UDP_IPV6 = 1 << 0, 123 MLX4_RSS_UDP_IPV4 = 1 << 1, 124 MLX4_RSS_TCP_IPV6 = 1 << 2, 125 MLX4_RSS_IPV6 = 1 << 3, 126 MLX4_RSS_TCP_IPV4 = 1 << 4, 127 MLX4_RSS_IPV4 = 1 << 5, 128 129 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 130 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 131 /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 132 MLX4_RSS_QPC_FLAG_OFFSET = 13, 133 }; 134 135 struct mlx4_rss_context { 136 __be32 base_qpn; 137 __be32 default_qpn; 138 u16 reserved; 139 u8 hash_fn; 140 u8 flags; 141 __be32 rss_key[10]; 142 __be32 base_qpn_udp; 143 }; 144 145 struct mlx4_qp_path { 146 u8 fl; 147 u8 vlan_control; 148 u8 disable_pkey_check; 149 u8 pkey_index; 150 u8 counter_index; 151 u8 grh_mylmc; 152 __be16 rlid; 153 u8 ackto; 154 u8 mgid_index; 155 u8 static_rate; 156 u8 hop_limit; 157 __be32 tclass_flowlabel; 158 u8 rgid[16]; 159 u8 sched_queue; 160 u8 vlan_index; 161 u8 feup; 162 u8 fvl_rx; 163 u8 reserved4[2]; 164 u8 dmac[6]; 165 }; 166 167 enum { /* fl */ 168 MLX4_FL_CV = 1 << 6, 169 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2, 170 MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1, 171 MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0, 172 }; 173 enum { /* vlan_control */ 174 MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7, 175 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 176 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 177 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1,/* 802.1p priorty tag*/ 178 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 179 }; 180 181 enum { /* feup */ 182 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 183 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 184 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 185 }; 186 187 enum { /* fvl_rx */ 188 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 189 }; 190 191 struct mlx4_qp_context { 192 __be32 flags; 193 __be32 pd; 194 u8 mtu_msgmax; 195 u8 rq_size_stride; 196 u8 sq_size_stride; 197 u8 rlkey; 198 __be32 usr_page; 199 __be32 local_qpn; 200 __be32 remote_qpn; 201 struct mlx4_qp_path pri_path; 202 struct mlx4_qp_path alt_path; 203 __be32 params1; 204 u32 reserved1; 205 __be32 next_send_psn; 206 __be32 cqn_send; 207 u32 reserved2[2]; 208 __be32 last_acked_psn; 209 __be32 ssn; 210 __be32 params2; 211 __be32 rnr_nextrecvpsn; 212 __be32 xrcd; 213 __be32 cqn_recv; 214 __be64 db_rec_addr; 215 __be32 qkey; 216 __be32 srqn; 217 __be32 msn; 218 __be16 rq_wqe_counter; 219 __be16 sq_wqe_counter; 220 u32 reserved3[2]; 221 __be32 param3; 222 __be32 nummmcpeers_basemkey; 223 u8 log_page_size; 224 u8 reserved4[2]; 225 u8 mtt_base_addr_h; 226 __be32 mtt_base_addr_l; 227 u32 reserved5[10]; 228 }; 229 230 struct mlx4_update_qp_context { 231 __be64 qp_mask; 232 __be64 primary_addr_path_mask; 233 __be64 secondary_addr_path_mask; 234 u64 reserved1; 235 struct mlx4_qp_context qp_context; 236 u64 reserved2[58]; 237 }; 238 239 enum { 240 MLX4_UPD_QP_MASK_PM_STATE = 32, 241 MLX4_UPD_QP_MASK_VSD = 33, 242 }; 243 244 enum { 245 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 246 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 247 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 248 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 249 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 250 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 251 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 252 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 253 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 254 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 255 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 256 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 257 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 258 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 259 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 260 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 261 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 262 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32, 263 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32, 264 }; 265 266 enum { /* param3 */ 267 MLX4_STRIP_VLAN = 1 << 30 268 }; 269 270 271 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 272 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 273 274 enum { 275 MLX4_WQE_CTRL_OWN = 1 << 31, 276 MLX4_WQE_CTRL_NEC = 1 << 29, 277 MLX4_WQE_CTRL_RR = 1 << 6, 278 MLX4_WQE_CTRL_FENCE = 1 << 6, 279 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 280 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 281 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 282 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 283 MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 284 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 285 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 286 }; 287 288 struct mlx4_wqe_ctrl_seg { 289 __be32 owner_opcode; 290 __be16 vlan_tag; 291 u8 ins_vlan; 292 u8 fence_size; 293 /* 294 * High 24 bits are SRC remote buffer; low 8 bits are flags: 295 * [7] SO (strong ordering) 296 * [5] TCP/UDP checksum 297 * [4] IP checksum 298 * [3:2] C (generate completion queue entry) 299 * [1] SE (solicited event) 300 * [0] FL (force loopback) 301 */ 302 union { 303 __be32 srcrb_flags; 304 __be16 srcrb_flags16[2]; 305 }; 306 /* 307 * imm is immediate data for send/RDMA write w/ immediate; 308 * also invalidation key for send with invalidate; input 309 * modifier for WQEs on CCQs. 310 */ 311 __be32 imm; 312 }; 313 314 enum { 315 MLX4_WQE_MLX_VL15 = 1 << 17, 316 MLX4_WQE_MLX_SLR = 1 << 16 317 }; 318 319 struct mlx4_wqe_mlx_seg { 320 u8 owner; 321 u8 reserved1[2]; 322 u8 opcode; 323 __be16 sched_prio; 324 u8 reserved2; 325 u8 size; 326 /* 327 * [17] VL15 328 * [16] SLR 329 * [15:12] static rate 330 * [11:8] SL 331 * [4] ICRC 332 * [3:2] C 333 * [0] FL (force loopback) 334 */ 335 __be32 flags; 336 __be16 rlid; 337 u16 reserved3; 338 }; 339 340 struct mlx4_wqe_datagram_seg { 341 __be32 av[8]; 342 __be32 dqpn; 343 __be32 qkey; 344 __be16 vlan; 345 u8 mac[6]; 346 }; 347 348 struct mlx4_wqe_lso_seg { 349 __be32 mss_hdr_size; 350 __be32 header[0]; 351 }; 352 353 enum mlx4_wqe_bind_seg_flags2 { 354 MLX4_WQE_BIND_TYPE_2 = (1<<31), 355 MLX4_WQE_BIND_ZERO_BASED = (1<<30), 356 }; 357 358 struct mlx4_wqe_bind_seg { 359 __be32 flags1; 360 __be32 flags2; 361 __be32 new_rkey; 362 __be32 lkey; 363 __be64 addr; 364 __be64 length; 365 }; 366 367 enum { 368 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 369 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 370 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 371 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 372 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 373 }; 374 375 struct mlx4_wqe_fmr_seg { 376 __be32 flags; 377 __be32 mem_key; 378 __be64 buf_list; 379 __be64 start_addr; 380 __be64 reg_len; 381 __be32 offset; 382 __be32 page_size; 383 u32 reserved[2]; 384 }; 385 386 struct mlx4_wqe_fmr_ext_seg { 387 u8 flags; 388 u8 reserved; 389 __be16 app_mask; 390 __be16 wire_app_tag; 391 __be16 mem_app_tag; 392 __be32 wire_ref_tag_base; 393 __be32 mem_ref_tag_base; 394 }; 395 396 struct mlx4_wqe_local_inval_seg { 397 u64 reserved1; 398 __be32 mem_key; 399 u32 reserved2; 400 u64 reserved3[2]; 401 }; 402 403 struct mlx4_wqe_raddr_seg { 404 __be64 raddr; 405 __be32 rkey; 406 u32 reserved; 407 }; 408 409 struct mlx4_wqe_atomic_seg { 410 __be64 swap_add; 411 __be64 compare; 412 }; 413 414 struct mlx4_wqe_masked_atomic_seg { 415 __be64 swap_add; 416 __be64 compare; 417 __be64 swap_add_mask; 418 __be64 compare_mask; 419 }; 420 421 struct mlx4_wqe_data_seg { 422 __be32 byte_count; 423 __be32 lkey; 424 __be64 addr; 425 }; 426 427 enum { 428 MLX4_INLINE_ALIGN = 64, 429 MLX4_INLINE_SEG = 1 << 31, 430 }; 431 432 struct mlx4_wqe_inline_seg { 433 __be32 byte_count; 434 }; 435 436 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 437 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 438 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 439 int sqd_event, struct mlx4_qp *qp); 440 441 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 442 struct mlx4_qp_context *context); 443 444 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 445 struct mlx4_qp_context *context, 446 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 447 448 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 449 { 450 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 451 } 452 453 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 454 455 #endif /* MLX4_QP_H */ 456