1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/slab.h> 36 #include <linux/netdevice.h> 37 #include <linux/bitops.h> 38 39 #include <rdma/ib_cache.h> 40 #include <rdma/ib_pack.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_mad.h> 43 44 #include <dev/mlx4/qp.h> 45 #include <dev/mlx4/driver.h> 46 #include <linux/io.h> 47 48 #include "mlx4_ib.h" 49 #include "user.h" 50 51 #define asm __asm 52 53 enum { 54 MLX4_IB_ACK_REQ_FREQ = 8, 55 }; 56 57 enum { 58 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 59 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 60 MLX4_IB_LINK_TYPE_IB = 0, 61 MLX4_IB_LINK_TYPE_ETH = 1 62 }; 63 64 enum { 65 /* 66 * Largest possible UD header: send with GRH and immediate 67 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 68 * tag. (LRH would only use 8 bytes, so Ethernet is the 69 * biggest case) 70 */ 71 MLX4_IB_UD_HEADER_SIZE = 82, 72 MLX4_IB_LSO_HEADER_SPARE = 128, 73 }; 74 75 enum { 76 MLX4_IB_IBOE_ETHERTYPE = 0x8915 77 }; 78 79 struct mlx4_ib_sqp { 80 struct mlx4_ib_qp qp; 81 int pkey_index; 82 u32 qkey; 83 u32 send_psn; 84 struct ib_ud_header ud_header; 85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 86 }; 87 88 enum { 89 MLX4_IB_MIN_SQ_STRIDE = 6, 90 MLX4_IB_CACHE_LINE_SIZE = 64, 91 }; 92 93 enum { 94 MLX4_RAW_QP_MTU = 7, 95 MLX4_RAW_QP_MSGMAX = 31, 96 }; 97 98 static const __be32 mlx4_ib_opcode[] = { 99 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 100 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 101 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 102 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 103 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 104 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 105 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 106 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 107 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 108 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 109 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 110 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 111 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 112 [IB_WR_BIND_MW] = cpu_to_be32( 113 MLX4_OPCODE_BIND_MW), 114 }; 115 116 #ifndef wc_wmb 117 #if defined(__i386__) 118 #define wc_wmb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory") 119 #elif defined(__x86_64__) 120 #define wc_wmb() asm volatile("sfence" ::: "memory") 121 #elif defined(__ia64__) 122 #define wc_wmb() asm volatile("fwb" ::: "memory") 123 #else 124 #define wc_wmb() wmb() 125 #endif 126 #endif 127 128 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 129 { 130 return container_of(mqp, struct mlx4_ib_sqp, qp); 131 } 132 133 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 134 { 135 if (!mlx4_is_master(dev->dev)) 136 return 0; 137 138 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 139 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 140 8 * MLX4_MFUNC_MAX; 141 } 142 143 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 144 { 145 int proxy_sqp = 0; 146 int real_sqp = 0; 147 int i; 148 /* PPF or Native -- real SQP */ 149 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 150 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 151 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 152 if (real_sqp) 153 return 1; 154 /* VF or PF -- proxy SQP */ 155 if (mlx4_is_mfunc(dev->dev)) { 156 for (i = 0; i < dev->dev->caps.num_ports; i++) { 157 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] || 158 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) { 159 proxy_sqp = 1; 160 break; 161 } 162 } 163 } 164 return proxy_sqp; 165 } 166 167 /* used for INIT/CLOSE port logic */ 168 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 169 { 170 int proxy_qp0 = 0; 171 int real_qp0 = 0; 172 int i; 173 /* PPF or Native -- real QP0 */ 174 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 175 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 176 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 177 if (real_qp0) 178 return 1; 179 /* VF or PF -- proxy QP0 */ 180 if (mlx4_is_mfunc(dev->dev)) { 181 for (i = 0; i < dev->dev->caps.num_ports; i++) { 182 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) { 183 proxy_qp0 = 1; 184 break; 185 } 186 } 187 } 188 return proxy_qp0; 189 } 190 191 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 192 { 193 return mlx4_buf_offset(&qp->buf, offset); 194 } 195 196 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 197 { 198 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 199 } 200 201 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 202 { 203 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 204 } 205 206 /* 207 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 208 * first four bytes of every 64 byte chunk with 209 * 0x7FFFFFF | (invalid_ownership_value << 31). 210 * 211 * When the max work request size is less than or equal to the WQE 212 * basic block size, as an optimization, we can stamp all WQEs with 213 * 0xffffffff, and skip the very first chunk of each WQE. 214 */ 215 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 216 { 217 __be32 *wqe; 218 int i; 219 int s; 220 int ind; 221 void *buf; 222 __be32 stamp; 223 struct mlx4_wqe_ctrl_seg *ctrl; 224 225 if (qp->sq_max_wqes_per_wr > 1) { 226 s = roundup(size, 1U << qp->sq.wqe_shift); 227 for (i = 0; i < s; i += 64) { 228 ind = (i >> qp->sq.wqe_shift) + n; 229 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 230 cpu_to_be32(0xffffffff); 231 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 232 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 233 *wqe = stamp; 234 } 235 } else { 236 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 237 s = (ctrl->fence_size & 0x3f) << 4; 238 for (i = 64; i < s; i += 64) { 239 wqe = buf + i; 240 *wqe = cpu_to_be32(0xffffffff); 241 } 242 } 243 } 244 245 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 246 { 247 struct mlx4_wqe_ctrl_seg *ctrl; 248 struct mlx4_wqe_inline_seg *inl; 249 void *wqe; 250 int s; 251 252 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 253 s = sizeof(struct mlx4_wqe_ctrl_seg); 254 255 if (qp->ibqp.qp_type == IB_QPT_UD) { 256 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 257 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 258 memset(dgram, 0, sizeof *dgram); 259 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 260 s += sizeof(struct mlx4_wqe_datagram_seg); 261 } 262 263 /* Pad the remainder of the WQE with an inline data segment. */ 264 if (size > s) { 265 inl = wqe + s; 266 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); 267 } 268 ctrl->srcrb_flags = 0; 269 ctrl->fence_size = size / 16; 270 /* 271 * Make sure descriptor is fully written before setting ownership bit 272 * (because HW can start executing as soon as we do). 273 */ 274 wmb(); 275 276 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 277 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); 278 279 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 280 } 281 282 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 283 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 284 { 285 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 286 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 287 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 288 ind += s; 289 } 290 return ind; 291 } 292 293 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 294 { 295 struct ib_event event; 296 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 297 298 if (type == MLX4_EVENT_TYPE_PATH_MIG) 299 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 300 301 if (ibqp->event_handler) { 302 event.device = ibqp->device; 303 event.element.qp = ibqp; 304 switch (type) { 305 case MLX4_EVENT_TYPE_PATH_MIG: 306 event.event = IB_EVENT_PATH_MIG; 307 break; 308 case MLX4_EVENT_TYPE_COMM_EST: 309 event.event = IB_EVENT_COMM_EST; 310 break; 311 case MLX4_EVENT_TYPE_SQ_DRAINED: 312 event.event = IB_EVENT_SQ_DRAINED; 313 break; 314 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 315 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 316 break; 317 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 318 event.event = IB_EVENT_QP_FATAL; 319 break; 320 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 321 event.event = IB_EVENT_PATH_MIG_ERR; 322 break; 323 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 324 event.event = IB_EVENT_QP_REQ_ERR; 325 break; 326 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 327 event.event = IB_EVENT_QP_ACCESS_ERR; 328 break; 329 default: 330 pr_warn("Unexpected event type %d " 331 "on QP %06x\n", type, qp->qpn); 332 return; 333 } 334 335 ibqp->event_handler(&event, ibqp->qp_context); 336 } 337 } 338 339 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 340 { 341 /* 342 * UD WQEs must have a datagram segment. 343 * RC and UC WQEs might have a remote address segment. 344 * MLX WQEs need two extra inline data segments (for the UD 345 * header and space for the ICRC). 346 */ 347 switch (type) { 348 case MLX4_IB_QPT_UD: 349 return sizeof (struct mlx4_wqe_ctrl_seg) + 350 sizeof (struct mlx4_wqe_datagram_seg) + 351 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 352 case MLX4_IB_QPT_PROXY_SMI_OWNER: 353 case MLX4_IB_QPT_PROXY_SMI: 354 case MLX4_IB_QPT_PROXY_GSI: 355 return sizeof (struct mlx4_wqe_ctrl_seg) + 356 sizeof (struct mlx4_wqe_datagram_seg) + 64; 357 case MLX4_IB_QPT_TUN_SMI_OWNER: 358 case MLX4_IB_QPT_TUN_GSI: 359 return sizeof (struct mlx4_wqe_ctrl_seg) + 360 sizeof (struct mlx4_wqe_datagram_seg); 361 362 case MLX4_IB_QPT_UC: 363 return sizeof (struct mlx4_wqe_ctrl_seg) + 364 sizeof (struct mlx4_wqe_raddr_seg); 365 case MLX4_IB_QPT_RC: 366 return sizeof (struct mlx4_wqe_ctrl_seg) + 367 sizeof (struct mlx4_wqe_masked_atomic_seg) + 368 sizeof (struct mlx4_wqe_raddr_seg); 369 case MLX4_IB_QPT_SMI: 370 case MLX4_IB_QPT_GSI: 371 return sizeof (struct mlx4_wqe_ctrl_seg) + 372 ALIGN(MLX4_IB_UD_HEADER_SIZE + 373 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 374 MLX4_INLINE_ALIGN) * 375 sizeof (struct mlx4_wqe_inline_seg), 376 sizeof (struct mlx4_wqe_data_seg)) + 377 ALIGN(4 + 378 sizeof (struct mlx4_wqe_inline_seg), 379 sizeof (struct mlx4_wqe_data_seg)); 380 default: 381 return sizeof (struct mlx4_wqe_ctrl_seg); 382 } 383 } 384 385 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 386 int is_user, int has_rq, struct mlx4_ib_qp *qp) 387 { 388 /* Sanity check RQ size before proceeding */ 389 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 390 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 391 return -EINVAL; 392 393 if (!has_rq) { 394 if (cap->max_recv_wr) 395 return -EINVAL; 396 397 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 398 } else { 399 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 400 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) 401 return -EINVAL; 402 403 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 404 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 405 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); 406 } 407 408 /* leave userspace return values as they were, so as not to break ABI */ 409 if (is_user) { 410 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 411 cap->max_recv_sge = qp->rq.max_gs; 412 } else { 413 cap->max_recv_wr = qp->rq.max_post = 414 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 415 cap->max_recv_sge = min(qp->rq.max_gs, 416 min(dev->dev->caps.max_sq_sg, 417 dev->dev->caps.max_rq_sg)); 418 } 419 420 return 0; 421 } 422 423 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 424 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 425 { 426 int s; 427 428 /* Sanity check SQ size before proceeding */ 429 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 430 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 431 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 432 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 433 return -EINVAL; 434 435 /* 436 * For MLX transport we need 2 extra S/G entries: 437 * one for the header and one for the checksum at the end 438 */ 439 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 440 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 441 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 442 return -EINVAL; 443 444 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 445 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 446 send_wqe_overhead(type, qp->flags); 447 448 if (s > dev->dev->caps.max_sq_desc_sz) 449 return -EINVAL; 450 451 /* 452 * Hermon supports shrinking WQEs, such that a single work 453 * request can include multiple units of 1 << wqe_shift. This 454 * way, work requests can differ in size, and do not have to 455 * be a power of 2 in size, saving memory and speeding up send 456 * WR posting. Unfortunately, if we do this then the 457 * wqe_index field in CQEs can't be used to look up the WR ID 458 * anymore, so we do this only if selective signaling is off. 459 * 460 * Further, on 32-bit platforms, we can't use vmap() to make 461 * the QP buffer virtually contiguous. Thus we have to use 462 * constant-sized WRs to make sure a WR is always fully within 463 * a single page-sized chunk. 464 * 465 * Finally, we use NOP work requests to pad the end of the 466 * work queue, to avoid wrap-around in the middle of WR. We 467 * set NEC bit to avoid getting completions with error for 468 * these NOP WRs, but since NEC is only supported starting 469 * with firmware 2.2.232, we use constant-sized WRs for older 470 * firmware. 471 * 472 * And, since MLX QPs only support SEND, we use constant-sized 473 * WRs in this case. 474 * 475 * We look for the smallest value of wqe_shift such that the 476 * resulting number of wqes does not exceed device 477 * capabilities. 478 * 479 * We set WQE size to at least 64 bytes, this way stamping 480 * invalidates each WQE. 481 */ 482 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 483 qp->sq_signal_bits && BITS_PER_LONG == 64 && 484 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 485 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 486 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 487 qp->sq.wqe_shift = ilog2(64); 488 else 489 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 490 491 for (;;) { 492 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 493 494 /* 495 * We need to leave 2 KB + 1 WR of headroom in the SQ to 496 * allow HW to prefetch. 497 */ 498 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 499 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 500 qp->sq_max_wqes_per_wr + 501 qp->sq_spare_wqes); 502 503 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 504 break; 505 506 if (qp->sq_max_wqes_per_wr <= 1) 507 return -EINVAL; 508 509 ++qp->sq.wqe_shift; 510 } 511 512 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 513 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 514 send_wqe_overhead(type, qp->flags)) / 515 sizeof (struct mlx4_wqe_data_seg); 516 517 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 518 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 519 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 520 qp->rq.offset = 0; 521 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 522 } else { 523 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 524 qp->sq.offset = 0; 525 } 526 527 cap->max_send_wr = qp->sq.max_post = 528 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 529 cap->max_send_sge = min(qp->sq.max_gs, 530 min(dev->dev->caps.max_sq_sg, 531 dev->dev->caps.max_rq_sg)); 532 qp->max_inline_data = cap->max_inline_data; 533 534 return 0; 535 } 536 537 static int set_user_sq_size(struct mlx4_ib_dev *dev, 538 struct mlx4_ib_qp *qp, 539 struct mlx4_ib_create_qp *ucmd) 540 { 541 /* Sanity check SQ size before proceeding */ 542 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 543 ucmd->log_sq_stride > 544 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 545 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 546 return -EINVAL; 547 548 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 549 qp->sq.wqe_shift = ucmd->log_sq_stride; 550 551 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 552 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 553 554 return 0; 555 } 556 557 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 558 { 559 int i; 560 561 qp->sqp_proxy_rcv = 562 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt, 563 GFP_KERNEL); 564 if (!qp->sqp_proxy_rcv) 565 return -ENOMEM; 566 for (i = 0; i < qp->rq.wqe_cnt; i++) { 567 qp->sqp_proxy_rcv[i].addr = 568 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 569 GFP_KERNEL); 570 if (!qp->sqp_proxy_rcv[i].addr) 571 goto err; 572 qp->sqp_proxy_rcv[i].map = 573 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 574 sizeof (struct mlx4_ib_proxy_sqp_hdr), 575 DMA_FROM_DEVICE); 576 if (unlikely(ib_dma_mapping_error(dev, 577 qp->sqp_proxy_rcv[i].map))) { 578 pr_warn("ib_dma_map_single failed\n"); 579 kfree(qp->sqp_proxy_rcv[i].addr); 580 goto err; 581 } 582 } 583 return 0; 584 585 err: 586 while (i > 0) { 587 --i; 588 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 589 sizeof (struct mlx4_ib_proxy_sqp_hdr), 590 DMA_FROM_DEVICE); 591 kfree(qp->sqp_proxy_rcv[i].addr); 592 } 593 kfree(qp->sqp_proxy_rcv); 594 qp->sqp_proxy_rcv = NULL; 595 return -ENOMEM; 596 } 597 598 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 599 { 600 int i; 601 602 for (i = 0; i < qp->rq.wqe_cnt; i++) { 603 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 604 sizeof (struct mlx4_ib_proxy_sqp_hdr), 605 DMA_FROM_DEVICE); 606 kfree(qp->sqp_proxy_rcv[i].addr); 607 } 608 kfree(qp->sqp_proxy_rcv); 609 } 610 611 static int init_qpg_parent(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *pqp, 612 struct ib_qp_init_attr *attr, int *qpn) 613 { 614 struct mlx4_ib_qpg_data *qpg_data; 615 int tss_num, rss_num; 616 int tss_align_num, rss_align_num; 617 int tss_base, rss_base = 0; 618 int err; 619 620 /* Parent is part of the TSS range (in SW TSS ARP is sent via parent) */ 621 tss_num = 1 + attr->parent_attrib.tss_child_count; 622 tss_align_num = roundup_pow_of_two(tss_num); 623 rss_num = attr->parent_attrib.rss_child_count; 624 rss_align_num = roundup_pow_of_two(rss_num); 625 626 if (rss_num > 1) { 627 /* RSS is requested */ 628 if (!(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS)) 629 return -ENOSYS; 630 if (rss_align_num > dev->dev->caps.max_rss_tbl_sz) 631 return -EINVAL; 632 /* We must work with power of two */ 633 attr->parent_attrib.rss_child_count = rss_align_num; 634 } 635 636 qpg_data = kzalloc(sizeof *qpg_data, GFP_KERNEL); 637 if (!qpg_data) 638 return -ENOMEM; 639 640 if(pqp->flags & MLX4_IB_QP_NETIF) 641 err = mlx4_ib_steer_qp_alloc(dev, tss_align_num, &tss_base); 642 else 643 err = mlx4_qp_reserve_range(dev->dev, tss_align_num, 644 tss_align_num, &tss_base, MLX4_RESERVE_BF_QP); 645 if (err) 646 goto err1; 647 648 if (tss_num > 1) { 649 u32 alloc = BITS_TO_LONGS(tss_align_num) * sizeof(long); 650 qpg_data->tss_bitmap = kzalloc(alloc, GFP_KERNEL); 651 if (qpg_data->tss_bitmap == NULL) { 652 err = -ENOMEM; 653 goto err2; 654 } 655 bitmap_fill(qpg_data->tss_bitmap, tss_num); 656 /* Note parent takes first index */ 657 clear_bit(0, qpg_data->tss_bitmap); 658 } 659 660 if (rss_num > 1) { 661 u32 alloc = BITS_TO_LONGS(rss_align_num) * sizeof(long); 662 err = mlx4_qp_reserve_range(dev->dev, rss_align_num, 663 1, &rss_base, 0); 664 if (err) 665 goto err3; 666 qpg_data->rss_bitmap = kzalloc(alloc, GFP_KERNEL); 667 if (qpg_data->rss_bitmap == NULL) { 668 err = -ENOMEM; 669 goto err4; 670 } 671 bitmap_fill(qpg_data->rss_bitmap, rss_align_num); 672 } 673 674 qpg_data->tss_child_count = attr->parent_attrib.tss_child_count; 675 qpg_data->rss_child_count = attr->parent_attrib.rss_child_count; 676 qpg_data->qpg_parent = pqp; 677 qpg_data->qpg_tss_mask_sz = ilog2(tss_align_num); 678 qpg_data->tss_qpn_base = tss_base; 679 qpg_data->rss_qpn_base = rss_base; 680 681 pqp->qpg_data = qpg_data; 682 *qpn = tss_base; 683 684 return 0; 685 686 err4: 687 mlx4_qp_release_range(dev->dev, rss_base, rss_align_num); 688 689 err3: 690 if (tss_num > 1) 691 kfree(qpg_data->tss_bitmap); 692 693 err2: 694 if(pqp->flags & MLX4_IB_QP_NETIF) 695 mlx4_ib_steer_qp_free(dev, tss_base, tss_align_num); 696 else 697 mlx4_qp_release_range(dev->dev, tss_base, tss_align_num); 698 699 err1: 700 kfree(qpg_data); 701 return err; 702 } 703 704 static void free_qpg_parent(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *pqp) 705 { 706 struct mlx4_ib_qpg_data *qpg_data = pqp->qpg_data; 707 int align_num; 708 709 if (qpg_data->tss_child_count > 1) 710 kfree(qpg_data->tss_bitmap); 711 712 align_num = roundup_pow_of_two(1 + qpg_data->tss_child_count); 713 if(pqp->flags & MLX4_IB_QP_NETIF) 714 mlx4_ib_steer_qp_free(dev, qpg_data->tss_qpn_base, align_num); 715 else 716 mlx4_qp_release_range(dev->dev, qpg_data->tss_qpn_base, align_num); 717 718 if (qpg_data->rss_child_count > 1) { 719 kfree(qpg_data->rss_bitmap); 720 align_num = roundup_pow_of_two(qpg_data->rss_child_count); 721 mlx4_qp_release_range(dev->dev, qpg_data->rss_qpn_base, 722 align_num); 723 } 724 725 kfree(qpg_data); 726 } 727 728 static int alloc_qpg_qpn(struct ib_qp_init_attr *init_attr, 729 struct mlx4_ib_qp *pqp, int *qpn) 730 { 731 struct mlx4_ib_qp *mqp = to_mqp(init_attr->qpg_parent); 732 struct mlx4_ib_qpg_data *qpg_data = mqp->qpg_data; 733 u32 idx, old; 734 735 switch (init_attr->qpg_type) { 736 case IB_QPG_CHILD_TX: 737 if (qpg_data->tss_child_count == 0) 738 return -EINVAL; 739 do { 740 /* Parent took index 0 */ 741 idx = find_first_bit(qpg_data->tss_bitmap, 742 qpg_data->tss_child_count + 1); 743 if (idx >= qpg_data->tss_child_count + 1) 744 return -ENOMEM; 745 old = test_and_clear_bit(idx, qpg_data->tss_bitmap); 746 } while (old == 0); 747 idx += qpg_data->tss_qpn_base; 748 break; 749 case IB_QPG_CHILD_RX: 750 if (qpg_data->rss_child_count == 0) 751 return -EINVAL; 752 do { 753 idx = find_first_bit(qpg_data->rss_bitmap, 754 qpg_data->rss_child_count); 755 if (idx >= qpg_data->rss_child_count) 756 return -ENOMEM; 757 old = test_and_clear_bit(idx, qpg_data->rss_bitmap); 758 } while (old == 0); 759 idx += qpg_data->rss_qpn_base; 760 break; 761 default: 762 return -EINVAL; 763 } 764 765 pqp->qpg_data = qpg_data; 766 *qpn = idx; 767 768 return 0; 769 } 770 771 static void free_qpg_qpn(struct mlx4_ib_qp *mqp, int qpn) 772 { 773 struct mlx4_ib_qpg_data *qpg_data = mqp->qpg_data; 774 775 switch (mqp->qpg_type) { 776 case IB_QPG_CHILD_TX: 777 /* Do range check */ 778 qpn -= qpg_data->tss_qpn_base; 779 set_bit(qpn, qpg_data->tss_bitmap); 780 break; 781 case IB_QPG_CHILD_RX: 782 qpn -= qpg_data->rss_qpn_base; 783 set_bit(qpn, qpg_data->rss_bitmap); 784 break; 785 default: 786 /* error */ 787 pr_warn("wrong qpg type (%d)\n", mqp->qpg_type); 788 break; 789 } 790 } 791 792 static int alloc_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 793 struct ib_qp_init_attr *attr, int *qpn) 794 { 795 int err = 0; 796 797 switch (attr->qpg_type) { 798 case IB_QPG_NONE: 799 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 800 * otherwise, the WQE BlueFlame setup flow wrongly causes 801 * VLAN insertion. */ 802 if (attr->qp_type == IB_QPT_RAW_PACKET) { 803 err = mlx4_qp_reserve_range(dev->dev, 1, 1, qpn, 804 MLX4_RESERVE_BF_QP); 805 } else { 806 if(qp->flags & MLX4_IB_QP_NETIF) 807 err = mlx4_ib_steer_qp_alloc(dev, 1, qpn); 808 else 809 err = mlx4_qp_reserve_range(dev->dev, 1, 1, qpn, 0); 810 } 811 break; 812 case IB_QPG_PARENT: 813 err = init_qpg_parent(dev, qp, attr, qpn); 814 break; 815 case IB_QPG_CHILD_TX: 816 case IB_QPG_CHILD_RX: 817 err = alloc_qpg_qpn(attr, qp, qpn); 818 break; 819 default: 820 qp->qpg_type = IB_QPG_NONE; 821 err = -EINVAL; 822 break; 823 } 824 if (err) 825 return err; 826 qp->qpg_type = attr->qpg_type; 827 return 0; 828 } 829 830 static void free_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 831 enum ib_qpg_type qpg_type, int qpn) 832 { 833 switch (qpg_type) { 834 case IB_QPG_NONE: 835 if (qp->flags & MLX4_IB_QP_NETIF) 836 mlx4_ib_steer_qp_free(dev, qpn, 1); 837 else 838 mlx4_qp_release_range(dev->dev, qpn, 1); 839 break; 840 case IB_QPG_PARENT: 841 free_qpg_parent(dev, qp); 842 break; 843 case IB_QPG_CHILD_TX: 844 case IB_QPG_CHILD_RX: 845 free_qpg_qpn(qp, qpn); 846 break; 847 default: 848 break; 849 } 850 } 851 852 /* Revert allocation on create_qp_common */ 853 static void unalloc_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 854 struct ib_qp_init_attr *attr, int qpn) 855 { 856 free_qpn_common(dev, qp, attr->qpg_type, qpn); 857 } 858 859 static void release_qpn_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 860 { 861 free_qpn_common(dev, qp, qp->qpg_type, qp->mqp.qpn); 862 } 863 864 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 865 struct ib_qp_init_attr *init_attr, 866 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp) 867 { 868 int qpn; 869 int err; 870 struct mlx4_ib_sqp *sqp; 871 struct mlx4_ib_qp *qp; 872 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 873 874 /* When tunneling special qps, we use a plain UD qp */ 875 if (sqpn) { 876 if (mlx4_is_mfunc(dev->dev) && 877 (!mlx4_is_master(dev->dev) || 878 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 879 if (init_attr->qp_type == IB_QPT_GSI) 880 qp_type = MLX4_IB_QPT_PROXY_GSI; 881 else if (mlx4_is_master(dev->dev)) 882 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 883 else 884 qp_type = MLX4_IB_QPT_PROXY_SMI; 885 } 886 qpn = sqpn; 887 /* add extra sg entry for tunneling */ 888 init_attr->cap.max_recv_sge++; 889 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 890 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 891 container_of(init_attr, 892 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 893 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 894 tnl_init->proxy_qp_type != IB_QPT_GSI) || 895 !mlx4_is_master(dev->dev)) 896 return -EINVAL; 897 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 898 qp_type = MLX4_IB_QPT_TUN_GSI; 899 else if (tnl_init->slave == mlx4_master_func_num(dev->dev)) 900 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 901 else 902 qp_type = MLX4_IB_QPT_TUN_SMI; 903 /* we are definitely in the PPF here, since we are creating 904 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 905 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 906 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 907 sqpn = qpn; 908 } 909 910 if (!*caller_qp) { 911 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 912 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 913 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 914 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL); 915 if (!sqp) 916 return -ENOMEM; 917 qp = &sqp->qp; 918 qp->pri.vid = qp->alt.vid = 0xFFFF; 919 } else { 920 qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL); 921 if (!qp) 922 return -ENOMEM; 923 qp->pri.vid = qp->alt.vid = 0xFFFF; 924 } 925 } else 926 qp = *caller_qp; 927 928 qp->mlx4_ib_qp_type = qp_type; 929 930 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 931 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 932 933 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 934 qp->flags |= MLX4_IB_QP_LSO; 935 936 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 937 if (dev->dev->caps.steering_mode == 938 MLX4_STEERING_MODE_DEVICE_MANAGED && 939 !mlx4_is_mfunc(dev->dev)) 940 qp->flags |= MLX4_IB_QP_NETIF; 941 else { 942 err = -EINVAL; 943 goto err; 944 } 945 } 946 947 mutex_init(&qp->mutex); 948 spin_lock_init(&qp->sq.lock); 949 spin_lock_init(&qp->rq.lock); 950 INIT_LIST_HEAD(&qp->gid_list); 951 INIT_LIST_HEAD(&qp->steering_rules); 952 INIT_LIST_HEAD(&qp->rules_list); 953 954 qp->state = IB_QPS_RESET; 955 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 956 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 957 958 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, mlx4_ib_qp_has_rq(init_attr), qp); 959 if (err) 960 goto err; 961 962 if (pd->uobject) { 963 struct mlx4_ib_create_qp ucmd; 964 int shift; 965 int n; 966 967 if (!udata || ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 968 err = -EFAULT; 969 goto err; 970 } 971 972 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 973 qp->flags |= MLX4_IB_QP_CAP_CROSS_CHANNEL; 974 975 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 976 qp->flags |= MLX4_IB_QP_CAP_MANAGED_SEND; 977 978 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 979 qp->flags |= MLX4_IB_QP_CAP_MANAGED_RECV; 980 981 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 982 983 err = set_user_sq_size(dev, qp, &ucmd); 984 if (err) 985 goto err; 986 987 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 988 qp->buf_size, 0, 0); 989 if (IS_ERR(qp->umem)) { 990 err = PTR_ERR(qp->umem); 991 goto err; 992 } 993 994 n = ib_umem_page_count(qp->umem); 995 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 996 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 997 998 if (err) 999 goto err_buf; 1000 1001 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1002 if (err) 1003 goto err_mtt; 1004 1005 if (mlx4_ib_qp_has_rq(init_attr)) { 1006 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 1007 ucmd.db_addr, &qp->db); 1008 if (err) 1009 goto err_mtt; 1010 } 1011 } else { 1012 qp->sq_no_prefetch = 0; 1013 1014 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1015 if (err) 1016 goto err; 1017 1018 if (mlx4_ib_qp_has_rq(init_attr)) { 1019 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1020 if (err) 1021 goto err; 1022 1023 *qp->db.db = 0; 1024 } 1025 1026 if (qp->max_inline_data) { 1027 err = mlx4_bf_alloc(dev->dev, &qp->bf, 0); 1028 if (err) { 1029 pr_debug("failed to allocate blue flame" 1030 " register (%d)", err); 1031 qp->bf.uar = &dev->priv_uar; 1032 } 1033 } else 1034 qp->bf.uar = &dev->priv_uar; 1035 1036 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) { 1037 err = -ENOMEM; 1038 goto err_db; 1039 } 1040 1041 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1042 &qp->mtt); 1043 if (err) 1044 goto err_buf; 1045 1046 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1047 if (err) 1048 goto err_mtt; 1049 1050 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL); 1051 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL); 1052 1053 if (!qp->sq.wrid || !qp->rq.wrid) { 1054 err = -ENOMEM; 1055 goto err_wrid; 1056 } 1057 } 1058 1059 if (sqpn) { 1060 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1061 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1062 if (alloc_proxy_bufs(pd->device, qp)) { 1063 err = -ENOMEM; 1064 goto err_wrid; 1065 } 1066 } 1067 } else { 1068 err = alloc_qpn_common(dev, qp, init_attr, &qpn); 1069 if (err) 1070 goto err_proxy; 1071 } 1072 1073 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1074 if (err) 1075 goto err_qpn; 1076 1077 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1078 qp->mqp.qpn |= (1 << 23); 1079 1080 /* 1081 * Hardware wants QPN written in big-endian order (after 1082 * shifting) for send doorbell. Precompute this value to save 1083 * a little bit when posting sends. 1084 */ 1085 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1086 1087 qp->mqp.event = mlx4_ib_qp_event; 1088 if (!*caller_qp) 1089 *caller_qp = qp; 1090 return 0; 1091 1092 err_qpn: 1093 unalloc_qpn_common(dev, qp, init_attr, qpn); 1094 1095 err_proxy: 1096 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1097 free_proxy_bufs(pd->device, qp); 1098 err_wrid: 1099 if (pd->uobject) { 1100 if (mlx4_ib_qp_has_rq(init_attr)) 1101 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 1102 } else { 1103 kfree(qp->sq.wrid); 1104 kfree(qp->rq.wrid); 1105 } 1106 1107 err_mtt: 1108 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1109 1110 err_buf: 1111 if (pd->uobject) 1112 ib_umem_release(qp->umem); 1113 else 1114 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1115 1116 err_db: 1117 if (!pd->uobject && mlx4_ib_qp_has_rq(init_attr)) 1118 mlx4_db_free(dev->dev, &qp->db); 1119 1120 if (qp->max_inline_data) 1121 mlx4_bf_free(dev->dev, &qp->bf); 1122 1123 err: 1124 if (!*caller_qp) 1125 kfree(qp); 1126 return err; 1127 } 1128 1129 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1130 { 1131 switch (state) { 1132 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1133 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1134 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1135 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1136 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1137 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1138 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1139 default: return -1; 1140 } 1141 } 1142 1143 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1144 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1145 { 1146 if (send_cq == recv_cq) { 1147 spin_lock_irq(&send_cq->lock); 1148 __acquire(&recv_cq->lock); 1149 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1150 spin_lock_irq(&send_cq->lock); 1151 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1152 } else { 1153 spin_lock_irq(&recv_cq->lock); 1154 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1155 } 1156 } 1157 1158 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1159 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1160 { 1161 if (send_cq == recv_cq) { 1162 __release(&recv_cq->lock); 1163 spin_unlock_irq(&send_cq->lock); 1164 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1165 spin_unlock(&recv_cq->lock); 1166 spin_unlock_irq(&send_cq->lock); 1167 } else { 1168 spin_unlock(&send_cq->lock); 1169 spin_unlock_irq(&recv_cq->lock); 1170 } 1171 } 1172 1173 static void del_gid_entries(struct mlx4_ib_qp *qp) 1174 { 1175 struct mlx4_ib_gid_entry *ge, *tmp; 1176 1177 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1178 list_del(&ge->list); 1179 kfree(ge); 1180 } 1181 } 1182 1183 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1184 { 1185 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1186 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1187 else 1188 return to_mpd(qp->ibqp.pd); 1189 } 1190 1191 static void get_cqs(struct mlx4_ib_qp *qp, 1192 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1193 { 1194 switch (qp->ibqp.qp_type) { 1195 case IB_QPT_XRC_TGT: 1196 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1197 *recv_cq = *send_cq; 1198 break; 1199 case IB_QPT_XRC_INI: 1200 *send_cq = to_mcq(qp->ibqp.send_cq); 1201 *recv_cq = *send_cq; 1202 break; 1203 default: 1204 *send_cq = to_mcq(qp->ibqp.send_cq); 1205 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1206 break; 1207 } 1208 } 1209 1210 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1211 int is_user) 1212 { 1213 struct mlx4_ib_cq *send_cq, *recv_cq; 1214 1215 if (qp->state != IB_QPS_RESET) { 1216 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1217 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1218 pr_warn("modify QP %06x to RESET failed.\n", 1219 qp->mqp.qpn); 1220 if (qp->pri.smac) { 1221 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1222 qp->pri.smac = 0; 1223 } 1224 if (qp->alt.smac) { 1225 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1226 qp->alt.smac = 0; 1227 } 1228 if (qp->pri.vid < 0x1000) { 1229 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1230 qp->pri.vid = 0xFFFF; 1231 qp->pri.candidate_vid = 0xFFFF; 1232 qp->pri.update_vid = 0; 1233 } 1234 if (qp->alt.vid < 0x1000) { 1235 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1236 qp->alt.vid = 0xFFFF; 1237 qp->alt.candidate_vid = 0xFFFF; 1238 qp->alt.update_vid = 0; 1239 } 1240 } 1241 1242 get_cqs(qp, &send_cq, &recv_cq); 1243 1244 mlx4_ib_lock_cqs(send_cq, recv_cq); 1245 1246 if (!is_user) { 1247 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1248 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1249 if (send_cq != recv_cq) 1250 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1251 } 1252 1253 mlx4_qp_remove(dev->dev, &qp->mqp); 1254 1255 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1256 1257 mlx4_qp_free(dev->dev, &qp->mqp); 1258 1259 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) 1260 release_qpn_common(dev, qp); 1261 1262 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1263 1264 if (is_user) { 1265 if (qp->rq.wqe_cnt) 1266 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context), 1267 &qp->db); 1268 ib_umem_release(qp->umem); 1269 } else { 1270 kfree(qp->sq.wrid); 1271 kfree(qp->rq.wrid); 1272 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1273 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1274 free_proxy_bufs(&dev->ib_dev, qp); 1275 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1276 if (qp->max_inline_data) 1277 mlx4_bf_free(dev->dev, &qp->bf); 1278 1279 if (qp->rq.wqe_cnt) 1280 mlx4_db_free(dev->dev, &qp->db); 1281 } 1282 1283 del_gid_entries(qp); 1284 } 1285 1286 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1287 { 1288 /* Native or PPF */ 1289 if (!mlx4_is_mfunc(dev->dev) || 1290 (mlx4_is_master(dev->dev) && 1291 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1292 return dev->dev->phys_caps.base_sqpn + 1293 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1294 attr->port_num - 1; 1295 } 1296 /* PF or VF -- creating proxies */ 1297 if (attr->qp_type == IB_QPT_SMI) 1298 return dev->dev->caps.qp0_proxy[attr->port_num - 1]; 1299 else 1300 return dev->dev->caps.qp1_proxy[attr->port_num - 1]; 1301 } 1302 1303 static int check_qpg_attr(struct mlx4_ib_dev *dev, 1304 struct ib_qp_init_attr *attr) 1305 { 1306 if (attr->qpg_type == IB_QPG_NONE) 1307 return 0; 1308 1309 if (attr->qp_type != IB_QPT_UD && 1310 attr->qp_type != IB_QPT_RAW_PACKET) 1311 return -EINVAL; 1312 1313 if (attr->qpg_type == IB_QPG_PARENT) { 1314 if (attr->parent_attrib.tss_child_count == 1) 1315 return -EINVAL; /* Doesn't make sense */ 1316 if (attr->parent_attrib.rss_child_count == 1) 1317 return -EINVAL; /* Doesn't make sense */ 1318 if ((attr->parent_attrib.tss_child_count == 0) && 1319 (attr->parent_attrib.rss_child_count == 0)) 1320 /* Should be called with IP_QPG_NONE */ 1321 return -EINVAL; 1322 if (attr->parent_attrib.rss_child_count > 1) { 1323 int rss_align_num; 1324 if (!(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS)) 1325 return -ENOSYS; 1326 rss_align_num = roundup_pow_of_two( 1327 attr->parent_attrib.rss_child_count); 1328 if (rss_align_num > dev->dev->caps.max_rss_tbl_sz) 1329 return -EINVAL; 1330 } 1331 } else { 1332 struct mlx4_ib_qpg_data *qpg_data; 1333 if (attr->qpg_parent == NULL) 1334 return -EINVAL; 1335 if (IS_ERR(attr->qpg_parent)) 1336 return -EINVAL; 1337 qpg_data = to_mqp(attr->qpg_parent)->qpg_data; 1338 if (qpg_data == NULL) 1339 return -EINVAL; 1340 if (attr->qpg_type == IB_QPG_CHILD_TX && 1341 !qpg_data->tss_child_count) 1342 return -EINVAL; 1343 if (attr->qpg_type == IB_QPG_CHILD_RX && 1344 !qpg_data->rss_child_count) 1345 return -EINVAL; 1346 } 1347 return 0; 1348 } 1349 1350 #define RESERVED_FLAGS_MASK ((((unsigned int)IB_QP_CREATE_RESERVED_END - 1) | IB_QP_CREATE_RESERVED_END) \ 1351 & ~(IB_QP_CREATE_RESERVED_START - 1)) 1352 1353 static enum mlx4_ib_qp_flags to_mlx4_ib_qp_flags(enum ib_qp_create_flags ib_qp_flags) 1354 { 1355 enum mlx4_ib_qp_flags mlx4_ib_qp_flags = 0; 1356 1357 if (ib_qp_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1358 mlx4_ib_qp_flags |= MLX4_IB_QP_LSO; 1359 1360 if (ib_qp_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1361 mlx4_ib_qp_flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1362 1363 if (ib_qp_flags & IB_QP_CREATE_NETIF_QP) 1364 mlx4_ib_qp_flags |= MLX4_IB_QP_NETIF; 1365 1366 if (ib_qp_flags & IB_QP_CREATE_CROSS_CHANNEL) 1367 mlx4_ib_qp_flags |= MLX4_IB_QP_CAP_CROSS_CHANNEL; 1368 1369 if (ib_qp_flags & IB_QP_CREATE_MANAGED_SEND) 1370 mlx4_ib_qp_flags |= MLX4_IB_QP_CAP_MANAGED_SEND; 1371 1372 if (ib_qp_flags & IB_QP_CREATE_MANAGED_RECV) 1373 mlx4_ib_qp_flags |= MLX4_IB_QP_CAP_MANAGED_RECV; 1374 1375 /* reserved flags */ 1376 mlx4_ib_qp_flags |= (ib_qp_flags & RESERVED_FLAGS_MASK); 1377 1378 return mlx4_ib_qp_flags; 1379 } 1380 1381 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1382 struct ib_qp_init_attr *init_attr, 1383 struct ib_udata *udata) 1384 { 1385 struct mlx4_ib_qp *qp = NULL; 1386 int err; 1387 u16 xrcdn = 0; 1388 enum mlx4_ib_qp_flags mlx4_qp_flags = to_mlx4_ib_qp_flags(init_attr->create_flags); 1389 struct ib_device *device; 1390 1391 /* see ib_core::ib_create_qp same handling */ 1392 device = pd ? pd->device : init_attr->xrcd->device; 1393 /* 1394 * We only support LSO, vendor flag1, and multicast loopback blocking, 1395 * and only for kernel UD QPs. 1396 */ 1397 if (mlx4_qp_flags & ~(MLX4_IB_QP_LSO | 1398 MLX4_IB_QP_CAP_CROSS_CHANNEL | 1399 MLX4_IB_QP_CAP_MANAGED_SEND | 1400 MLX4_IB_QP_CAP_MANAGED_RECV | 1401 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1402 MLX4_IB_SRIOV_TUNNEL_QP | MLX4_IB_SRIOV_SQP | 1403 MLX4_IB_QP_NETIF)) 1404 return ERR_PTR(-EINVAL); 1405 1406 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1407 if (init_attr->qp_type != IB_QPT_UD) 1408 return ERR_PTR(-EINVAL); 1409 } 1410 1411 if ((mlx4_qp_flags & 1412 (MLX4_IB_QP_CAP_CROSS_CHANNEL | 1413 MLX4_IB_QP_CAP_MANAGED_SEND | 1414 MLX4_IB_QP_CAP_MANAGED_RECV)) && 1415 !(to_mdev(device)->dev->caps.flags & 1416 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL)) { 1417 pr_debug("%s Does not support cross-channel operations\n", 1418 to_mdev(device)->ib_dev.name); 1419 return ERR_PTR(-EINVAL); 1420 } 1421 1422 if ((init_attr->create_flags & 1423 ~(IB_QP_CREATE_CROSS_CHANNEL | 1424 IB_QP_CREATE_MANAGED_SEND | 1425 IB_QP_CREATE_MANAGED_RECV)) && 1426 (((mlx4_qp_flags & ~MLX4_IB_SRIOV_SQP) && 1427 init_attr->qp_type != IB_QPT_UD) || 1428 ((mlx4_qp_flags & MLX4_IB_SRIOV_SQP) && 1429 init_attr->qp_type > IB_QPT_GSI))) 1430 return ERR_PTR(-EINVAL); 1431 1432 err = check_qpg_attr(to_mdev(device), init_attr); 1433 if (err) 1434 return ERR_PTR(err); 1435 1436 switch (init_attr->qp_type) { 1437 case IB_QPT_XRC_TGT: 1438 pd = to_mxrcd(init_attr->xrcd)->pd; 1439 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1440 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1441 /* fall through */ 1442 case IB_QPT_XRC_INI: 1443 if (!(to_mdev(device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1444 return ERR_PTR(-ENOSYS); 1445 init_attr->recv_cq = init_attr->send_cq; 1446 /* fall through */ 1447 case IB_QPT_RC: 1448 case IB_QPT_UC: 1449 case IB_QPT_RAW_PACKET: 1450 qp = kzalloc(sizeof *qp, GFP_KERNEL); 1451 if (!qp) 1452 return ERR_PTR(-ENOMEM); 1453 qp->pri.vid = qp->alt.vid = 0xFFFF; 1454 /* fall through */ 1455 case IB_QPT_UD: 1456 { 1457 err = create_qp_common(to_mdev(device), pd, init_attr, udata, 0, &qp); 1458 if (err) { 1459 kfree(qp); 1460 return ERR_PTR(err); 1461 } 1462 1463 qp->ibqp.qp_num = qp->mqp.qpn; 1464 qp->xrcdn = xrcdn; 1465 1466 break; 1467 } 1468 case IB_QPT_SMI: 1469 case IB_QPT_GSI: 1470 { 1471 /* Userspace is not allowed to create special QPs: */ 1472 if (udata) 1473 return ERR_PTR(-EINVAL); 1474 1475 err = create_qp_common(to_mdev(device), pd, init_attr, udata, 1476 get_sqp_num(to_mdev(device), init_attr), 1477 &qp); 1478 if (err) 1479 return ERR_PTR(err); 1480 1481 qp->port = init_attr->port_num; 1482 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1; 1483 1484 break; 1485 } 1486 default: 1487 /* Don't support raw QPs */ 1488 return ERR_PTR(-EINVAL); 1489 } 1490 1491 return &qp->ibqp; 1492 } 1493 1494 int mlx4_ib_destroy_qp(struct ib_qp *qp) 1495 { 1496 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1497 struct mlx4_ib_qp *mqp = to_mqp(qp); 1498 struct mlx4_ib_pd *pd; 1499 1500 if (is_qp0(dev, mqp)) 1501 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1502 1503 pd = get_pd(mqp); 1504 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject); 1505 1506 if (is_sqp(dev, mqp)) 1507 kfree(to_msqp(mqp)); 1508 else 1509 kfree(mqp); 1510 1511 return 0; 1512 } 1513 1514 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1515 { 1516 switch (type) { 1517 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1518 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1519 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1520 case MLX4_IB_QPT_XRC_INI: 1521 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1522 case MLX4_IB_QPT_SMI: 1523 case MLX4_IB_QPT_GSI: 1524 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1525 1526 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1527 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1528 MLX4_QP_ST_MLX : -1); 1529 case MLX4_IB_QPT_PROXY_SMI: 1530 case MLX4_IB_QPT_TUN_SMI: 1531 case MLX4_IB_QPT_PROXY_GSI: 1532 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1533 MLX4_QP_ST_UD : -1); 1534 default: return -1; 1535 } 1536 } 1537 1538 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1539 int attr_mask) 1540 { 1541 u8 dest_rd_atomic; 1542 u32 access_flags; 1543 u32 hw_access_flags = 0; 1544 1545 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1546 dest_rd_atomic = attr->max_dest_rd_atomic; 1547 else 1548 dest_rd_atomic = qp->resp_depth; 1549 1550 if (attr_mask & IB_QP_ACCESS_FLAGS) 1551 access_flags = attr->qp_access_flags; 1552 else 1553 access_flags = qp->atomic_rd_en; 1554 1555 if (!dest_rd_atomic) 1556 access_flags &= IB_ACCESS_REMOTE_WRITE; 1557 1558 if (access_flags & IB_ACCESS_REMOTE_READ) 1559 hw_access_flags |= MLX4_QP_BIT_RRE; 1560 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1561 hw_access_flags |= MLX4_QP_BIT_RAE; 1562 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1563 hw_access_flags |= MLX4_QP_BIT_RWE; 1564 1565 return cpu_to_be32(hw_access_flags); 1566 } 1567 1568 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1569 int attr_mask) 1570 { 1571 if (attr_mask & IB_QP_PKEY_INDEX) 1572 sqp->pkey_index = attr->pkey_index; 1573 if (attr_mask & IB_QP_QKEY) 1574 sqp->qkey = attr->qkey; 1575 if (attr_mask & IB_QP_SQ_PSN) 1576 sqp->send_psn = attr->sq_psn; 1577 } 1578 1579 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1580 { 1581 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1582 } 1583 1584 static int ib_rate_to_mlx4(struct mlx4_ib_dev *dev, u8 rate) 1585 { 1586 if (rate == IB_RATE_PORT_CURRENT) { 1587 return 0; 1588 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 1589 return -EINVAL; 1590 } else { 1591 while (rate != IB_RATE_2_5_GBPS && 1592 !(1 << (rate + MLX4_STAT_RATE_OFFSET) & 1593 dev->dev->caps.stat_rate_support)) 1594 --rate; 1595 } 1596 1597 return rate + MLX4_STAT_RATE_OFFSET; 1598 } 1599 1600 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, 1601 u8 *smac, u16 vlan_id, struct mlx4_ib_qp *qp, 1602 struct mlx4_qp_path *path, u8 port, int is_primary) 1603 { 1604 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) == 1605 IB_LINK_LAYER_ETHERNET; 1606 u16 vlan_tag; 1607 int vidx; 1608 int smac_index; 1609 int err; 1610 u64 u64_mac; 1611 struct mlx4_roce_smac_vlan_info *smac_info; 1612 1613 path->grh_mylmc = ah->src_path_bits & 0x7f; 1614 path->rlid = cpu_to_be16(ah->dlid); 1615 1616 err = ib_rate_to_mlx4(dev, ah->static_rate); 1617 if (err < 0) 1618 return err; 1619 path->static_rate = err; 1620 1621 if (ah->ah_flags & IB_AH_GRH) { 1622 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) { 1623 pr_err("sgid_index (%u) too large. max is %d\n", 1624 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1625 return -1; 1626 } 1627 1628 path->grh_mylmc |= 1 << 7; 1629 path->mgid_index = ah->grh.sgid_index; 1630 path->hop_limit = ah->grh.hop_limit; 1631 path->tclass_flowlabel = 1632 cpu_to_be32((ah->grh.traffic_class << 20) | 1633 (ah->grh.flow_label)); 1634 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1635 } 1636 1637 if (is_eth) { 1638 if (!(ah->ah_flags & IB_AH_GRH)) 1639 return -1; 1640 1641 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1642 ((port - 1) << 6) | ((ah->sl & 7) << 3); 1643 1644 if (is_primary) 1645 smac_info = &qp->pri; 1646 else 1647 smac_info = &qp->alt; 1648 1649 vlan_tag = vlan_id; 1650 if (vlan_tag < 0x1000) { 1651 if (smac_info->vid < 0x1000) { 1652 /* both valid vlan ids */ 1653 if (smac_info->vid != vlan_tag) { 1654 /* different VIDs. unreg old and reg new */ 1655 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1656 if (err) 1657 return err; 1658 smac_info->candidate_vid = vlan_tag; 1659 smac_info->candidate_vlan_index = vidx; 1660 smac_info->candidate_vlan_port = port; 1661 smac_info->update_vid = 1; 1662 path->vlan_index = vidx; 1663 path->fl = 1 << 6; 1664 } else { 1665 path->vlan_index = smac_info->vlan_index; 1666 path->fl = 1 << 6; 1667 } 1668 } else { 1669 /* no current vlan tag in qp */ 1670 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1671 if (err) 1672 return err; 1673 smac_info->candidate_vid = vlan_tag; 1674 smac_info->candidate_vlan_index = vidx; 1675 smac_info->candidate_vlan_port = port; 1676 smac_info->update_vid = 1; 1677 path->vlan_index = vidx; 1678 path->fl = 1 << 6; 1679 } 1680 } else { 1681 /* have current vlan tag. unregister it at modify-qp success */ 1682 if (smac_info->vid < 0x1000) { 1683 smac_info->candidate_vid = 0xFFFF; 1684 smac_info->update_vid = 1; 1685 } 1686 } 1687 1688 1689 /* get smac_index for RoCE use. 1690 * If no smac was yet assigned, register one. 1691 * If one was already assigned, but the new mac differs, 1692 * unregister the old one and register the new one. 1693 */ 1694 u64_mac = mlx4_mac_to_u64(smac); 1695 1696 if (!smac_info->smac || smac_info->smac != u64_mac) { 1697 /* register candidate now, unreg if needed, after success */ 1698 smac_index = mlx4_register_mac(dev->dev, port, u64_mac); 1699 if (smac_index >= 0) { 1700 smac_info->candidate_smac_index = smac_index; 1701 smac_info->candidate_smac = u64_mac; 1702 smac_info->candidate_smac_port = port; 1703 } else 1704 return -EINVAL; 1705 } else 1706 smac_index = smac_info->smac_index; 1707 1708 memcpy(path->dmac, ah->dmac, 6); 1709 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1710 /* put MAC table smac index for IBoE */ 1711 path->grh_mylmc = (u8) (smac_index) | 0x80 ; 1712 1713 } else 1714 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1715 ((port - 1) << 6) | ((ah->sl & 0xf) << 2); 1716 1717 return 0; 1718 } 1719 1720 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1721 { 1722 struct mlx4_ib_gid_entry *ge, *tmp; 1723 1724 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1725 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1726 ge->added = 1; 1727 ge->port = qp->port; 1728 } 1729 } 1730 } 1731 1732 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, const u8 *smac, 1733 struct mlx4_qp_context *context) 1734 { 1735 struct net_device *ndev; 1736 u64 u64_mac; 1737 int smac_index; 1738 1739 1740 ndev = dev->iboe.netdevs[qp->port - 1]; 1741 if (ndev) { 1742 smac = IF_LLADDR(ndev); 1743 u64_mac = mlx4_mac_to_u64(smac); 1744 } else { 1745 u64_mac = dev->dev->caps.def_mac[qp->port]; 1746 } 1747 1748 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1749 if (!qp->pri.smac) { 1750 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1751 if (smac_index >= 0) { 1752 qp->pri.candidate_smac_index = smac_index; 1753 qp->pri.candidate_smac = u64_mac; 1754 qp->pri.candidate_smac_port = qp->port; 1755 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1756 } else 1757 return -ENOENT; 1758 } 1759 return 0; 1760 } 1761 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 1762 const struct ib_qp_attr *attr, int attr_mask, 1763 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1764 { 1765 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1766 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1767 struct mlx4_ib_pd *pd; 1768 struct mlx4_ib_cq *send_cq, *recv_cq; 1769 struct mlx4_qp_context *context; 1770 enum mlx4_qp_optpar optpar = 0; 1771 int sqd_event; 1772 int steer_qp = 0; 1773 int err = -EINVAL; 1774 int is_eth = -1; 1775 1776 context = kzalloc(sizeof *context, GFP_KERNEL); 1777 if (!context) 1778 return -ENOMEM; 1779 1780 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 1781 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 1782 1783 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 1784 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1785 else { 1786 optpar |= MLX4_QP_OPTPAR_PM_STATE; 1787 switch (attr->path_mig_state) { 1788 case IB_MIG_MIGRATED: 1789 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1790 break; 1791 case IB_MIG_REARM: 1792 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 1793 break; 1794 case IB_MIG_ARMED: 1795 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 1796 break; 1797 } 1798 } 1799 1800 if (qp->max_inlr_data) 1801 context->param3 |= cpu_to_be32(1 << 25); 1802 1803 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 1804 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 1805 else if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1806 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 1807 else if (ibqp->qp_type == IB_QPT_UD) { 1808 if (qp->flags & MLX4_IB_QP_LSO) 1809 context->mtu_msgmax = (IB_MTU_4096 << 5) | 1810 ilog2(dev->dev->caps.max_gso_sz); 1811 else 1812 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1813 } else if (attr_mask & IB_QP_PATH_MTU) { 1814 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 1815 pr_err("path MTU (%u) is invalid\n", 1816 attr->path_mtu); 1817 goto out; 1818 } 1819 context->mtu_msgmax = (attr->path_mtu << 5) | 1820 ilog2(dev->dev->caps.max_msg_sz); 1821 } 1822 1823 if (qp->rq.wqe_cnt) 1824 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 1825 context->rq_size_stride |= qp->rq.wqe_shift - 4; 1826 1827 if (qp->sq.wqe_cnt) 1828 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 1829 context->sq_size_stride |= qp->sq.wqe_shift - 4; 1830 1831 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1832 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 1833 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 1834 context->param3 |= cpu_to_be32(1 << 30); 1835 } 1836 1837 if (qp->ibqp.uobject) 1838 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index); 1839 else 1840 context->usr_page = cpu_to_be32(qp->bf.uar->index); 1841 1842 if (attr_mask & IB_QP_DEST_QPN) 1843 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 1844 1845 if (attr_mask & IB_QP_PORT) { 1846 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 1847 !(attr_mask & IB_QP_AV)) { 1848 mlx4_set_sched(&context->pri_path, attr->port_num); 1849 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 1850 } 1851 } 1852 1853 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 1854 if (dev->counters[qp->port - 1].counter_index != -1) { 1855 context->pri_path.counter_index = 1856 dev->counters[qp->port - 1].counter_index; 1857 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 1858 } else { 1859 context->pri_path.counter_index = 0xff; 1860 } 1861 1862 if (qp->flags & MLX4_IB_QP_NETIF && 1863 (qp->qpg_type == IB_QPG_NONE || qp->qpg_type == IB_QPG_PARENT)) { 1864 mlx4_ib_steer_qp_reg(dev, qp, 1); 1865 steer_qp = 1; 1866 } 1867 } 1868 1869 if (attr_mask & IB_QP_PKEY_INDEX) { 1870 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1871 context->pri_path.disable_pkey_check = 0x40; 1872 context->pri_path.pkey_index = attr->pkey_index; 1873 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 1874 } 1875 1876 if ((attr_mask & IB_QP_AV) && (ibqp->qp_type != IB_QPT_RAW_PACKET)) { 1877 if (mlx4_set_path(dev, &attr->ah_attr, (u8 *)attr->smac, 1878 attr_mask & IB_QP_VID ? 1879 attr->vlan_id : 0xffff , 1880 qp, &context->pri_path, 1881 attr_mask & IB_QP_PORT ? 1882 attr->port_num : qp->port, 1)) 1883 goto out; 1884 1885 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 1886 MLX4_QP_OPTPAR_SCHED_QUEUE); 1887 } 1888 1889 if (attr_mask & IB_QP_TIMEOUT) { 1890 context->pri_path.ackto |= attr->timeout << 3; 1891 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 1892 } 1893 1894 if (attr_mask & IB_QP_ALT_PATH) { 1895 if (attr->alt_port_num == 0 || 1896 attr->alt_port_num > dev->dev->caps.num_ports) 1897 goto out; 1898 1899 if (attr->alt_pkey_index >= 1900 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 1901 goto out; 1902 1903 if (mlx4_set_path(dev, &attr->alt_ah_attr, (u8 *)attr->smac, 1904 attr_mask & IB_QP_ALT_VID ? 1905 attr->alt_vlan_id : 0xffff, 1906 qp, &context->alt_path, 1907 attr->alt_port_num, 0)) 1908 goto out; 1909 1910 context->alt_path.pkey_index = attr->alt_pkey_index; 1911 context->alt_path.ackto = attr->alt_timeout << 3; 1912 context->alt_path.counter_index = dev->counters[attr->alt_port_num - 1].counter_index; 1913 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 1914 } 1915 1916 pd = get_pd(qp); 1917 get_cqs(qp, &send_cq, &recv_cq); 1918 context->pd = cpu_to_be32(pd->pdn); 1919 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 1920 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 1921 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 1922 1923 /* Set "fast registration enabled" for all kernel QPs */ 1924 if (!qp->ibqp.uobject) 1925 context->params1 |= cpu_to_be32(1 << 11); 1926 1927 if (attr_mask & IB_QP_RNR_RETRY) { 1928 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1929 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 1930 } 1931 1932 if (attr_mask & IB_QP_RETRY_CNT) { 1933 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1934 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 1935 } 1936 1937 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1938 if (attr->max_rd_atomic) 1939 context->params1 |= 1940 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1941 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 1942 } 1943 1944 if (attr_mask & IB_QP_SQ_PSN) 1945 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1946 1947 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1948 if (attr->max_dest_rd_atomic) 1949 context->params2 |= 1950 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1951 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 1952 } 1953 1954 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 1955 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 1956 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 1957 } 1958 1959 if (attr_mask & IB_M_EXT_CLASS_1) 1960 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_MASTER); 1961 1962 /* for now we enable also sqe on send */ 1963 if (attr_mask & IB_M_EXT_CLASS_2) { 1964 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_SYNC_SQ); 1965 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_MASTER); 1966 } 1967 1968 if (attr_mask & IB_M_EXT_CLASS_3) 1969 context->params2 |= cpu_to_be32(MLX4_QP_BIT_COLL_SYNC_RQ); 1970 1971 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1972 context->params2 |= (qp->flags & MLX4_IB_QP_CAP_CROSS_CHANNEL ? 1973 cpu_to_be32(MLX4_QP_BIT_COLL_MASTER) : 0); 1974 context->params2 |= (qp->flags & MLX4_IB_QP_CAP_MANAGED_SEND ? 1975 cpu_to_be32(MLX4_QP_BIT_COLL_MASTER | MLX4_QP_BIT_COLL_SYNC_SQ) : 0); 1976 context->params2 |= (qp->flags & MLX4_IB_QP_CAP_MANAGED_RECV ? 1977 cpu_to_be32(MLX4_QP_BIT_COLL_MASTER | MLX4_QP_BIT_COLL_SYNC_RQ) : 0); 1978 } 1979 1980 if (ibqp->srq) 1981 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 1982 1983 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1984 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1985 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 1986 } 1987 if (attr_mask & IB_QP_RQ_PSN) 1988 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1989 1990 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 1991 if (attr_mask & IB_QP_QKEY) { 1992 if (qp->mlx4_ib_qp_type & 1993 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 1994 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 1995 else { 1996 if (mlx4_is_mfunc(dev->dev) && 1997 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 1998 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 1999 MLX4_RESERVED_QKEY_BASE) { 2000 pr_err("Cannot use reserved QKEY" 2001 " 0x%x (range 0xffff0000..0xffffffff" 2002 " is reserved)\n", attr->qkey); 2003 err = -EINVAL; 2004 goto out; 2005 } 2006 context->qkey = cpu_to_be32(attr->qkey); 2007 } 2008 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2009 } 2010 2011 if (ibqp->srq) 2012 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); 2013 2014 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2015 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2016 2017 if (cur_state == IB_QPS_INIT && 2018 new_state == IB_QPS_RTR && 2019 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || 2020 ibqp->qp_type == IB_QPT_UD || 2021 ibqp->qp_type == IB_QPT_RAW_PACKET)) { 2022 context->pri_path.sched_queue = (qp->port - 1) << 6; 2023 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2024 qp->mlx4_ib_qp_type & 2025 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2026 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2027 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2028 context->pri_path.fl = 0x80; 2029 } else { 2030 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2031 context->pri_path.fl = 0x80; 2032 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2033 } 2034 if (ibqp->qp_type == IB_QPT_RAW_PACKET && 2035 (attr_mask & IB_QP_AV)) { 2036 context->pri_path.sched_queue |= 2037 ((attr->ah_attr.sl & 0xf) << 3); 2038 context->pri_path.feup = 1 << 6; 2039 } 2040 is_eth = rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2041 IB_LINK_LAYER_ETHERNET; 2042 if (is_eth) { 2043 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2044 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2045 context->pri_path.feup = 1 << 7; /* don't fsm */ 2046 /* handle smac_index */ 2047 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2048 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2049 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2050 err = handle_eth_ud_smac_index(dev, qp, (const u8 *)attr->smac, context); 2051 if (err) 2052 return -EINVAL; 2053 } 2054 } 2055 } 2056 2057 if (ibqp->qp_type == IB_QPT_UD) 2058 if (is_eth && (new_state == IB_QPS_RTR)) { 2059 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2060 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2061 } 2062 2063 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2064 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2065 sqd_event = 1; 2066 else 2067 sqd_event = 0; 2068 2069 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2070 context->rlkey |= (1 << 4); 2071 2072 if ((attr_mask & IB_QP_GROUP_RSS) && 2073 (qp->qpg_data->rss_child_count > 1)) { 2074 struct mlx4_ib_qpg_data *qpg_data = qp->qpg_data; 2075 void *rss_context_base = &context->pri_path; 2076 struct mlx4_rss_context *rss_context = 2077 (struct mlx4_rss_context *) (rss_context_base 2078 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH); 2079 2080 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2081 2082 /* This should be tbl_sz_base_qpn */ 2083 rss_context->base_qpn = cpu_to_be32(qpg_data->rss_qpn_base | 2084 (ilog2(qpg_data->rss_child_count) << 24)); 2085 rss_context->default_qpn = cpu_to_be32(qpg_data->rss_qpn_base); 2086 /* This should be flags_hash_fn */ 2087 rss_context->flags = MLX4_RSS_TCP_IPV6 | 2088 MLX4_RSS_TCP_IPV4; 2089 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS) { 2090 rss_context->base_qpn_udp = rss_context->default_qpn; 2091 rss_context->flags |= MLX4_RSS_IPV6 | 2092 MLX4_RSS_IPV4 | 2093 MLX4_RSS_UDP_IPV6 | 2094 MLX4_RSS_UDP_IPV4; 2095 } 2096 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) { 2097 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 2098 0x1983A2FC, 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 2099 0xA74499AD, 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; 2100 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2101 memcpy(rss_context->rss_key, rsskey, 2102 sizeof(rss_context->rss_key)); 2103 } else { 2104 rss_context->hash_fn = MLX4_RSS_HASH_XOR; 2105 memset(rss_context->rss_key, 0, 2106 sizeof(rss_context->rss_key)); 2107 } 2108 } 2109 /* 2110 * Before passing a kernel QP to the HW, make sure that the 2111 * ownership bits of the send queue are set and the SQ 2112 * headroom is stamped so that the hardware doesn't start 2113 * processing stale work requests. 2114 */ 2115 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2116 struct mlx4_wqe_ctrl_seg *ctrl; 2117 int i; 2118 2119 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2120 ctrl = get_send_wqe(qp, i); 2121 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2122 if (qp->sq_max_wqes_per_wr == 1) 2123 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4); 2124 2125 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 2126 } 2127 } 2128 2129 if ((qp->port && rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2130 IB_LINK_LAYER_ETHERNET) && (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)) 2131 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2132 MLX4_IB_LINK_TYPE_ETH; 2133 2134 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2135 to_mlx4_state(new_state), context, optpar, 2136 sqd_event, &qp->mqp); 2137 if (err) 2138 goto out; 2139 2140 qp->state = new_state; 2141 2142 if (attr_mask & IB_QP_ACCESS_FLAGS) 2143 qp->atomic_rd_en = attr->qp_access_flags; 2144 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2145 qp->resp_depth = attr->max_dest_rd_atomic; 2146 if (attr_mask & IB_QP_PORT) { 2147 qp->port = attr->port_num; 2148 update_mcg_macs(dev, qp); 2149 } 2150 if (attr_mask & IB_QP_ALT_PATH) 2151 qp->alt_port = attr->alt_port_num; 2152 2153 if (is_sqp(dev, qp)) 2154 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2155 2156 /* Set 'ignore_cq_overrun' bits for collectives offload */ 2157 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2158 if (attr_mask & (IB_M_EXT_CLASS_2 | IB_M_EXT_CLASS_3)) { 2159 err = mlx4_ib_ignore_overrun_cq(ibqp->send_cq); 2160 if (err) { 2161 pr_err("Failed to set ignore CQ " 2162 "overrun for QP 0x%x's send CQ\n", 2163 ibqp->qp_num); 2164 goto out; 2165 } 2166 2167 if (ibqp->recv_cq != ibqp->send_cq) { 2168 err = mlx4_ib_ignore_overrun_cq(ibqp->recv_cq); 2169 if (err) { 2170 pr_err("Failed to set ignore " 2171 "CQ overrun for QP 0x%x's recv " 2172 "CQ\n", ibqp->qp_num); 2173 goto out; 2174 } 2175 } 2176 } 2177 } 2178 2179 /* 2180 * If we moved QP0 to RTR, bring the IB link up; if we moved 2181 * QP0 to RESET or ERROR, bring the link back down. 2182 */ 2183 if (is_qp0(dev, qp)) { 2184 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2185 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2186 pr_warn("INIT_PORT failed for port %d\n", 2187 qp->port); 2188 2189 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2190 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2191 mlx4_CLOSE_PORT(dev->dev, qp->port); 2192 } 2193 2194 /* 2195 * If we moved a kernel QP to RESET, clean up all old CQ 2196 * entries and reinitialize the QP. 2197 */ 2198 if (new_state == IB_QPS_RESET) { 2199 if (!ibqp->uobject) { 2200 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2201 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2202 if (send_cq != recv_cq) 2203 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2204 2205 qp->rq.head = 0; 2206 qp->rq.tail = 0; 2207 qp->sq.head = 0; 2208 qp->sq.tail = 0; 2209 qp->sq_next_wqe = 0; 2210 if (qp->rq.wqe_cnt) 2211 *qp->db.db = 0; 2212 2213 if (qp->flags & MLX4_IB_QP_NETIF && 2214 (qp->qpg_type == IB_QPG_NONE || 2215 qp->qpg_type == IB_QPG_PARENT)) 2216 mlx4_ib_steer_qp_reg(dev, qp, 0); 2217 } 2218 if (qp->pri.smac) { 2219 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2220 qp->pri.smac = 0; 2221 } 2222 if (qp->alt.smac) { 2223 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2224 qp->alt.smac = 0; 2225 } 2226 if (qp->pri.vid < 0x1000) { 2227 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2228 qp->pri.vid = 0xFFFF; 2229 qp->pri.candidate_vid = 0xFFFF; 2230 qp->pri.update_vid = 0; 2231 } 2232 2233 if (qp->alt.vid < 0x1000) { 2234 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2235 qp->alt.vid = 0xFFFF; 2236 qp->alt.candidate_vid = 0xFFFF; 2237 qp->alt.update_vid = 0; 2238 } 2239 } 2240 2241 out: 2242 if (err && steer_qp) 2243 mlx4_ib_steer_qp_reg(dev, qp, 0); 2244 kfree(context); 2245 if (qp->pri.candidate_smac) { 2246 if (err) 2247 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2248 else { 2249 if (qp->pri.smac) { 2250 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2251 } 2252 qp->pri.smac = qp->pri.candidate_smac; 2253 qp->pri.smac_index = qp->pri.candidate_smac_index; 2254 qp->pri.smac_port = qp->pri.candidate_smac_port; 2255 2256 } 2257 qp->pri.candidate_smac = 0; 2258 qp->pri.candidate_smac_index = 0; 2259 qp->pri.candidate_smac_port = 0; 2260 } 2261 if (qp->alt.candidate_smac) { 2262 if (err) 2263 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->pri.candidate_smac); 2264 else { 2265 if (qp->pri.smac) { 2266 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2267 } 2268 qp->alt.smac = qp->alt.candidate_smac; 2269 qp->alt.smac_index = qp->alt.candidate_smac_index; 2270 qp->alt.smac_port = qp->alt.candidate_smac_port; 2271 2272 } 2273 qp->pri.candidate_smac = 0; 2274 qp->pri.candidate_smac_index = 0; 2275 qp->pri.candidate_smac_port = 0; 2276 } 2277 2278 if (qp->pri.update_vid) { 2279 if (err) { 2280 if (qp->pri.candidate_vid < 0x1000) 2281 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2282 qp->pri.candidate_vid); 2283 } else { 2284 if (qp->pri.vid < 0x1000) 2285 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2286 qp->pri.vid); 2287 qp->pri.vid = qp->pri.candidate_vid; 2288 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2289 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2290 } 2291 qp->pri.candidate_vid = 0xFFFF; 2292 qp->pri.update_vid = 0; 2293 } 2294 2295 if (qp->alt.update_vid) { 2296 if (err) { 2297 if (qp->alt.candidate_vid < 0x1000) 2298 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2299 qp->alt.candidate_vid); 2300 } else { 2301 if (qp->alt.vid < 0x1000) 2302 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2303 qp->alt.vid); 2304 qp->alt.vid = qp->alt.candidate_vid; 2305 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2306 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2307 } 2308 qp->alt.candidate_vid = 0xFFFF; 2309 qp->alt.update_vid = 0; 2310 } 2311 2312 return err; 2313 } 2314 2315 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2316 int attr_mask, struct ib_udata *udata) 2317 { 2318 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2319 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2320 enum ib_qp_state cur_state, new_state; 2321 int err = -EINVAL; 2322 int ll; 2323 2324 mutex_lock(&qp->mutex); 2325 2326 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2327 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2328 2329 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2330 ll = IB_LINK_LAYER_UNSPECIFIED; 2331 } else { 2332 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2333 ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2334 } 2335 2336 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2337 attr_mask & ~IB_M_QP_MOD_VEND_MASK, ll)) { 2338 pr_debug("qpn 0x%x: invalid attribute mask specified " 2339 "for transition %d to %d. qp_type %d," 2340 " attr_mask 0x%x\n", 2341 ibqp->qp_num, cur_state, new_state, 2342 ibqp->qp_type, attr_mask); 2343 goto out; 2344 } 2345 2346 if ((attr_mask & IB_M_QP_MOD_VEND_MASK) && !dev->dev->caps.sync_qp) { 2347 pr_err("extended verbs are not supported by %s\n", 2348 dev->ib_dev.name); 2349 goto out; 2350 } 2351 2352 if ((attr_mask & IB_QP_PORT) && 2353 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2354 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2355 "for transition %d to %d. qp_type %d\n", 2356 ibqp->qp_num, attr->port_num, cur_state, 2357 new_state, ibqp->qp_type); 2358 goto out; 2359 } 2360 2361 if (attr_mask & IB_QP_PKEY_INDEX) { 2362 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2363 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2364 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2365 "for transition %d to %d. qp_type %d\n", 2366 ibqp->qp_num, attr->pkey_index, cur_state, 2367 new_state, ibqp->qp_type); 2368 goto out; 2369 } 2370 } 2371 2372 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2373 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2374 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2375 "Transition %d to %d. qp_type %d\n", 2376 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2377 new_state, ibqp->qp_type); 2378 goto out; 2379 } 2380 2381 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2382 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2383 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2384 "Transition %d to %d. qp_type %d\n", 2385 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2386 new_state, ibqp->qp_type); 2387 goto out; 2388 } 2389 2390 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2391 err = 0; 2392 goto out; 2393 } 2394 2395 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2396 2397 out: 2398 mutex_unlock(&qp->mutex); 2399 return err; 2400 } 2401 2402 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2403 struct ib_send_wr *wr, 2404 void *wqe, unsigned *mlx_seg_len) 2405 { 2406 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2407 struct ib_device *ib_dev = &mdev->ib_dev; 2408 struct mlx4_wqe_mlx_seg *mlx = wqe; 2409 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2410 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2411 u16 pkey; 2412 u32 qkey; 2413 int send_size; 2414 int header_size; 2415 int spc; 2416 int i; 2417 2418 if (wr->opcode != IB_WR_SEND) 2419 return -EINVAL; 2420 2421 send_size = 0; 2422 2423 for (i = 0; i < wr->num_sge; ++i) 2424 send_size += wr->sg_list[i].length; 2425 2426 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2427 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2428 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2429 send_size += sizeof (struct mlx4_ib_tunnel_header); 2430 2431 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header); 2432 2433 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2434 sqp->ud_header.lrh.service_level = 2435 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2436 sqp->ud_header.lrh.destination_lid = 2437 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2438 sqp->ud_header.lrh.source_lid = 2439 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2440 } 2441 2442 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2443 2444 /* force loopback */ 2445 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2446 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2447 2448 sqp->ud_header.lrh.virtual_lane = 0; 2449 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 2450 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2451 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2452 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2453 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2454 else 2455 sqp->ud_header.bth.destination_qpn = 2456 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]); 2457 2458 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2459 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2460 return -EINVAL; 2461 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2462 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2463 2464 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2465 sqp->ud_header.immediate_present = 0; 2466 2467 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2468 2469 /* 2470 * Inline data segments may not cross a 64 byte boundary. If 2471 * our UD header is bigger than the space available up to the 2472 * next 64 byte boundary in the WQE, use two inline data 2473 * segments to hold the UD header. 2474 */ 2475 spc = MLX4_INLINE_ALIGN - 2476 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2477 if (header_size <= spc) { 2478 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2479 memcpy(inl + 1, sqp->header_buf, header_size); 2480 i = 1; 2481 } else { 2482 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2483 memcpy(inl + 1, sqp->header_buf, spc); 2484 2485 inl = (void *) (inl + 1) + spc; 2486 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2487 /* 2488 * Need a barrier here to make sure all the data is 2489 * visible before the byte_count field is set. 2490 * Otherwise the HCA prefetcher could grab the 64-byte 2491 * chunk with this inline segment and get a valid (!= 2492 * 0xffffffff) byte count but stale data, and end up 2493 * generating a packet with bad headers. 2494 * 2495 * The first inline segment's byte_count field doesn't 2496 * need a barrier, because it comes after a 2497 * control/MLX segment and therefore is at an offset 2498 * of 16 mod 64. 2499 */ 2500 wmb(); 2501 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2502 i = 2; 2503 } 2504 2505 *mlx_seg_len = 2506 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2507 return 0; 2508 } 2509 2510 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr, 2511 void *wqe, unsigned *mlx_seg_len) 2512 { 2513 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2514 struct mlx4_wqe_mlx_seg *mlx = wqe; 2515 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2516 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2517 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2518 union ib_gid sgid; 2519 u16 pkey; 2520 int send_size; 2521 int header_size; 2522 int spc; 2523 int i; 2524 int is_eth; 2525 int is_vlan = 0; 2526 int is_grh; 2527 u16 uninitialized_var(vlan); 2528 int err = 0; 2529 2530 send_size = 0; 2531 for (i = 0; i < wr->num_sge; ++i) 2532 send_size += wr->sg_list[i].length; 2533 2534 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2535 is_grh = mlx4_ib_ah_grh_present(ah); 2536 if (is_eth) { 2537 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2538 /* When multi-function is enabled, the ib_core gid 2539 * indexes don't necessarily match the hw ones, so 2540 * we must use our own cache */ 2541 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2542 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2543 ah->av.ib.gid_index, &sgid.raw[0]); 2544 if (err) 2545 return err; 2546 } else { 2547 err = ib_get_cached_gid(ib_dev, 2548 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2549 ah->av.ib.gid_index, &sgid); 2550 if (err) 2551 return err; 2552 } 2553 2554 if (is_eth && ah->av.eth.vlan != 0xffff) { 2555 vlan = cpu_to_be16(ah->av.eth.vlan) & 0x0fff; 2556 is_vlan = 1; 2557 } 2558 } 2559 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header); 2560 2561 if (!is_eth) { 2562 sqp->ud_header.lrh.service_level = 2563 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2564 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 2565 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2566 } 2567 2568 if (is_grh) { 2569 sqp->ud_header.grh.traffic_class = 2570 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2571 sqp->ud_header.grh.flow_label = 2572 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 2573 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 2574 if (is_eth) 2575 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 2576 else { 2577 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2578 /* When multi-function is enabled, the ib_core gid 2579 * indexes don't necessarily match the hw ones, so 2580 * we must use our own cache */ 2581 sqp->ud_header.grh.source_gid.global.subnet_prefix = 2582 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2583 subnet_prefix; 2584 sqp->ud_header.grh.source_gid.global.interface_id = 2585 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2586 guid_cache[ah->av.ib.gid_index]; 2587 } else 2588 ib_get_cached_gid(ib_dev, 2589 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2590 ah->av.ib.gid_index, 2591 &sqp->ud_header.grh.source_gid); 2592 } 2593 memcpy(sqp->ud_header.grh.destination_gid.raw, 2594 ah->av.ib.dgid, 16); 2595 } 2596 2597 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2598 2599 if (!is_eth) { 2600 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 2601 (sqp->ud_header.lrh.destination_lid == 2602 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 2603 (sqp->ud_header.lrh.service_level << 8)); 2604 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 2605 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 2606 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2607 } 2608 2609 switch (wr->opcode) { 2610 case IB_WR_SEND: 2611 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2612 sqp->ud_header.immediate_present = 0; 2613 break; 2614 case IB_WR_SEND_WITH_IMM: 2615 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2616 sqp->ud_header.immediate_present = 1; 2617 sqp->ud_header.immediate_data = wr->ex.imm_data; 2618 break; 2619 default: 2620 return -EINVAL; 2621 } 2622 2623 if (is_eth) { 2624 u8 *smac; 2625 struct in6_addr in6; 2626 2627 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 2628 2629 mlx->sched_prio = cpu_to_be16(pcp); 2630 2631 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 2632 /* FIXME: cache smac value? */ 2633 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 2634 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 2635 memcpy(&in6, sgid.raw, sizeof(in6)); 2636 2637 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) 2638 smac = IF_LLADDR(to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1]); 2639 else 2640 smac = ah->av.eth.s_mac; /* use the src mac of the tunnel */ 2641 memcpy(sqp->ud_header.eth.smac_h, smac, 6); 2642 2643 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 2644 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 2645 if (!is_vlan) { 2646 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE); 2647 } else { 2648 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE); 2649 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 2650 } 2651 } else { 2652 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 2653 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 2654 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 2655 } 2656 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 2657 if (!sqp->qp.ibqp.qp_num) 2658 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 2659 else 2660 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey); 2661 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2662 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2663 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2664 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? 2665 sqp->qkey : wr->wr.ud.remote_qkey); 2666 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 2667 2668 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2669 2670 if (0) { 2671 pr_err("built UD header of size %d:\n", header_size); 2672 for (i = 0; i < header_size / 4; ++i) { 2673 if (i % 8 == 0) 2674 pr_err(" [%02x] ", i * 4); 2675 pr_cont(" %08x", 2676 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 2677 if ((i + 1) % 8 == 0) 2678 pr_cont("\n"); 2679 } 2680 pr_err("\n"); 2681 } 2682 2683 /* 2684 * Inline data segments may not cross a 64 byte boundary. If 2685 * our UD header is bigger than the space available up to the 2686 * next 64 byte boundary in the WQE, use two inline data 2687 * segments to hold the UD header. 2688 */ 2689 spc = MLX4_INLINE_ALIGN - 2690 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2691 if (header_size <= spc) { 2692 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2693 memcpy(inl + 1, sqp->header_buf, header_size); 2694 i = 1; 2695 } else { 2696 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2697 memcpy(inl + 1, sqp->header_buf, spc); 2698 2699 inl = (void *) (inl + 1) + spc; 2700 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2701 /* 2702 * Need a barrier here to make sure all the data is 2703 * visible before the byte_count field is set. 2704 * Otherwise the HCA prefetcher could grab the 64-byte 2705 * chunk with this inline segment and get a valid (!= 2706 * 0xffffffff) byte count but stale data, and end up 2707 * generating a packet with bad headers. 2708 * 2709 * The first inline segment's byte_count field doesn't 2710 * need a barrier, because it comes after a 2711 * control/MLX segment and therefore is at an offset 2712 * of 16 mod 64. 2713 */ 2714 wmb(); 2715 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2716 i = 2; 2717 } 2718 2719 *mlx_seg_len = 2720 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2721 return 0; 2722 } 2723 2724 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2725 { 2726 unsigned cur; 2727 struct mlx4_ib_cq *cq; 2728 2729 cur = wq->head - wq->tail; 2730 if (likely(cur + nreq < wq->max_post)) 2731 return 0; 2732 2733 cq = to_mcq(ib_cq); 2734 spin_lock(&cq->lock); 2735 cur = wq->head - wq->tail; 2736 spin_unlock(&cq->lock); 2737 2738 return cur + nreq >= wq->max_post; 2739 } 2740 2741 static __be32 convert_access(int acc) 2742 { 2743 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 2744 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 2745 (acc & IB_ACCESS_REMOTE_WRITE ? 2746 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 2747 (acc & IB_ACCESS_REMOTE_READ ? 2748 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 2749 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 2750 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 2751 } 2752 2753 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr) 2754 { 2755 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list); 2756 int i; 2757 2758 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i) 2759 mfrpl->mapped_page_list[i] = 2760 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] | 2761 MLX4_MTT_FLAG_PRESENT); 2762 2763 fseg->flags = convert_access(wr->wr.fast_reg.access_flags); 2764 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey); 2765 fseg->buf_list = cpu_to_be64(mfrpl->map); 2766 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 2767 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length); 2768 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 2769 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift); 2770 fseg->reserved[0] = 0; 2771 fseg->reserved[1] = 0; 2772 } 2773 2774 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr) 2775 { 2776 bseg->flags1 = 2777 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) & 2778 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ | 2779 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE | 2780 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC); 2781 bseg->flags2 = 0; 2782 if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2) 2783 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2); 2784 if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED) 2785 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED); 2786 bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey); 2787 bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey); 2788 bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr); 2789 bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length); 2790 } 2791 2792 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 2793 { 2794 iseg->mem_key = cpu_to_be32(rkey); 2795 2796 iseg->reserved1 = 0; 2797 iseg->reserved2 = 0; 2798 iseg->reserved3[0] = 0; 2799 iseg->reserved3[1] = 0; 2800 } 2801 2802 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 2803 u64 remote_addr, u32 rkey) 2804 { 2805 rseg->raddr = cpu_to_be64(remote_addr); 2806 rseg->rkey = cpu_to_be32(rkey); 2807 rseg->reserved = 0; 2808 } 2809 2810 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr) 2811 { 2812 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 2813 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 2814 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 2815 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 2816 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 2817 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask); 2818 } else { 2819 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 2820 aseg->compare = 0; 2821 } 2822 2823 } 2824 2825 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 2826 struct ib_send_wr *wr) 2827 { 2828 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 2829 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask); 2830 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 2831 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask); 2832 } 2833 2834 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 2835 struct ib_send_wr *wr) 2836 { 2837 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); 2838 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2839 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 2840 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan; 2841 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6); 2842 } 2843 2844 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 2845 struct mlx4_wqe_datagram_seg *dseg, 2846 struct ib_send_wr *wr, enum ib_qp_type qpt) 2847 { 2848 union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av; 2849 struct mlx4_av sqp_av = {0}; 2850 int port = *((u8 *) &av->ib.port_pd) & 0x3; 2851 2852 /* force loopback */ 2853 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 2854 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 2855 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 2856 cpu_to_be32(0xf0000000); 2857 2858 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 2859 /* This function used only for sending on QP1 proxies */ 2860 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]); 2861 /* Use QKEY from the QP context, which is set by master */ 2862 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2863 } 2864 2865 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len) 2866 { 2867 struct mlx4_wqe_inline_seg *inl = wqe; 2868 struct mlx4_ib_tunnel_header hdr; 2869 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); 2870 int spc; 2871 int i; 2872 2873 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 2874 hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 2875 hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index); 2876 hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 2877 memcpy(hdr.mac, ah->av.eth.mac, 6); 2878 hdr.vlan = cpu_to_be16(ah->av.eth.vlan); 2879 2880 spc = MLX4_INLINE_ALIGN - 2881 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2882 if (sizeof (hdr) <= spc) { 2883 memcpy(inl + 1, &hdr, sizeof (hdr)); 2884 wmb(); 2885 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 2886 i = 1; 2887 } else { 2888 memcpy(inl + 1, &hdr, spc); 2889 wmb(); 2890 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2891 2892 inl = (void *) (inl + 1) + spc; 2893 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 2894 wmb(); 2895 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 2896 i = 2; 2897 } 2898 2899 *mlx_seg_len = 2900 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 2901 } 2902 2903 static void set_mlx_icrc_seg(void *dseg) 2904 { 2905 u32 *t = dseg; 2906 struct mlx4_wqe_inline_seg *iseg = dseg; 2907 2908 t[1] = 0; 2909 2910 /* 2911 * Need a barrier here before writing the byte_count field to 2912 * make sure that all the data is visible before the 2913 * byte_count field is set. Otherwise, if the segment begins 2914 * a new cacheline, the HCA prefetcher could grab the 64-byte 2915 * chunk and get a valid (!= * 0xffffffff) byte count but 2916 * stale data, and end up sending the wrong data. 2917 */ 2918 wmb(); 2919 2920 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 2921 } 2922 2923 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2924 { 2925 dseg->lkey = cpu_to_be32(sg->lkey); 2926 dseg->addr = cpu_to_be64(sg->addr); 2927 2928 /* 2929 * Need a barrier here before writing the byte_count field to 2930 * make sure that all the data is visible before the 2931 * byte_count field is set. Otherwise, if the segment begins 2932 * a new cacheline, the HCA prefetcher could grab the 64-byte 2933 * chunk and get a valid (!= * 0xffffffff) byte count but 2934 * stale data, and end up sending the wrong data. 2935 */ 2936 wmb(); 2937 2938 dseg->byte_count = cpu_to_be32(sg->length); 2939 } 2940 2941 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2942 { 2943 dseg->byte_count = cpu_to_be32(sg->length); 2944 dseg->lkey = cpu_to_be32(sg->lkey); 2945 dseg->addr = cpu_to_be64(sg->addr); 2946 } 2947 2948 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr, 2949 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 2950 __be32 *lso_hdr_sz, __be32 *blh) 2951 { 2952 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16); 2953 2954 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 2955 *blh = cpu_to_be32(1 << 6); 2956 2957 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 2958 wr->num_sge > qp->sq.max_gs - (halign >> 4))) 2959 return -EINVAL; 2960 2961 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen); 2962 2963 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 | 2964 wr->wr.ud.hlen); 2965 *lso_seg_len = halign; 2966 return 0; 2967 } 2968 2969 static __be32 send_ieth(struct ib_send_wr *wr) 2970 { 2971 switch (wr->opcode) { 2972 case IB_WR_SEND_WITH_IMM: 2973 case IB_WR_RDMA_WRITE_WITH_IMM: 2974 return wr->ex.imm_data; 2975 2976 case IB_WR_SEND_WITH_INV: 2977 return cpu_to_be32(wr->ex.invalidate_rkey); 2978 2979 default: 2980 return 0; 2981 } 2982 } 2983 2984 static void add_zero_len_inline(void *wqe) 2985 { 2986 struct mlx4_wqe_inline_seg *inl = wqe; 2987 memset(wqe, 0, 16); 2988 inl->byte_count = cpu_to_be32(1 << 31); 2989 } 2990 2991 static int lay_inline_data(struct mlx4_ib_qp *qp, struct ib_send_wr *wr, 2992 void *wqe, int *sz) 2993 { 2994 struct mlx4_wqe_inline_seg *seg; 2995 void *addr; 2996 int len, seg_len; 2997 int num_seg; 2998 int off, to_copy; 2999 int i; 3000 int inl = 0; 3001 3002 seg = wqe; 3003 wqe += sizeof *seg; 3004 off = ((unsigned long)wqe) & (unsigned long)(MLX4_INLINE_ALIGN - 1); 3005 num_seg = 0; 3006 seg_len = 0; 3007 3008 for (i = 0; i < wr->num_sge; ++i) { 3009 addr = (void *) (unsigned long)(wr->sg_list[i].addr); 3010 len = wr->sg_list[i].length; 3011 inl += len; 3012 3013 if (inl > qp->max_inline_data) { 3014 inl = 0; 3015 return -1; 3016 } 3017 3018 while (len >= MLX4_INLINE_ALIGN - off) { 3019 to_copy = MLX4_INLINE_ALIGN - off; 3020 memcpy(wqe, addr, to_copy); 3021 len -= to_copy; 3022 wqe += to_copy; 3023 addr += to_copy; 3024 seg_len += to_copy; 3025 wmb(); /* see comment below */ 3026 seg->byte_count = htonl(MLX4_INLINE_SEG | seg_len); 3027 seg_len = 0; 3028 seg = wqe; 3029 wqe += sizeof *seg; 3030 off = sizeof *seg; 3031 ++num_seg; 3032 } 3033 3034 memcpy(wqe, addr, len); 3035 wqe += len; 3036 seg_len += len; 3037 off += len; 3038 } 3039 3040 if (seg_len) { 3041 ++num_seg; 3042 /* 3043 * Need a barrier here to make sure 3044 * all the data is visible before the 3045 * byte_count field is set. Otherwise 3046 * the HCA prefetcher could grab the 3047 * 64-byte chunk with this inline 3048 * segment and get a valid (!= 3049 * 0xffffffff) byte count but stale 3050 * data, and end up sending the wrong 3051 * data. 3052 */ 3053 wmb(); 3054 seg->byte_count = htonl(MLX4_INLINE_SEG | seg_len); 3055 } 3056 3057 *sz = (inl + num_seg * sizeof *seg + 15) / 16; 3058 3059 return 0; 3060 } 3061 3062 /* 3063 * Avoid using memcpy() to copy to BlueFlame page, since memcpy() 3064 * implementations may use move-string-buffer assembler instructions, 3065 * which do not guarantee order of copying. 3066 */ 3067 static void mlx4_bf_copy(unsigned long *dst, unsigned long *src, 3068 unsigned bytecnt) 3069 { 3070 __iowrite64_copy(dst, src, bytecnt / 8); 3071 } 3072 3073 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3074 struct ib_send_wr **bad_wr) 3075 { 3076 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3077 void *wqe; 3078 struct mlx4_wqe_ctrl_seg *uninitialized_var(ctrl); 3079 struct mlx4_wqe_data_seg *dseg; 3080 unsigned long flags; 3081 int nreq; 3082 int err = 0; 3083 unsigned ind; 3084 int uninitialized_var(stamp); 3085 int uninitialized_var(size); 3086 unsigned uninitialized_var(seglen); 3087 __be32 dummy; 3088 __be32 *lso_wqe; 3089 __be32 uninitialized_var(lso_hdr_sz); 3090 __be32 blh; 3091 int i; 3092 int inl = 0; 3093 spin_lock_irqsave(&qp->sq.lock, flags); 3094 3095 ind = qp->sq_next_wqe; 3096 3097 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3098 lso_wqe = &dummy; 3099 blh = 0; 3100 3101 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3102 err = -ENOMEM; 3103 *bad_wr = wr; 3104 goto out; 3105 } 3106 3107 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3108 err = -EINVAL; 3109 *bad_wr = wr; 3110 goto out; 3111 } 3112 3113 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3114 *((u32 *) (&ctrl->vlan_tag)) = 0; 3115 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3116 3117 ctrl->srcrb_flags = 3118 (wr->send_flags & IB_SEND_SIGNALED ? 3119 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3120 (wr->send_flags & IB_SEND_SOLICITED ? 3121 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3122 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3123 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3124 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3125 qp->sq_signal_bits; 3126 3127 ctrl->imm = send_ieth(wr); 3128 3129 wqe += sizeof *ctrl; 3130 size = sizeof *ctrl / 16; 3131 3132 switch (qp->mlx4_ib_qp_type) { 3133 case MLX4_IB_QPT_RC: 3134 case MLX4_IB_QPT_UC: 3135 switch (wr->opcode) { 3136 case IB_WR_ATOMIC_CMP_AND_SWP: 3137 case IB_WR_ATOMIC_FETCH_AND_ADD: 3138 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3139 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 3140 wr->wr.atomic.rkey); 3141 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3142 3143 set_atomic_seg(wqe, wr); 3144 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3145 3146 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3147 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3148 3149 break; 3150 3151 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3152 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 3153 wr->wr.atomic.rkey); 3154 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3155 3156 set_masked_atomic_seg(wqe, wr); 3157 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3158 3159 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3160 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3161 3162 break; 3163 3164 case IB_WR_RDMA_READ: 3165 case IB_WR_RDMA_WRITE: 3166 case IB_WR_RDMA_WRITE_WITH_IMM: 3167 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 3168 wr->wr.rdma.rkey); 3169 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3170 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3171 break; 3172 3173 case IB_WR_LOCAL_INV: 3174 ctrl->srcrb_flags |= 3175 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3176 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3177 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3178 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3179 break; 3180 3181 case IB_WR_FAST_REG_MR: 3182 ctrl->srcrb_flags |= 3183 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3184 set_fmr_seg(wqe, wr); 3185 wqe += sizeof (struct mlx4_wqe_fmr_seg); 3186 size += sizeof (struct mlx4_wqe_fmr_seg) / 16; 3187 break; 3188 3189 case IB_WR_BIND_MW: 3190 ctrl->srcrb_flags |= 3191 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3192 set_bind_seg(wqe, wr); 3193 wqe += sizeof(struct mlx4_wqe_bind_seg); 3194 size += sizeof(struct mlx4_wqe_bind_seg) / 16; 3195 default: 3196 /* No extra segments required for sends */ 3197 break; 3198 } 3199 break; 3200 3201 case MLX4_IB_QPT_TUN_SMI_OWNER: 3202 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen); 3203 if (unlikely(err)) { 3204 *bad_wr = wr; 3205 goto out; 3206 } 3207 wqe += seglen; 3208 size += seglen / 16; 3209 break; 3210 case MLX4_IB_QPT_TUN_SMI: 3211 case MLX4_IB_QPT_TUN_GSI: 3212 /* this is a UD qp used in MAD responses to slaves. */ 3213 set_datagram_seg(wqe, wr); 3214 /* set the forced-loopback bit in the data seg av */ 3215 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3216 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3217 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3218 break; 3219 case MLX4_IB_QPT_UD: 3220 set_datagram_seg(wqe, wr); 3221 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3222 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3223 3224 if (wr->opcode == IB_WR_LSO) { 3225 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh); 3226 if (unlikely(err)) { 3227 *bad_wr = wr; 3228 goto out; 3229 } 3230 lso_wqe = (__be32 *) wqe; 3231 wqe += seglen; 3232 size += seglen / 16; 3233 } 3234 break; 3235 3236 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3237 if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) { 3238 err = -ENOSYS; 3239 *bad_wr = wr; 3240 goto out; 3241 } 3242 err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen); 3243 if (unlikely(err)) { 3244 *bad_wr = wr; 3245 goto out; 3246 } 3247 wqe += seglen; 3248 size += seglen / 16; 3249 /* to start tunnel header on a cache-line boundary */ 3250 add_zero_len_inline(wqe); 3251 wqe += 16; 3252 size++; 3253 build_tunnel_header(wr, wqe, &seglen); 3254 wqe += seglen; 3255 size += seglen / 16; 3256 break; 3257 case MLX4_IB_QPT_PROXY_SMI: 3258 /* don't allow QP0 sends on guests */ 3259 err = -ENOSYS; 3260 *bad_wr = wr; 3261 goto out; 3262 case MLX4_IB_QPT_PROXY_GSI: 3263 /* If we are tunneling special qps, this is a UD qp. 3264 * In this case we first add a UD segment targeting 3265 * the tunnel qp, and then add a header with address 3266 * information */ 3267 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type); 3268 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3269 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3270 build_tunnel_header(wr, wqe, &seglen); 3271 wqe += seglen; 3272 size += seglen / 16; 3273 break; 3274 3275 case MLX4_IB_QPT_SMI: 3276 case MLX4_IB_QPT_GSI: 3277 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen); 3278 if (unlikely(err)) { 3279 *bad_wr = wr; 3280 goto out; 3281 } 3282 wqe += seglen; 3283 size += seglen / 16; 3284 break; 3285 3286 default: 3287 break; 3288 } 3289 3290 /* 3291 * Write data segments in reverse order, so as to 3292 * overwrite cacheline stamp last within each 3293 * cacheline. This avoids issues with WQE 3294 * prefetching. 3295 */ 3296 dseg = wqe; 3297 dseg += wr->num_sge - 1; 3298 3299 /* Add one more inline data segment for ICRC for MLX sends */ 3300 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3301 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3302 qp->mlx4_ib_qp_type & 3303 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3304 set_mlx_icrc_seg(dseg + 1); 3305 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3306 } 3307 3308 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) { 3309 int sz; 3310 err = lay_inline_data(qp, wr, wqe, &sz); 3311 if (!err) { 3312 inl = 1; 3313 size += sz; 3314 } 3315 } else { 3316 size += wr->num_sge * 3317 (sizeof(struct mlx4_wqe_data_seg) / 16); 3318 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3319 set_data_seg(dseg, wr->sg_list + i); 3320 } 3321 3322 /* 3323 * Possibly overwrite stamping in cacheline with LSO 3324 * segment only after making sure all data segments 3325 * are written. 3326 */ 3327 wmb(); 3328 *lso_wqe = lso_hdr_sz; 3329 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? 3330 MLX4_WQE_CTRL_FENCE : 0) | size; 3331 3332 /* 3333 * Make sure descriptor is fully written before 3334 * setting ownership bit (because HW can start 3335 * executing as soon as we do). 3336 */ 3337 wmb(); 3338 3339 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3340 *bad_wr = wr; 3341 err = -EINVAL; 3342 goto out; 3343 } 3344 3345 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3346 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3347 3348 stamp = ind + qp->sq_spare_wqes; 3349 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 3350 3351 /* 3352 * We can improve latency by not stamping the last 3353 * send queue WQE until after ringing the doorbell, so 3354 * only stamp here if there are still more WQEs to post. 3355 * 3356 * Same optimization applies to padding with NOP wqe 3357 * in case of WQE shrinking (used to prevent wrap-around 3358 * in the middle of WR). 3359 */ 3360 if (wr->next) { 3361 stamp_send_wqe(qp, stamp, size * 16); 3362 ind = pad_wraparound(qp, ind); 3363 } 3364 } 3365 3366 out: 3367 if (nreq == 1 && inl && size > 1 && size < qp->bf.buf_size / 16) { 3368 ctrl->owner_opcode |= htonl((qp->sq_next_wqe & 0xffff) << 8); 3369 /* We set above doorbell_qpn bits to 0 as part of vlan 3370 * tag initialization, so |= should be correct. 3371 */ 3372 *(u32 *) (&ctrl->vlan_tag) |= qp->doorbell_qpn; 3373 /* 3374 * Make sure that descriptor is written to memory 3375 * before writing to BlueFlame page. 3376 */ 3377 wmb(); 3378 3379 ++qp->sq.head; 3380 3381 mlx4_bf_copy(qp->bf.reg + qp->bf.offset, (unsigned long *) ctrl, 3382 ALIGN(size * 16, 64)); 3383 wc_wmb(); 3384 3385 qp->bf.offset ^= qp->bf.buf_size; 3386 3387 } else if (nreq) { 3388 qp->sq.head += nreq; 3389 3390 /* 3391 * Make sure that descriptors are written before 3392 * doorbell record. 3393 */ 3394 wmb(); 3395 3396 writel(qp->doorbell_qpn, qp->bf.uar->map + MLX4_SEND_DOORBELL); 3397 3398 /* 3399 * Make sure doorbells don't leak out of SQ spinlock 3400 * and reach the HCA out of order. 3401 */ 3402 mmiowb(); 3403 3404 } 3405 3406 if (likely(nreq)) { 3407 stamp_send_wqe(qp, stamp, size * 16); 3408 ind = pad_wraparound(qp, ind); 3409 qp->sq_next_wqe = ind; 3410 } 3411 3412 spin_unlock_irqrestore(&qp->sq.lock, flags); 3413 3414 return err; 3415 } 3416 3417 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 3418 struct ib_recv_wr **bad_wr) 3419 { 3420 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3421 struct mlx4_wqe_data_seg *scat; 3422 unsigned long flags; 3423 int err = 0; 3424 int nreq; 3425 int ind; 3426 int max_gs; 3427 int i; 3428 3429 max_gs = qp->rq.max_gs; 3430 spin_lock_irqsave(&qp->rq.lock, flags); 3431 3432 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3433 3434 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3435 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3436 err = -ENOMEM; 3437 *bad_wr = wr; 3438 goto out; 3439 } 3440 3441 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3442 err = -EINVAL; 3443 *bad_wr = wr; 3444 goto out; 3445 } 3446 3447 scat = get_recv_wqe(qp, ind); 3448 3449 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3450 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3451 ib_dma_sync_single_for_device(ibqp->device, 3452 qp->sqp_proxy_rcv[ind].map, 3453 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3454 DMA_FROM_DEVICE); 3455 scat->byte_count = 3456 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3457 /* use dma lkey from upper layer entry */ 3458 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3459 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3460 scat++; 3461 max_gs--; 3462 } 3463 3464 for (i = 0; i < wr->num_sge; ++i) 3465 __set_data_seg(scat + i, wr->sg_list + i); 3466 3467 if (i < max_gs) { 3468 scat[i].byte_count = 0; 3469 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3470 scat[i].addr = 0; 3471 } 3472 3473 qp->rq.wrid[ind] = wr->wr_id; 3474 3475 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3476 } 3477 3478 out: 3479 if (likely(nreq)) { 3480 qp->rq.head += nreq; 3481 3482 /* 3483 * Make sure that descriptors are written before 3484 * doorbell record. 3485 */ 3486 wmb(); 3487 3488 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3489 } 3490 3491 spin_unlock_irqrestore(&qp->rq.lock, flags); 3492 3493 return err; 3494 } 3495 3496 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3497 { 3498 switch (mlx4_state) { 3499 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3500 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3501 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3502 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3503 case MLX4_QP_STATE_SQ_DRAINING: 3504 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3505 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3506 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3507 default: return -1; 3508 } 3509 } 3510 3511 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3512 { 3513 switch (mlx4_mig_state) { 3514 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3515 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3516 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3517 default: return -1; 3518 } 3519 } 3520 3521 static int to_ib_qp_access_flags(int mlx4_flags) 3522 { 3523 int ib_flags = 0; 3524 3525 if (mlx4_flags & MLX4_QP_BIT_RRE) 3526 ib_flags |= IB_ACCESS_REMOTE_READ; 3527 if (mlx4_flags & MLX4_QP_BIT_RWE) 3528 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3529 if (mlx4_flags & MLX4_QP_BIT_RAE) 3530 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3531 3532 return ib_flags; 3533 } 3534 3535 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 3536 struct mlx4_qp_path *path) 3537 { 3538 struct mlx4_dev *dev = ibdev->dev; 3539 int is_eth; 3540 3541 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 3542 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1; 3543 3544 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) 3545 return; 3546 3547 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) == 3548 IB_LINK_LAYER_ETHERNET; 3549 if (is_eth) 3550 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) | 3551 ((path->sched_queue & 4) << 1); 3552 else 3553 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf; 3554 3555 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3556 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f; 3557 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3558 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 3559 if (ib_ah_attr->ah_flags) { 3560 ib_ah_attr->grh.sgid_index = path->mgid_index; 3561 ib_ah_attr->grh.hop_limit = path->hop_limit; 3562 ib_ah_attr->grh.traffic_class = 3563 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3564 ib_ah_attr->grh.flow_label = 3565 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3566 memcpy(ib_ah_attr->grh.dgid.raw, 3567 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 3568 } 3569 } 3570 3571 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3572 struct ib_qp_init_attr *qp_init_attr) 3573 { 3574 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3575 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3576 struct mlx4_qp_context context; 3577 int mlx4_state; 3578 int err = 0; 3579 3580 mutex_lock(&qp->mutex); 3581 3582 if (qp->state == IB_QPS_RESET) { 3583 qp_attr->qp_state = IB_QPS_RESET; 3584 goto done; 3585 } 3586 3587 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3588 if (err) { 3589 err = -EINVAL; 3590 goto out; 3591 } 3592 3593 mlx4_state = be32_to_cpu(context.flags) >> 28; 3594 3595 qp->state = to_ib_qp_state(mlx4_state); 3596 qp_attr->qp_state = qp->state; 3597 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3598 qp_attr->path_mig_state = 3599 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3600 qp_attr->qkey = be32_to_cpu(context.qkey); 3601 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3602 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3603 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3604 qp_attr->qp_access_flags = 3605 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3606 3607 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3608 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3609 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3610 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3611 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3612 } 3613 3614 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3615 if (qp_attr->qp_state == IB_QPS_INIT) 3616 qp_attr->port_num = qp->port; 3617 else 3618 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3619 3620 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3621 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3622 3623 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3624 3625 qp_attr->max_dest_rd_atomic = 3626 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3627 qp_attr->min_rnr_timer = 3628 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 3629 qp_attr->timeout = context.pri_path.ackto >> 3; 3630 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 3631 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 3632 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 3633 3634 done: 3635 qp_attr->cur_qp_state = qp_attr->qp_state; 3636 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3637 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3638 3639 if (!ibqp->uobject) { 3640 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3641 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3642 } else { 3643 qp_attr->cap.max_send_wr = 0; 3644 qp_attr->cap.max_send_sge = 0; 3645 } 3646 3647 /* 3648 * We don't support inline sends for kernel QPs (yet), and we 3649 * don't know what userspace's value should be. 3650 */ 3651 qp_attr->cap.max_inline_data = 0; 3652 3653 qp_init_attr->cap = qp_attr->cap; 3654 3655 qp_init_attr->create_flags = 0; 3656 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3657 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3658 3659 if (qp->flags & MLX4_IB_QP_LSO) 3660 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 3661 3662 if (qp->flags & MLX4_IB_QP_NETIF) 3663 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 3664 3665 qp_init_attr->sq_sig_type = 3666 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 3667 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3668 3669 if (qp->flags & MLX4_IB_QP_CAP_CROSS_CHANNEL) 3670 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 3671 3672 if (qp->flags & MLX4_IB_QP_CAP_MANAGED_SEND) 3673 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 3674 3675 if (qp->flags & MLX4_IB_QP_CAP_MANAGED_RECV) 3676 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 3677 3678 qp_init_attr->qpg_type = ibqp->qpg_type; 3679 if (ibqp->qpg_type == IB_QPG_PARENT) 3680 qp_init_attr->cap.qpg_tss_mask_sz = qp->qpg_data->qpg_tss_mask_sz; 3681 else 3682 qp_init_attr->cap.qpg_tss_mask_sz = 0; 3683 3684 out: 3685 mutex_unlock(&qp->mutex); 3686 return err; 3687 } 3688