1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <dev/mlx4/cq.h> 35 #include <dev/mlx4/qp.h> 36 #include <dev/mlx4/srq.h> 37 #include <dev/mlx4/driver.h> 38 #include <linux/slab.h> 39 40 #include "mlx4_ib.h" 41 #include <rdma/mlx4-abi.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 45 { 46 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 47 ibcq->comp_handler(ibcq, ibcq->cq_context); 48 } 49 50 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 51 { 52 struct ib_event event; 53 struct ib_cq *ibcq; 54 55 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 56 pr_warn("Unexpected event type %d " 57 "on CQ %06x\n", type, cq->cqn); 58 return; 59 } 60 61 ibcq = &to_mibcq(cq)->ibcq; 62 if (ibcq->event_handler) { 63 event.device = ibcq->device; 64 event.event = IB_EVENT_CQ_ERR; 65 event.element.cq = ibcq; 66 ibcq->event_handler(&event, ibcq->cq_context); 67 } 68 } 69 70 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 71 { 72 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 73 } 74 75 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 76 { 77 return get_cqe_from_buf(&cq->buf, n); 78 } 79 80 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 81 { 82 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 83 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 84 85 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 86 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 87 } 88 89 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 90 { 91 return get_sw_cqe(cq, cq->mcq.cons_index); 92 } 93 94 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 95 { 96 struct mlx4_ib_cq *mcq = to_mcq(cq); 97 struct mlx4_ib_dev *dev = to_mdev(cq->device); 98 99 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 100 } 101 102 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 103 { 104 int err; 105 106 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 107 PAGE_SIZE * 2, &buf->buf, GFP_KERNEL); 108 109 if (err) 110 goto out; 111 112 buf->entry_size = dev->dev->caps.cqe_size; 113 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 114 &buf->mtt); 115 if (err) 116 goto err_buf; 117 118 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL); 119 if (err) 120 goto err_mtt; 121 122 return 0; 123 124 err_mtt: 125 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 126 127 err_buf: 128 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 129 130 out: 131 return err; 132 } 133 134 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 135 { 136 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 137 } 138 139 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_udata *udata, 140 struct mlx4_ib_cq_buf *buf, 141 struct ib_umem **umem, u64 buf_addr, int cqe) 142 { 143 int err; 144 int cqe_size = dev->dev->caps.cqe_size; 145 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 146 udata, struct mlx4_ib_ucontext, ibucontext); 147 148 *umem = ib_umem_get(&context->ibucontext, buf_addr, cqe * cqe_size, 149 IB_ACCESS_LOCAL_WRITE, 1); 150 if (IS_ERR(*umem)) 151 return PTR_ERR(*umem); 152 153 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem), 154 ilog2((*umem)->page_size), &buf->mtt); 155 if (err) 156 goto err_buf; 157 158 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); 159 if (err) 160 goto err_mtt; 161 162 return 0; 163 164 err_mtt: 165 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 166 167 err_buf: 168 ib_umem_release(*umem); 169 170 return err; 171 } 172 173 #define CQ_CREATE_FLAGS_SUPPORTED IB_CQ_FLAGS_TIMESTAMP_COMPLETION 174 int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 175 struct ib_udata *udata) 176 { 177 struct ib_device *ibdev = ibcq->device; 178 int entries = attr->cqe; 179 int vector = attr->comp_vector; 180 struct mlx4_ib_dev *dev = to_mdev(ibdev); 181 struct mlx4_ib_cq *cq = to_mcq(ibcq); 182 struct mlx4_uar *uar; 183 void *buf_addr; 184 int err; 185 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 186 udata, struct mlx4_ib_ucontext, ibucontext); 187 188 if (entries < 1 || entries > dev->dev->caps.max_cqes) 189 return -EINVAL; 190 191 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 192 return -EINVAL; 193 194 entries = roundup_pow_of_two(entries + 1); 195 cq->ibcq.cqe = entries - 1; 196 mutex_init(&cq->resize_mutex); 197 spin_lock_init(&cq->lock); 198 cq->resize_buf = NULL; 199 cq->resize_umem = NULL; 200 cq->create_flags = attr->flags; 201 INIT_LIST_HEAD(&cq->send_qp_list); 202 INIT_LIST_HEAD(&cq->recv_qp_list); 203 204 if (udata) { 205 struct mlx4_ib_create_cq ucmd; 206 207 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 208 err = -EFAULT; 209 goto err_cq; 210 } 211 212 buf_addr = (void *)(unsigned long)ucmd.buf_addr; 213 err = mlx4_ib_get_cq_umem(dev, udata, &cq->buf, &cq->umem, 214 ucmd.buf_addr, entries); 215 if (err) 216 goto err_cq; 217 218 err = mlx4_ib_db_map_user(context, ucmd.db_addr, &cq->db); 219 if (err) 220 goto err_mtt; 221 222 uar = &context->uar; 223 } else { 224 err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL); 225 if (err) 226 goto err_cq; 227 228 cq->mcq.set_ci_db = cq->db.db; 229 cq->mcq.arm_db = cq->db.db + 1; 230 *cq->mcq.set_ci_db = 0; 231 *cq->mcq.arm_db = 0; 232 233 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 234 if (err) 235 goto err_db; 236 237 buf_addr = &cq->buf.buf; 238 239 uar = &dev->priv_uar; 240 } 241 242 if (dev->eq_table) 243 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 244 245 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, 246 cq->db.dma, &cq->mcq, vector, 0, 247 !!(cq->create_flags & IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 248 if (err) 249 goto err_dbmap; 250 251 cq->mcq.comp = mlx4_ib_cq_comp; 252 cq->mcq.event = mlx4_ib_cq_event; 253 254 if (udata) 255 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { 256 err = -EFAULT; 257 goto err_cq_free; 258 } 259 260 return 0; 261 262 err_cq_free: 263 mlx4_cq_free(dev->dev, &cq->mcq); 264 265 err_dbmap: 266 if (udata) 267 mlx4_ib_db_unmap_user(context, &cq->db); 268 269 err_mtt: 270 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 271 272 ib_umem_release(cq->umem); 273 if (!udata) 274 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 275 276 err_db: 277 if (!udata) 278 mlx4_db_free(dev->dev, &cq->db); 279 err_cq: 280 return err; 281 } 282 283 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 284 int entries) 285 { 286 int err; 287 288 if (cq->resize_buf) 289 return -EBUSY; 290 291 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 292 if (!cq->resize_buf) 293 return -ENOMEM; 294 295 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 296 if (err) { 297 kfree(cq->resize_buf); 298 cq->resize_buf = NULL; 299 return err; 300 } 301 302 cq->resize_buf->cqe = entries - 1; 303 304 return 0; 305 } 306 307 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 308 int entries, struct ib_udata *udata) 309 { 310 struct mlx4_ib_resize_cq ucmd; 311 int err; 312 313 if (cq->resize_umem) 314 return -EBUSY; 315 316 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) 317 return -EFAULT; 318 319 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 320 if (!cq->resize_buf) 321 return -ENOMEM; 322 323 err = mlx4_ib_get_cq_umem(dev, udata, &cq->resize_buf->buf, 324 &cq->resize_umem, ucmd.buf_addr, entries); 325 if (err) { 326 kfree(cq->resize_buf); 327 cq->resize_buf = NULL; 328 return err; 329 } 330 331 cq->resize_buf->cqe = entries - 1; 332 333 return 0; 334 } 335 336 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 337 { 338 u32 i; 339 340 i = cq->mcq.cons_index; 341 while (get_sw_cqe(cq, i)) 342 ++i; 343 344 return i - cq->mcq.cons_index; 345 } 346 347 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 348 { 349 struct mlx4_cqe *cqe, *new_cqe; 350 int i; 351 int cqe_size = cq->buf.entry_size; 352 int cqe_inc = cqe_size == 64 ? 1 : 0; 353 354 i = cq->mcq.cons_index; 355 cqe = get_cqe(cq, i & cq->ibcq.cqe); 356 cqe += cqe_inc; 357 358 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 359 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 360 (i + 1) & cq->resize_buf->cqe); 361 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 362 new_cqe += cqe_inc; 363 364 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 365 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 366 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 367 cqe += cqe_inc; 368 } 369 ++cq->mcq.cons_index; 370 } 371 372 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 373 { 374 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 375 struct mlx4_ib_cq *cq = to_mcq(ibcq); 376 struct mlx4_mtt mtt; 377 int outst_cqe; 378 int err; 379 380 mutex_lock(&cq->resize_mutex); 381 if (entries < 1 || entries > dev->dev->caps.max_cqes) { 382 err = -EINVAL; 383 goto out; 384 } 385 386 entries = roundup_pow_of_two(entries + 1); 387 if (entries == ibcq->cqe + 1) { 388 err = 0; 389 goto out; 390 } 391 392 if (entries > dev->dev->caps.max_cqes + 1) { 393 err = -EINVAL; 394 goto out; 395 } 396 397 if (ibcq->uobject) { 398 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 399 if (err) 400 goto out; 401 } else { 402 /* Can't be smaller than the number of outstanding CQEs */ 403 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 404 if (entries < outst_cqe + 1) { 405 err = -EINVAL; 406 goto out; 407 } 408 409 err = mlx4_alloc_resize_buf(dev, cq, entries); 410 if (err) 411 goto out; 412 } 413 414 mtt = cq->buf.mtt; 415 416 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 417 if (err) 418 goto err_buf; 419 420 mlx4_mtt_cleanup(dev->dev, &mtt); 421 if (ibcq->uobject) { 422 cq->buf = cq->resize_buf->buf; 423 cq->ibcq.cqe = cq->resize_buf->cqe; 424 ib_umem_release(cq->umem); 425 cq->umem = cq->resize_umem; 426 427 kfree(cq->resize_buf); 428 cq->resize_buf = NULL; 429 cq->resize_umem = NULL; 430 } else { 431 struct mlx4_ib_cq_buf tmp_buf; 432 int tmp_cqe = 0; 433 434 spin_lock_irq(&cq->lock); 435 if (cq->resize_buf) { 436 mlx4_ib_cq_resize_copy_cqes(cq); 437 tmp_buf = cq->buf; 438 tmp_cqe = cq->ibcq.cqe; 439 cq->buf = cq->resize_buf->buf; 440 cq->ibcq.cqe = cq->resize_buf->cqe; 441 442 kfree(cq->resize_buf); 443 cq->resize_buf = NULL; 444 } 445 spin_unlock_irq(&cq->lock); 446 447 if (tmp_cqe) 448 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 449 } 450 451 goto out; 452 453 err_buf: 454 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 455 if (!ibcq->uobject) 456 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 457 cq->resize_buf->cqe); 458 459 kfree(cq->resize_buf); 460 cq->resize_buf = NULL; 461 462 ib_umem_release(cq->resize_umem); 463 cq->resize_umem = NULL; 464 out: 465 mutex_unlock(&cq->resize_mutex); 466 467 return err; 468 } 469 470 void mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 471 { 472 struct mlx4_ib_dev *dev = to_mdev(cq->device); 473 struct mlx4_ib_cq *mcq = to_mcq(cq); 474 475 mlx4_cq_free(dev->dev, &mcq->mcq); 476 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 477 478 if (udata) { 479 mlx4_ib_db_unmap_user( 480 rdma_udata_to_drv_context( 481 udata, 482 struct mlx4_ib_ucontext, 483 ibucontext), 484 &mcq->db); 485 } else { 486 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 487 mlx4_db_free(dev->dev, &mcq->db); 488 } 489 ib_umem_release(mcq->umem); 490 } 491 492 static void dump_cqe(void *cqe) 493 { 494 __be32 *buf = cqe; 495 496 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 497 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 498 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 499 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 500 } 501 502 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 503 struct ib_wc *wc) 504 { 505 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 506 pr_debug("local QP operation err " 507 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 508 "opcode = %02x)\n", 509 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 510 cqe->vendor_err_syndrome, 511 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 512 dump_cqe(cqe); 513 } 514 515 switch (cqe->syndrome) { 516 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 517 wc->status = IB_WC_LOC_LEN_ERR; 518 break; 519 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 520 wc->status = IB_WC_LOC_QP_OP_ERR; 521 break; 522 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 523 wc->status = IB_WC_LOC_PROT_ERR; 524 break; 525 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 526 wc->status = IB_WC_WR_FLUSH_ERR; 527 break; 528 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 529 wc->status = IB_WC_MW_BIND_ERR; 530 break; 531 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 532 wc->status = IB_WC_BAD_RESP_ERR; 533 break; 534 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 535 wc->status = IB_WC_LOC_ACCESS_ERR; 536 break; 537 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 538 wc->status = IB_WC_REM_INV_REQ_ERR; 539 break; 540 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 541 wc->status = IB_WC_REM_ACCESS_ERR; 542 break; 543 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 544 wc->status = IB_WC_REM_OP_ERR; 545 break; 546 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 547 wc->status = IB_WC_RETRY_EXC_ERR; 548 break; 549 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 550 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 551 break; 552 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 553 wc->status = IB_WC_REM_ABORT_ERR; 554 break; 555 default: 556 wc->status = IB_WC_GENERAL_ERR; 557 break; 558 } 559 560 wc->vendor_err = cqe->vendor_err_syndrome; 561 } 562 563 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) 564 { 565 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 566 MLX4_CQE_STATUS_IPV4F | 567 MLX4_CQE_STATUS_IPV4OPT | 568 MLX4_CQE_STATUS_IPV6 | 569 MLX4_CQE_STATUS_IPOK)) == 570 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 571 MLX4_CQE_STATUS_IPOK)) && 572 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | 573 MLX4_CQE_STATUS_TCP)) && 574 checksum == cpu_to_be16(0xffff); 575 } 576 577 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 578 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 579 { 580 struct mlx4_ib_proxy_sqp_hdr *hdr; 581 582 ib_dma_sync_single_for_cpu(qp->ibqp.device, 583 qp->sqp_proxy_rcv[tail].map, 584 sizeof (struct mlx4_ib_proxy_sqp_hdr), 585 DMA_FROM_DEVICE); 586 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 587 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 588 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 589 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 590 wc->dlid_path_bits = 0; 591 592 if (is_eth) { 593 wc->slid = 0; 594 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 595 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 596 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 597 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 598 } else { 599 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 600 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 601 } 602 } 603 604 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 605 struct ib_wc *wc, int *npolled, int is_send) 606 { 607 struct mlx4_ib_wq *wq; 608 unsigned cur; 609 int i; 610 611 wq = is_send ? &qp->sq : &qp->rq; 612 cur = wq->head - wq->tail; 613 614 if (cur == 0) 615 return; 616 617 for (i = 0; i < cur && *npolled < num_entries; i++) { 618 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 619 wc->status = IB_WC_WR_FLUSH_ERR; 620 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 621 wq->tail++; 622 (*npolled)++; 623 wc->qp = &qp->ibqp; 624 wc++; 625 } 626 } 627 628 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 629 struct ib_wc *wc, int *npolled) 630 { 631 struct mlx4_ib_qp *qp; 632 633 *npolled = 0; 634 /* Find uncompleted WQEs belonging to that cq and retrun 635 * simulated FLUSH_ERR completions 636 */ 637 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 638 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 639 if (*npolled >= num_entries) 640 goto out; 641 } 642 643 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 644 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 645 if (*npolled >= num_entries) 646 goto out; 647 } 648 649 out: 650 return; 651 } 652 653 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 654 struct mlx4_ib_qp **cur_qp, 655 struct ib_wc *wc) 656 { 657 struct mlx4_cqe *cqe; 658 struct mlx4_qp *mqp; 659 struct mlx4_ib_wq *wq; 660 struct mlx4_ib_srq *srq; 661 struct mlx4_srq *msrq = NULL; 662 int is_send; 663 int is_error; 664 int is_eth; 665 u32 g_mlpath_rqpn; 666 u16 wqe_ctr; 667 unsigned tail = 0; 668 669 repoll: 670 cqe = next_cqe_sw(cq); 671 if (!cqe) 672 return -EAGAIN; 673 674 if (cq->buf.entry_size == 64) 675 cqe++; 676 677 ++cq->mcq.cons_index; 678 679 /* 680 * Make sure we read CQ entry contents after we've checked the 681 * ownership bit. 682 */ 683 rmb(); 684 685 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 686 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 687 MLX4_CQE_OPCODE_ERROR; 688 689 /* Resize CQ in progress */ 690 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 691 if (cq->resize_buf) { 692 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 693 694 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 695 cq->buf = cq->resize_buf->buf; 696 cq->ibcq.cqe = cq->resize_buf->cqe; 697 698 kfree(cq->resize_buf); 699 cq->resize_buf = NULL; 700 } 701 702 goto repoll; 703 } 704 705 if (!*cur_qp || 706 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 707 /* 708 * We do not have to take the QP table lock here, 709 * because CQs will be locked while QPs are removed 710 * from the table. 711 */ 712 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 713 be32_to_cpu(cqe->vlan_my_qpn)); 714 *cur_qp = to_mibqp(mqp); 715 } 716 717 wc->qp = &(*cur_qp)->ibqp; 718 719 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 720 u32 srq_num; 721 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 722 srq_num = g_mlpath_rqpn & 0xffffff; 723 /* SRQ is also in the radix tree */ 724 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 725 srq_num); 726 } 727 728 if (is_send) { 729 wq = &(*cur_qp)->sq; 730 if (!(*cur_qp)->sq_signal_bits) { 731 wqe_ctr = be16_to_cpu(cqe->wqe_index); 732 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 733 } 734 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 735 ++wq->tail; 736 } else if ((*cur_qp)->ibqp.srq) { 737 srq = to_msrq((*cur_qp)->ibqp.srq); 738 wqe_ctr = be16_to_cpu(cqe->wqe_index); 739 wc->wr_id = srq->wrid[wqe_ctr]; 740 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 741 } else if (msrq) { 742 srq = to_mibsrq(msrq); 743 wqe_ctr = be16_to_cpu(cqe->wqe_index); 744 wc->wr_id = srq->wrid[wqe_ctr]; 745 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 746 } else { 747 wq = &(*cur_qp)->rq; 748 tail = wq->tail & (wq->wqe_cnt - 1); 749 wc->wr_id = wq->wrid[tail]; 750 ++wq->tail; 751 } 752 753 if (unlikely(is_error)) { 754 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 755 return 0; 756 } 757 758 wc->status = IB_WC_SUCCESS; 759 760 if (is_send) { 761 wc->wc_flags = 0; 762 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 763 case MLX4_OPCODE_RDMA_WRITE_IMM: 764 wc->wc_flags |= IB_WC_WITH_IMM; 765 case MLX4_OPCODE_RDMA_WRITE: 766 wc->opcode = IB_WC_RDMA_WRITE; 767 break; 768 case MLX4_OPCODE_SEND_IMM: 769 wc->wc_flags |= IB_WC_WITH_IMM; 770 case MLX4_OPCODE_SEND: 771 case MLX4_OPCODE_SEND_INVAL: 772 wc->opcode = IB_WC_SEND; 773 break; 774 case MLX4_OPCODE_RDMA_READ: 775 wc->opcode = IB_WC_RDMA_READ; 776 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 777 break; 778 case MLX4_OPCODE_ATOMIC_CS: 779 wc->opcode = IB_WC_COMP_SWAP; 780 wc->byte_len = 8; 781 break; 782 case MLX4_OPCODE_ATOMIC_FA: 783 wc->opcode = IB_WC_FETCH_ADD; 784 wc->byte_len = 8; 785 break; 786 case MLX4_OPCODE_MASKED_ATOMIC_CS: 787 wc->opcode = IB_WC_MASKED_COMP_SWAP; 788 wc->byte_len = 8; 789 break; 790 case MLX4_OPCODE_MASKED_ATOMIC_FA: 791 wc->opcode = IB_WC_MASKED_FETCH_ADD; 792 wc->byte_len = 8; 793 break; 794 case MLX4_OPCODE_LSO: 795 wc->opcode = IB_WC_LSO; 796 break; 797 case MLX4_OPCODE_FMR: 798 wc->opcode = IB_WC_REG_MR; 799 break; 800 case MLX4_OPCODE_LOCAL_INVAL: 801 wc->opcode = IB_WC_LOCAL_INV; 802 break; 803 } 804 } else { 805 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 806 807 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 808 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 809 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 810 wc->wc_flags = IB_WC_WITH_IMM; 811 wc->ex.imm_data = cqe->immed_rss_invalid; 812 break; 813 case MLX4_RECV_OPCODE_SEND_INVAL: 814 wc->opcode = IB_WC_RECV; 815 wc->wc_flags = IB_WC_WITH_INVALIDATE; 816 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 817 break; 818 case MLX4_RECV_OPCODE_SEND: 819 wc->opcode = IB_WC_RECV; 820 wc->wc_flags = 0; 821 break; 822 case MLX4_RECV_OPCODE_SEND_IMM: 823 wc->opcode = IB_WC_RECV; 824 wc->wc_flags = IB_WC_WITH_IMM; 825 wc->ex.imm_data = cqe->immed_rss_invalid; 826 break; 827 } 828 829 is_eth = (rdma_port_get_link_layer(wc->qp->device, 830 (*cur_qp)->port) == 831 IB_LINK_LAYER_ETHERNET); 832 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 833 if ((*cur_qp)->mlx4_ib_qp_type & 834 (MLX4_IB_QPT_PROXY_SMI_OWNER | 835 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 836 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 837 is_eth); 838 return 0; 839 } 840 } 841 842 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 843 wc->src_qp = g_mlpath_rqpn & 0xffffff; 844 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 845 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 846 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 847 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 848 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 849 if (is_eth) { 850 wc->slid = 0; 851 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 852 if (be32_to_cpu(cqe->vlan_my_qpn) & 853 MLX4_CQE_CVLAN_PRESENT_MASK) { 854 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 855 MLX4_CQE_VID_MASK; 856 } else { 857 wc->vlan_id = 0xffff; 858 } 859 memcpy(wc->smac, cqe->smac, ETH_ALEN); 860 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 861 } else { 862 wc->slid = be16_to_cpu(cqe->rlid); 863 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 864 wc->vlan_id = 0xffff; 865 } 866 } 867 868 return 0; 869 } 870 871 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 872 { 873 struct mlx4_ib_cq *cq = to_mcq(ibcq); 874 struct mlx4_ib_qp *cur_qp = NULL; 875 unsigned long flags; 876 int npolled; 877 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 878 879 spin_lock_irqsave(&cq->lock, flags); 880 if (unlikely(mdev->dev->persist->state & 881 MLX4_DEVICE_STATE_INTERNAL_ERROR)) { 882 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 883 goto out; 884 } 885 886 for (npolled = 0; npolled < num_entries; ++npolled) { 887 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 888 break; 889 } 890 891 mlx4_cq_set_ci(&cq->mcq); 892 893 out: 894 spin_unlock_irqrestore(&cq->lock, flags); 895 896 return npolled; 897 } 898 899 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 900 { 901 struct mlx4_ib_cq *cq = to_mcq(ibcq); 902 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 903 904 if (unlikely(mdev->dev->persist->state & 905 MLX4_DEVICE_STATE_INTERNAL_ERROR)) 906 return -1; 907 908 mlx4_cq_arm(&cq->mcq, 909 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 910 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 911 mdev->uar_map, 912 MLX4_GET_DOORBELL_LOCK(&mdev->uar_lock)); 913 914 return 0; 915 } 916 917 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 918 { 919 u32 prod_index; 920 int nfreed = 0; 921 struct mlx4_cqe *cqe, *dest; 922 u8 owner_bit; 923 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 924 925 /* 926 * First we need to find the current producer index, so we 927 * know where to start cleaning from. It doesn't matter if HW 928 * adds new entries after this loop -- the QP we're worried 929 * about is already in RESET, so the new entries won't come 930 * from our QP and therefore don't need to be checked. 931 */ 932 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 933 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 934 break; 935 936 /* 937 * Now sweep backwards through the CQ, removing CQ entries 938 * that match our QP by copying older entries on top of them. 939 */ 940 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 941 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 942 cqe += cqe_inc; 943 944 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 945 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 946 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 947 ++nfreed; 948 } else if (nfreed) { 949 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 950 dest += cqe_inc; 951 952 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 953 memcpy(dest, cqe, sizeof *cqe); 954 dest->owner_sr_opcode = owner_bit | 955 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 956 } 957 } 958 959 if (nfreed) { 960 cq->mcq.cons_index += nfreed; 961 /* 962 * Make sure update of buffer contents is done before 963 * updating consumer index. 964 */ 965 wmb(); 966 mlx4_cq_set_ci(&cq->mcq); 967 } 968 } 969 970 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 971 { 972 spin_lock_irq(&cq->lock); 973 __mlx4_ib_cq_clean(cq, qpn, srq); 974 spin_unlock_irq(&cq->lock); 975 } 976