1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <dev/mlx4/cq.h> 35 #include <dev/mlx4/qp.h> 36 #include <dev/mlx4/srq.h> 37 #include <dev/mlx4/driver.h> 38 #include <linux/slab.h> 39 40 #include "mlx4_ib.h" 41 #include <rdma/mlx4-abi.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 45 { 46 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 47 ibcq->comp_handler(ibcq, ibcq->cq_context); 48 } 49 50 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 51 { 52 struct ib_event event; 53 struct ib_cq *ibcq; 54 55 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 56 pr_warn("Unexpected event type %d " 57 "on CQ %06x\n", type, cq->cqn); 58 return; 59 } 60 61 ibcq = &to_mibcq(cq)->ibcq; 62 if (ibcq->event_handler) { 63 event.device = ibcq->device; 64 event.event = IB_EVENT_CQ_ERR; 65 event.element.cq = ibcq; 66 ibcq->event_handler(&event, ibcq->cq_context); 67 } 68 } 69 70 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 71 { 72 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 73 } 74 75 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 76 { 77 return get_cqe_from_buf(&cq->buf, n); 78 } 79 80 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 81 { 82 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 83 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 84 85 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 86 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 87 } 88 89 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 90 { 91 return get_sw_cqe(cq, cq->mcq.cons_index); 92 } 93 94 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 95 { 96 struct mlx4_ib_cq *mcq = to_mcq(cq); 97 struct mlx4_ib_dev *dev = to_mdev(cq->device); 98 99 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 100 } 101 102 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 103 { 104 int err; 105 106 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 107 PAGE_SIZE * 2, &buf->buf, GFP_KERNEL); 108 109 if (err) 110 goto out; 111 112 buf->entry_size = dev->dev->caps.cqe_size; 113 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 114 &buf->mtt); 115 if (err) 116 goto err_buf; 117 118 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL); 119 if (err) 120 goto err_mtt; 121 122 return 0; 123 124 err_mtt: 125 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 126 127 err_buf: 128 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 129 130 out: 131 return err; 132 } 133 134 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 135 { 136 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 137 } 138 139 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_udata *udata, 140 struct mlx4_ib_cq_buf *buf, 141 struct ib_umem **umem, u64 buf_addr, int cqe) 142 { 143 int err; 144 int cqe_size = dev->dev->caps.cqe_size; 145 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 146 udata, struct mlx4_ib_ucontext, ibucontext); 147 148 *umem = ib_umem_get(&context->ibucontext, buf_addr, cqe * cqe_size, 149 IB_ACCESS_LOCAL_WRITE, 1); 150 if (IS_ERR(*umem)) 151 return PTR_ERR(*umem); 152 153 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem), 154 ilog2((*umem)->page_size), &buf->mtt); 155 if (err) 156 goto err_buf; 157 158 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); 159 if (err) 160 goto err_mtt; 161 162 return 0; 163 164 err_mtt: 165 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 166 167 err_buf: 168 ib_umem_release(*umem); 169 170 return err; 171 } 172 173 #define CQ_CREATE_FLAGS_SUPPORTED IB_CQ_FLAGS_TIMESTAMP_COMPLETION 174 int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 175 struct ib_udata *udata) 176 { 177 struct ib_device *ibdev = ibcq->device; 178 int entries = attr->cqe; 179 int vector = attr->comp_vector; 180 struct mlx4_ib_dev *dev = to_mdev(ibdev); 181 struct mlx4_ib_cq *cq = to_mcq(ibcq); 182 struct mlx4_uar *uar; 183 int err; 184 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 185 udata, struct mlx4_ib_ucontext, ibucontext); 186 187 if (entries < 1 || entries > dev->dev->caps.max_cqes) 188 return -EINVAL; 189 190 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 191 return -EINVAL; 192 193 entries = roundup_pow_of_two(entries + 1); 194 cq->ibcq.cqe = entries - 1; 195 mutex_init(&cq->resize_mutex); 196 spin_lock_init(&cq->lock); 197 cq->resize_buf = NULL; 198 cq->resize_umem = NULL; 199 cq->create_flags = attr->flags; 200 INIT_LIST_HEAD(&cq->send_qp_list); 201 INIT_LIST_HEAD(&cq->recv_qp_list); 202 203 if (udata) { 204 struct mlx4_ib_create_cq ucmd; 205 206 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 207 err = -EFAULT; 208 goto err_cq; 209 } 210 211 err = mlx4_ib_get_cq_umem(dev, udata, &cq->buf, &cq->umem, 212 ucmd.buf_addr, entries); 213 if (err) 214 goto err_cq; 215 216 err = mlx4_ib_db_map_user(context, ucmd.db_addr, &cq->db); 217 if (err) 218 goto err_mtt; 219 220 uar = &context->uar; 221 } else { 222 err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL); 223 if (err) 224 goto err_cq; 225 226 cq->mcq.set_ci_db = cq->db.db; 227 cq->mcq.arm_db = cq->db.db + 1; 228 *cq->mcq.set_ci_db = 0; 229 *cq->mcq.arm_db = 0; 230 231 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 232 if (err) 233 goto err_db; 234 235 uar = &dev->priv_uar; 236 } 237 238 if (dev->eq_table) 239 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 240 241 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, 242 cq->db.dma, &cq->mcq, vector, 0, 243 !!(cq->create_flags & IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 244 if (err) 245 goto err_dbmap; 246 247 cq->mcq.comp = mlx4_ib_cq_comp; 248 cq->mcq.event = mlx4_ib_cq_event; 249 250 if (udata) 251 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { 252 err = -EFAULT; 253 goto err_cq_free; 254 } 255 256 return 0; 257 258 err_cq_free: 259 mlx4_cq_free(dev->dev, &cq->mcq); 260 261 err_dbmap: 262 if (udata) 263 mlx4_ib_db_unmap_user(context, &cq->db); 264 265 err_mtt: 266 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 267 268 ib_umem_release(cq->umem); 269 if (!udata) 270 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 271 272 err_db: 273 if (!udata) 274 mlx4_db_free(dev->dev, &cq->db); 275 err_cq: 276 return err; 277 } 278 279 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 280 int entries) 281 { 282 int err; 283 284 if (cq->resize_buf) 285 return -EBUSY; 286 287 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 288 if (!cq->resize_buf) 289 return -ENOMEM; 290 291 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 292 if (err) { 293 kfree(cq->resize_buf); 294 cq->resize_buf = NULL; 295 return err; 296 } 297 298 cq->resize_buf->cqe = entries - 1; 299 300 return 0; 301 } 302 303 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 304 int entries, struct ib_udata *udata) 305 { 306 struct mlx4_ib_resize_cq ucmd; 307 int err; 308 309 if (cq->resize_umem) 310 return -EBUSY; 311 312 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) 313 return -EFAULT; 314 315 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 316 if (!cq->resize_buf) 317 return -ENOMEM; 318 319 err = mlx4_ib_get_cq_umem(dev, udata, &cq->resize_buf->buf, 320 &cq->resize_umem, ucmd.buf_addr, entries); 321 if (err) { 322 kfree(cq->resize_buf); 323 cq->resize_buf = NULL; 324 return err; 325 } 326 327 cq->resize_buf->cqe = entries - 1; 328 329 return 0; 330 } 331 332 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 333 { 334 u32 i; 335 336 i = cq->mcq.cons_index; 337 while (get_sw_cqe(cq, i)) 338 ++i; 339 340 return i - cq->mcq.cons_index; 341 } 342 343 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 344 { 345 struct mlx4_cqe *cqe, *new_cqe; 346 int i; 347 int cqe_size = cq->buf.entry_size; 348 int cqe_inc = cqe_size == 64 ? 1 : 0; 349 350 i = cq->mcq.cons_index; 351 cqe = get_cqe(cq, i & cq->ibcq.cqe); 352 cqe += cqe_inc; 353 354 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 355 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 356 (i + 1) & cq->resize_buf->cqe); 357 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 358 new_cqe += cqe_inc; 359 360 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 361 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 362 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 363 cqe += cqe_inc; 364 } 365 ++cq->mcq.cons_index; 366 } 367 368 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 369 { 370 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 371 struct mlx4_ib_cq *cq = to_mcq(ibcq); 372 struct mlx4_mtt mtt; 373 int outst_cqe; 374 int err; 375 376 mutex_lock(&cq->resize_mutex); 377 if (entries < 1 || entries > dev->dev->caps.max_cqes) { 378 err = -EINVAL; 379 goto out; 380 } 381 382 entries = roundup_pow_of_two(entries + 1); 383 if (entries == ibcq->cqe + 1) { 384 err = 0; 385 goto out; 386 } 387 388 if (entries > dev->dev->caps.max_cqes + 1) { 389 err = -EINVAL; 390 goto out; 391 } 392 393 if (ibcq->uobject) { 394 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 395 if (err) 396 goto out; 397 } else { 398 /* Can't be smaller than the number of outstanding CQEs */ 399 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 400 if (entries < outst_cqe + 1) { 401 err = -EINVAL; 402 goto out; 403 } 404 405 err = mlx4_alloc_resize_buf(dev, cq, entries); 406 if (err) 407 goto out; 408 } 409 410 mtt = cq->buf.mtt; 411 412 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 413 if (err) 414 goto err_buf; 415 416 mlx4_mtt_cleanup(dev->dev, &mtt); 417 if (ibcq->uobject) { 418 cq->buf = cq->resize_buf->buf; 419 cq->ibcq.cqe = cq->resize_buf->cqe; 420 ib_umem_release(cq->umem); 421 cq->umem = cq->resize_umem; 422 423 kfree(cq->resize_buf); 424 cq->resize_buf = NULL; 425 cq->resize_umem = NULL; 426 } else { 427 struct mlx4_ib_cq_buf tmp_buf; 428 int tmp_cqe = 0; 429 430 spin_lock_irq(&cq->lock); 431 if (cq->resize_buf) { 432 mlx4_ib_cq_resize_copy_cqes(cq); 433 tmp_buf = cq->buf; 434 tmp_cqe = cq->ibcq.cqe; 435 cq->buf = cq->resize_buf->buf; 436 cq->ibcq.cqe = cq->resize_buf->cqe; 437 438 kfree(cq->resize_buf); 439 cq->resize_buf = NULL; 440 } 441 spin_unlock_irq(&cq->lock); 442 443 if (tmp_cqe) 444 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 445 } 446 447 goto out; 448 449 err_buf: 450 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 451 if (!ibcq->uobject) 452 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 453 cq->resize_buf->cqe); 454 455 kfree(cq->resize_buf); 456 cq->resize_buf = NULL; 457 458 ib_umem_release(cq->resize_umem); 459 cq->resize_umem = NULL; 460 out: 461 mutex_unlock(&cq->resize_mutex); 462 463 return err; 464 } 465 466 void mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 467 { 468 struct mlx4_ib_dev *dev = to_mdev(cq->device); 469 struct mlx4_ib_cq *mcq = to_mcq(cq); 470 471 mlx4_cq_free(dev->dev, &mcq->mcq); 472 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 473 474 if (udata) { 475 mlx4_ib_db_unmap_user( 476 rdma_udata_to_drv_context( 477 udata, 478 struct mlx4_ib_ucontext, 479 ibucontext), 480 &mcq->db); 481 } else { 482 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 483 mlx4_db_free(dev->dev, &mcq->db); 484 } 485 ib_umem_release(mcq->umem); 486 } 487 488 static void dump_cqe(void *cqe) 489 { 490 __be32 *buf = cqe; 491 492 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 493 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 494 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 495 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 496 } 497 498 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 499 struct ib_wc *wc) 500 { 501 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 502 pr_debug("local QP operation err " 503 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 504 "opcode = %02x)\n", 505 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 506 cqe->vendor_err_syndrome, 507 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 508 dump_cqe(cqe); 509 } 510 511 switch (cqe->syndrome) { 512 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 513 wc->status = IB_WC_LOC_LEN_ERR; 514 break; 515 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 516 wc->status = IB_WC_LOC_QP_OP_ERR; 517 break; 518 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 519 wc->status = IB_WC_LOC_PROT_ERR; 520 break; 521 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 522 wc->status = IB_WC_WR_FLUSH_ERR; 523 break; 524 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 525 wc->status = IB_WC_MW_BIND_ERR; 526 break; 527 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 528 wc->status = IB_WC_BAD_RESP_ERR; 529 break; 530 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 531 wc->status = IB_WC_LOC_ACCESS_ERR; 532 break; 533 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 534 wc->status = IB_WC_REM_INV_REQ_ERR; 535 break; 536 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 537 wc->status = IB_WC_REM_ACCESS_ERR; 538 break; 539 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 540 wc->status = IB_WC_REM_OP_ERR; 541 break; 542 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 543 wc->status = IB_WC_RETRY_EXC_ERR; 544 break; 545 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 546 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 547 break; 548 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 549 wc->status = IB_WC_REM_ABORT_ERR; 550 break; 551 default: 552 wc->status = IB_WC_GENERAL_ERR; 553 break; 554 } 555 556 wc->vendor_err = cqe->vendor_err_syndrome; 557 } 558 559 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) 560 { 561 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 562 MLX4_CQE_STATUS_IPV4F | 563 MLX4_CQE_STATUS_IPV4OPT | 564 MLX4_CQE_STATUS_IPV6 | 565 MLX4_CQE_STATUS_IPOK)) == 566 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 567 MLX4_CQE_STATUS_IPOK)) && 568 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | 569 MLX4_CQE_STATUS_TCP)) && 570 checksum == cpu_to_be16(0xffff); 571 } 572 573 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 574 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 575 { 576 struct mlx4_ib_proxy_sqp_hdr *hdr; 577 578 ib_dma_sync_single_for_cpu(qp->ibqp.device, 579 qp->sqp_proxy_rcv[tail].map, 580 sizeof (struct mlx4_ib_proxy_sqp_hdr), 581 DMA_FROM_DEVICE); 582 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 583 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 584 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 585 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 586 wc->dlid_path_bits = 0; 587 588 if (is_eth) { 589 wc->slid = 0; 590 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 591 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 592 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 593 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 594 } else { 595 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 596 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 597 } 598 } 599 600 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 601 struct ib_wc *wc, int *npolled, int is_send) 602 { 603 struct mlx4_ib_wq *wq; 604 unsigned cur; 605 int i; 606 607 wq = is_send ? &qp->sq : &qp->rq; 608 cur = wq->head - wq->tail; 609 610 if (cur == 0) 611 return; 612 613 for (i = 0; i < cur && *npolled < num_entries; i++) { 614 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 615 wc->status = IB_WC_WR_FLUSH_ERR; 616 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 617 wq->tail++; 618 (*npolled)++; 619 wc->qp = &qp->ibqp; 620 wc++; 621 } 622 } 623 624 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 625 struct ib_wc *wc, int *npolled) 626 { 627 struct mlx4_ib_qp *qp; 628 629 *npolled = 0; 630 /* Find uncompleted WQEs belonging to that cq and retrun 631 * simulated FLUSH_ERR completions 632 */ 633 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 634 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 635 if (*npolled >= num_entries) 636 goto out; 637 } 638 639 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 640 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 641 if (*npolled >= num_entries) 642 goto out; 643 } 644 645 out: 646 return; 647 } 648 649 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 650 struct mlx4_ib_qp **cur_qp, 651 struct ib_wc *wc) 652 { 653 struct mlx4_cqe *cqe; 654 struct mlx4_qp *mqp; 655 struct mlx4_ib_wq *wq; 656 struct mlx4_ib_srq *srq; 657 struct mlx4_srq *msrq = NULL; 658 int is_send; 659 int is_error; 660 int is_eth; 661 u32 g_mlpath_rqpn; 662 u16 wqe_ctr; 663 unsigned tail = 0; 664 665 repoll: 666 cqe = next_cqe_sw(cq); 667 if (!cqe) 668 return -EAGAIN; 669 670 if (cq->buf.entry_size == 64) 671 cqe++; 672 673 ++cq->mcq.cons_index; 674 675 /* 676 * Make sure we read CQ entry contents after we've checked the 677 * ownership bit. 678 */ 679 rmb(); 680 681 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 682 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 683 MLX4_CQE_OPCODE_ERROR; 684 685 /* Resize CQ in progress */ 686 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 687 if (cq->resize_buf) { 688 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 689 690 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 691 cq->buf = cq->resize_buf->buf; 692 cq->ibcq.cqe = cq->resize_buf->cqe; 693 694 kfree(cq->resize_buf); 695 cq->resize_buf = NULL; 696 } 697 698 goto repoll; 699 } 700 701 if (!*cur_qp || 702 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 703 /* 704 * We do not have to take the QP table lock here, 705 * because CQs will be locked while QPs are removed 706 * from the table. 707 */ 708 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 709 be32_to_cpu(cqe->vlan_my_qpn)); 710 *cur_qp = to_mibqp(mqp); 711 } 712 713 wc->qp = &(*cur_qp)->ibqp; 714 715 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 716 u32 srq_num; 717 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 718 srq_num = g_mlpath_rqpn & 0xffffff; 719 /* SRQ is also in the radix tree */ 720 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 721 srq_num); 722 } 723 724 if (is_send) { 725 wq = &(*cur_qp)->sq; 726 if (!(*cur_qp)->sq_signal_bits) { 727 wqe_ctr = be16_to_cpu(cqe->wqe_index); 728 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 729 } 730 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 731 ++wq->tail; 732 } else if ((*cur_qp)->ibqp.srq) { 733 srq = to_msrq((*cur_qp)->ibqp.srq); 734 wqe_ctr = be16_to_cpu(cqe->wqe_index); 735 wc->wr_id = srq->wrid[wqe_ctr]; 736 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 737 } else if (msrq) { 738 srq = to_mibsrq(msrq); 739 wqe_ctr = be16_to_cpu(cqe->wqe_index); 740 wc->wr_id = srq->wrid[wqe_ctr]; 741 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 742 } else { 743 wq = &(*cur_qp)->rq; 744 tail = wq->tail & (wq->wqe_cnt - 1); 745 wc->wr_id = wq->wrid[tail]; 746 ++wq->tail; 747 } 748 749 if (unlikely(is_error)) { 750 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 751 return 0; 752 } 753 754 wc->status = IB_WC_SUCCESS; 755 756 if (is_send) { 757 wc->wc_flags = 0; 758 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 759 case MLX4_OPCODE_RDMA_WRITE_IMM: 760 wc->wc_flags |= IB_WC_WITH_IMM; 761 case MLX4_OPCODE_RDMA_WRITE: 762 wc->opcode = IB_WC_RDMA_WRITE; 763 break; 764 case MLX4_OPCODE_SEND_IMM: 765 wc->wc_flags |= IB_WC_WITH_IMM; 766 case MLX4_OPCODE_SEND: 767 case MLX4_OPCODE_SEND_INVAL: 768 wc->opcode = IB_WC_SEND; 769 break; 770 case MLX4_OPCODE_RDMA_READ: 771 wc->opcode = IB_WC_RDMA_READ; 772 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 773 break; 774 case MLX4_OPCODE_ATOMIC_CS: 775 wc->opcode = IB_WC_COMP_SWAP; 776 wc->byte_len = 8; 777 break; 778 case MLX4_OPCODE_ATOMIC_FA: 779 wc->opcode = IB_WC_FETCH_ADD; 780 wc->byte_len = 8; 781 break; 782 case MLX4_OPCODE_MASKED_ATOMIC_CS: 783 wc->opcode = IB_WC_MASKED_COMP_SWAP; 784 wc->byte_len = 8; 785 break; 786 case MLX4_OPCODE_MASKED_ATOMIC_FA: 787 wc->opcode = IB_WC_MASKED_FETCH_ADD; 788 wc->byte_len = 8; 789 break; 790 case MLX4_OPCODE_LSO: 791 wc->opcode = IB_WC_LSO; 792 break; 793 case MLX4_OPCODE_FMR: 794 wc->opcode = IB_WC_REG_MR; 795 break; 796 case MLX4_OPCODE_LOCAL_INVAL: 797 wc->opcode = IB_WC_LOCAL_INV; 798 break; 799 } 800 } else { 801 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 802 803 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 804 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 805 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 806 wc->wc_flags = IB_WC_WITH_IMM; 807 wc->ex.imm_data = cqe->immed_rss_invalid; 808 break; 809 case MLX4_RECV_OPCODE_SEND_INVAL: 810 wc->opcode = IB_WC_RECV; 811 wc->wc_flags = IB_WC_WITH_INVALIDATE; 812 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 813 break; 814 case MLX4_RECV_OPCODE_SEND: 815 wc->opcode = IB_WC_RECV; 816 wc->wc_flags = 0; 817 break; 818 case MLX4_RECV_OPCODE_SEND_IMM: 819 wc->opcode = IB_WC_RECV; 820 wc->wc_flags = IB_WC_WITH_IMM; 821 wc->ex.imm_data = cqe->immed_rss_invalid; 822 break; 823 } 824 825 is_eth = (rdma_port_get_link_layer(wc->qp->device, 826 (*cur_qp)->port) == 827 IB_LINK_LAYER_ETHERNET); 828 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 829 if ((*cur_qp)->mlx4_ib_qp_type & 830 (MLX4_IB_QPT_PROXY_SMI_OWNER | 831 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 832 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 833 is_eth); 834 return 0; 835 } 836 } 837 838 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 839 wc->src_qp = g_mlpath_rqpn & 0xffffff; 840 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 841 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 842 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 843 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 844 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 845 if (is_eth) { 846 wc->slid = 0; 847 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 848 if (be32_to_cpu(cqe->vlan_my_qpn) & 849 MLX4_CQE_CVLAN_PRESENT_MASK) { 850 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 851 MLX4_CQE_VID_MASK; 852 } else { 853 wc->vlan_id = 0xffff; 854 } 855 memcpy(wc->smac, cqe->smac, ETH_ALEN); 856 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 857 } else { 858 wc->slid = be16_to_cpu(cqe->rlid); 859 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 860 wc->vlan_id = 0xffff; 861 } 862 } 863 864 return 0; 865 } 866 867 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 868 { 869 struct mlx4_ib_cq *cq = to_mcq(ibcq); 870 struct mlx4_ib_qp *cur_qp = NULL; 871 unsigned long flags; 872 int npolled; 873 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 874 875 spin_lock_irqsave(&cq->lock, flags); 876 if (unlikely(mdev->dev->persist->state & 877 MLX4_DEVICE_STATE_INTERNAL_ERROR)) { 878 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 879 goto out; 880 } 881 882 for (npolled = 0; npolled < num_entries; ++npolled) { 883 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 884 break; 885 } 886 887 mlx4_cq_set_ci(&cq->mcq); 888 889 out: 890 spin_unlock_irqrestore(&cq->lock, flags); 891 892 return npolled; 893 } 894 895 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 896 { 897 struct mlx4_ib_cq *cq = to_mcq(ibcq); 898 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 899 900 if (unlikely(mdev->dev->persist->state & 901 MLX4_DEVICE_STATE_INTERNAL_ERROR)) 902 return -1; 903 904 mlx4_cq_arm(&cq->mcq, 905 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 906 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 907 mdev->uar_map, 908 MLX4_GET_DOORBELL_LOCK(&mdev->uar_lock)); 909 910 return 0; 911 } 912 913 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 914 { 915 u32 prod_index; 916 int nfreed = 0; 917 struct mlx4_cqe *cqe, *dest; 918 u8 owner_bit; 919 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 920 921 /* 922 * First we need to find the current producer index, so we 923 * know where to start cleaning from. It doesn't matter if HW 924 * adds new entries after this loop -- the QP we're worried 925 * about is already in RESET, so the new entries won't come 926 * from our QP and therefore don't need to be checked. 927 */ 928 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 929 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 930 break; 931 932 /* 933 * Now sweep backwards through the CQ, removing CQ entries 934 * that match our QP by copying older entries on top of them. 935 */ 936 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 937 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 938 cqe += cqe_inc; 939 940 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 941 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 942 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 943 ++nfreed; 944 } else if (nfreed) { 945 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 946 dest += cqe_inc; 947 948 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 949 memcpy(dest, cqe, sizeof *cqe); 950 dest->owner_sr_opcode = owner_bit | 951 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 952 } 953 } 954 955 if (nfreed) { 956 cq->mcq.cons_index += nfreed; 957 /* 958 * Make sure update of buffer contents is done before 959 * updating consumer index. 960 */ 961 wmb(); 962 mlx4_cq_set_ci(&cq->mcq); 963 } 964 } 965 966 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 967 { 968 spin_lock_irq(&cq->lock); 969 __mlx4_ib_cq_clean(cq, qpn, srq); 970 spin_unlock_irq(&cq->lock); 971 } 972