xref: /freebsd/sys/dev/mlx4/mlx4_en/mlx4_en_tx.c (revision 56e53cb8ef000c3ef72337a4095987a932cdedef)
1 /*
2  * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #define	LINUXKPI_PARAM_PREFIX mlx4_
35 
36 #include <linux/page.h>
37 #include <dev/mlx4/cq.h>
38 #include <linux/slab.h>
39 #include <dev/mlx4/qp.h>
40 #include <linux/if_vlan.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 
44 #include <netinet/in_systm.h>
45 #include <netinet/in.h>
46 #include <netinet/if_ether.h>
47 #include <netinet/ip.h>
48 #include <netinet/ip6.h>
49 #include <netinet/tcp.h>
50 #include <netinet/tcp_lro.h>
51 #include <netinet/udp.h>
52 
53 #include "en.h"
54 
55 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
56 			   struct mlx4_en_tx_ring **pring, u32 size,
57 			   u16 stride, int node, int queue_idx)
58 {
59 	struct mlx4_en_dev *mdev = priv->mdev;
60 	struct mlx4_en_tx_ring *ring;
61 	uint32_t x;
62 	int tmp;
63 	int err;
64 
65 	ring = kzalloc_node(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL, node);
66 	if (!ring) {
67 		ring = kzalloc(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL);
68 		if (!ring) {
69 			en_err(priv, "Failed allocating TX ring\n");
70 			return -ENOMEM;
71 		}
72 	}
73 
74 	/* Create DMA descriptor TAG */
75 	if ((err = -bus_dma_tag_create(
76 	    bus_get_dma_tag(mdev->pdev->dev.bsddev),
77 	    1,					/* any alignment */
78 	    0,					/* no boundary */
79 	    BUS_SPACE_MAXADDR,			/* lowaddr */
80 	    BUS_SPACE_MAXADDR,			/* highaddr */
81 	    NULL, NULL,				/* filter, filterarg */
82 	    MLX4_EN_TX_MAX_PAYLOAD_SIZE,	/* maxsize */
83 	    MLX4_EN_TX_MAX_MBUF_FRAGS,		/* nsegments */
84 	    MLX4_EN_TX_MAX_MBUF_SIZE,		/* maxsegsize */
85 	    0,					/* flags */
86 	    NULL, NULL,				/* lockfunc, lockfuncarg */
87 	    &ring->dma_tag)))
88 		goto done;
89 
90 	ring->size = size;
91 	ring->size_mask = size - 1;
92 	ring->stride = stride;
93 	ring->inline_thold = MAX(MIN_PKT_LEN, MIN(priv->prof->inline_thold, MAX_INLINE));
94 	mtx_init(&ring->tx_lock.m, "mlx4 tx", NULL, MTX_DEF);
95 	mtx_init(&ring->comp_lock.m, "mlx4 comp", NULL, MTX_DEF);
96 
97 	/* Allocate the buf ring */
98 	ring->br = buf_ring_alloc(MLX4_EN_DEF_TX_QUEUE_SIZE, M_DEVBUF,
99 		M_WAITOK, &ring->tx_lock.m);
100 	if (ring->br == NULL) {
101 		en_err(priv, "Failed allocating tx_info ring\n");
102 		err = -ENOMEM;
103 		goto err_free_dma_tag;
104 	}
105 
106 	tmp = size * sizeof(struct mlx4_en_tx_info);
107 	ring->tx_info = kzalloc_node(tmp, GFP_KERNEL, node);
108 	if (!ring->tx_info) {
109 		ring->tx_info = kzalloc(tmp, GFP_KERNEL);
110 		if (!ring->tx_info) {
111 			err = -ENOMEM;
112 			goto err_ring;
113 		}
114 	}
115 
116 	/* Create DMA descriptor MAPs */
117 	for (x = 0; x != size; x++) {
118 		err = -bus_dmamap_create(ring->dma_tag, 0,
119 		    &ring->tx_info[x].dma_map);
120 		if (err != 0) {
121 			while (x--) {
122 				bus_dmamap_destroy(ring->dma_tag,
123 				    ring->tx_info[x].dma_map);
124 			}
125 			goto err_info;
126 		}
127 	}
128 
129 	en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
130 		 ring->tx_info, tmp);
131 
132 	ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
133 
134 	/* Allocate HW buffers on provided NUMA node */
135 	err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
136 				 2 * PAGE_SIZE);
137 	if (err) {
138 		en_err(priv, "Failed allocating hwq resources\n");
139 		goto err_dma_map;
140 	}
141 
142 	err = mlx4_en_map_buffer(&ring->wqres.buf);
143 	if (err) {
144 		en_err(priv, "Failed to map TX buffer\n");
145 		goto err_hwq_res;
146 	}
147 
148 	ring->buf = ring->wqres.buf.direct.buf;
149 
150 	en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
151 	       "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
152 	       ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
153 
154 	err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
155 				    MLX4_RESERVE_ETH_BF_QP);
156 	if (err) {
157 		en_err(priv, "failed reserving qp for TX ring\n");
158 		goto err_map;
159 	}
160 
161 	err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
162 	if (err) {
163 		en_err(priv, "Failed allocating qp %d\n", ring->qpn);
164 		goto err_reserve;
165 	}
166 	ring->qp.event = mlx4_en_sqp_event;
167 
168 	err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
169 	if (err) {
170 		en_dbg(DRV, priv, "working without blueflame (%d)", err);
171 		ring->bf.uar = &mdev->priv_uar;
172 		ring->bf.uar->map = mdev->uar_map;
173 		ring->bf_enabled = false;
174 	} else
175 		ring->bf_enabled = true;
176 	ring->queue_index = queue_idx;
177 
178 	*pring = ring;
179 	return 0;
180 
181 err_reserve:
182 	mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
183 err_map:
184 	mlx4_en_unmap_buffer(&ring->wqres.buf);
185 err_hwq_res:
186 	mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
187 err_dma_map:
188 	for (x = 0; x != size; x++)
189 		bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
190 err_info:
191 	vfree(ring->tx_info);
192 err_ring:
193 	buf_ring_free(ring->br, M_DEVBUF);
194 err_free_dma_tag:
195 	bus_dma_tag_destroy(ring->dma_tag);
196 done:
197 	kfree(ring);
198 	return err;
199 }
200 
201 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
202 			     struct mlx4_en_tx_ring **pring)
203 {
204 	struct mlx4_en_dev *mdev = priv->mdev;
205 	struct mlx4_en_tx_ring *ring = *pring;
206 	uint32_t x;
207 	en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
208 
209 	buf_ring_free(ring->br, M_DEVBUF);
210 	if (ring->bf_enabled)
211 		mlx4_bf_free(mdev->dev, &ring->bf);
212 	mlx4_qp_remove(mdev->dev, &ring->qp);
213 	mlx4_qp_free(mdev->dev, &ring->qp);
214 	mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
215 	mlx4_en_unmap_buffer(&ring->wqres.buf);
216 	mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
217 	for (x = 0; x != ring->size; x++)
218 		bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
219 	vfree(ring->tx_info);
220 	mtx_destroy(&ring->tx_lock.m);
221 	mtx_destroy(&ring->comp_lock.m);
222 	bus_dma_tag_destroy(ring->dma_tag);
223 	kfree(ring);
224 	*pring = NULL;
225 }
226 
227 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
228 			     struct mlx4_en_tx_ring *ring,
229 			     int cq, int user_prio)
230 {
231 	struct mlx4_en_dev *mdev = priv->mdev;
232 	int err;
233 
234 	ring->cqn = cq;
235 	ring->prod = 0;
236 	ring->cons = 0xffffffff;
237 	ring->last_nr_txbb = 1;
238 	ring->poll_cnt = 0;
239 	ring->blocked = 0;
240 	memset(ring->buf, 0, ring->buf_size);
241 
242 	ring->qp_state = MLX4_QP_STATE_RST;
243 	ring->doorbell_qpn = ring->qp.qpn << 8;
244 
245 	mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
246 				ring->cqn, user_prio, &ring->context);
247 	if (ring->bf_enabled)
248 		ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
249 
250 	err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
251 			       &ring->qp, &ring->qp_state);
252 	return err;
253 }
254 
255 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
256 				struct mlx4_en_tx_ring *ring)
257 {
258 	struct mlx4_en_dev *mdev = priv->mdev;
259 
260 	mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
261 		       MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
262 }
263 
264 static volatile struct mlx4_wqe_data_seg *
265 mlx4_en_store_inline_lso_data(volatile struct mlx4_wqe_data_seg *dseg,
266     struct mbuf *mb, int len, __be32 owner_bit)
267 {
268 	uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
269 
270 	/* copy data into place */
271 	m_copydata(mb, 0, len, inl + 4);
272 	dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
273 	return (dseg);
274 }
275 
276 static void
277 mlx4_en_store_inline_lso_header(volatile struct mlx4_wqe_data_seg *dseg,
278     int len, __be32 owner_bit)
279 {
280 }
281 
282 static void
283 mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
284     struct mlx4_en_tx_ring *ring, u32 index, u8 owner)
285 {
286 	struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
287 	struct mlx4_en_tx_desc *tx_desc = (struct mlx4_en_tx_desc *)
288 	    (ring->buf + (index * TXBB_SIZE));
289 	volatile __be32 *ptr = (__be32 *)tx_desc;
290 	const __be32 stamp = cpu_to_be32(STAMP_VAL |
291 	    ((u32)owner << STAMP_SHIFT));
292 	u32 i;
293 
294 	/* Stamp the freed descriptor */
295 	for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
296 		*ptr = stamp;
297 		ptr += STAMP_DWORDS;
298 	}
299 }
300 
301 static u32
302 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
303     struct mlx4_en_tx_ring *ring, u32 index)
304 {
305 	struct mlx4_en_tx_info *tx_info;
306 	struct mbuf *mb;
307 
308 	tx_info = &ring->tx_info[index];
309 	mb = tx_info->mb;
310 
311 	if (mb == NULL)
312 		goto done;
313 
314 	bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
315 	    BUS_DMASYNC_POSTWRITE);
316 	bus_dmamap_unload(ring->dma_tag, tx_info->dma_map);
317 
318         m_freem(mb);
319 done:
320 	return (tx_info->nr_txbb);
321 }
322 
323 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
324 {
325 	struct mlx4_en_priv *priv = netdev_priv(dev);
326 	int cnt = 0;
327 
328 	/* Skip last polled descriptor */
329 	ring->cons += ring->last_nr_txbb;
330 	en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
331 		 ring->cons, ring->prod);
332 
333 	if ((u32) (ring->prod - ring->cons) > ring->size) {
334                 en_warn(priv, "Tx consumer passed producer!\n");
335 		return 0;
336 	}
337 
338 	while (ring->cons != ring->prod) {
339 		ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
340 		    ring->cons & ring->size_mask);
341 		ring->cons += ring->last_nr_txbb;
342 		cnt++;
343 	}
344 
345 	if (cnt)
346 		en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
347 
348 	return cnt;
349 }
350 
351 static bool
352 mlx4_en_tx_ring_is_full(struct mlx4_en_tx_ring *ring)
353 {
354 	int wqs;
355 	wqs = ring->size - (ring->prod - ring->cons);
356 	return (wqs < (HEADROOM + (2 * MLX4_EN_TX_WQE_MAX_WQEBBS)));
357 }
358 
359 static int mlx4_en_process_tx_cq(struct net_device *dev,
360 				 struct mlx4_en_cq *cq)
361 {
362 	struct mlx4_en_priv *priv = netdev_priv(dev);
363 	struct mlx4_cq *mcq = &cq->mcq;
364 	struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
365 	struct mlx4_cqe *cqe;
366 	u16 index;
367 	u16 new_index, ring_index, stamp_index;
368 	u32 txbbs_skipped = 0;
369 	u32 txbbs_stamp = 0;
370 	u32 cons_index = mcq->cons_index;
371 	int size = cq->size;
372 	u32 size_mask = ring->size_mask;
373 	struct mlx4_cqe *buf = cq->buf;
374 	int factor = priv->cqe_factor;
375 
376 	if (!priv->port_up)
377 		return 0;
378 
379 	index = cons_index & size_mask;
380 	cqe = &buf[(index << factor) + factor];
381 	ring_index = ring->cons & size_mask;
382 	stamp_index = ring_index;
383 
384 	/* Process all completed CQEs */
385 	while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
386 			cons_index & size)) {
387 		/*
388 		 * make sure we read the CQE after we read the
389 		 * ownership bit
390 		 */
391 		rmb();
392 
393 		if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
394 			     MLX4_CQE_OPCODE_ERROR)) {
395 			en_err(priv, "CQE completed in error - vendor syndrom: 0x%x syndrom: 0x%x\n",
396 			       ((struct mlx4_err_cqe *)cqe)->
397 				       vendor_err_syndrome,
398 			       ((struct mlx4_err_cqe *)cqe)->syndrome);
399 		}
400 
401 		/* Skip over last polled CQE */
402 		new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
403 
404 		do {
405 			txbbs_skipped += ring->last_nr_txbb;
406 			ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
407 			/* free next descriptor */
408 			ring->last_nr_txbb = mlx4_en_free_tx_desc(
409 			    priv, ring, ring_index);
410 			mlx4_en_stamp_wqe(priv, ring, stamp_index,
411 					  !!((ring->cons + txbbs_stamp) &
412 						ring->size));
413 			stamp_index = ring_index;
414 			txbbs_stamp = txbbs_skipped;
415 		} while (ring_index != new_index);
416 
417 		++cons_index;
418 		index = cons_index & size_mask;
419 		cqe = &buf[(index << factor) + factor];
420 	}
421 
422 
423 	/*
424 	 * To prevent CQ overflow we first update CQ consumer and only then
425 	 * the ring consumer.
426 	 */
427 	mcq->cons_index = cons_index;
428 	mlx4_cq_set_ci(mcq);
429 	wmb();
430 	ring->cons += txbbs_skipped;
431 
432 	/* Wakeup Tx queue if it was stopped and ring is not full */
433 	if (unlikely(ring->blocked) && !mlx4_en_tx_ring_is_full(ring)) {
434 		ring->blocked = 0;
435 		if (atomic_fetchadd_int(&priv->blocked, -1) == 1)
436 			atomic_clear_int(&dev->if_drv_flags ,IFF_DRV_OACTIVE);
437 		priv->port_stats.wake_queue++;
438 		ring->wake_queue++;
439 	}
440 	return (0);
441 }
442 
443 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
444 {
445 	struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
446 	struct mlx4_en_priv *priv = netdev_priv(cq->dev);
447 	struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
448 
449 	if (priv->port_up == 0 || !spin_trylock(&ring->comp_lock))
450 		return;
451 	mlx4_en_process_tx_cq(cq->dev, cq);
452 	mod_timer(&cq->timer, jiffies + 1);
453 	spin_unlock(&ring->comp_lock);
454 }
455 
456 void mlx4_en_poll_tx_cq(unsigned long data)
457 {
458 	struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
459 	struct mlx4_en_priv *priv = netdev_priv(cq->dev);
460 	struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
461 	u32 inflight;
462 
463 	INC_PERF_COUNTER(priv->pstats.tx_poll);
464 
465 	if (priv->port_up == 0)
466 		return;
467 	if (!spin_trylock(&ring->comp_lock)) {
468 		mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
469 		return;
470 	}
471 	mlx4_en_process_tx_cq(cq->dev, cq);
472 	inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
473 
474 	/* If there are still packets in flight and the timer has not already
475 	 * been scheduled by the Tx routine then schedule it here to guarantee
476 	 * completion processing of these packets */
477 	if (inflight && priv->port_up)
478 		mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
479 
480 	spin_unlock(&ring->comp_lock);
481 }
482 
483 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
484 {
485 	struct mlx4_en_cq *cq = priv->tx_cq[tx_ind];
486 	struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
487 
488 	if (priv->port_up == 0)
489 		return;
490 
491 	/* If we don't have a pending timer, set one up to catch our recent
492 	   post in case the interface becomes idle */
493 	if (!timer_pending(&cq->timer))
494 		mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
495 
496 	/* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
497 	if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
498 		if (spin_trylock(&ring->comp_lock)) {
499 			mlx4_en_process_tx_cq(priv->dev, cq);
500 			spin_unlock(&ring->comp_lock);
501 		}
502 }
503 
504 static u16
505 mlx4_en_get_inline_hdr_size(struct mlx4_en_tx_ring *ring, struct mbuf *mb)
506 {
507 	u16 retval;
508 
509 	/* only copy from first fragment, if possible */
510 	retval = MIN(ring->inline_thold, mb->m_len);
511 
512 	/* check for too little data */
513 	if (unlikely(retval < MIN_PKT_LEN))
514 		retval = MIN(ring->inline_thold, mb->m_pkthdr.len);
515 	return (retval);
516 }
517 
518 static int
519 mlx4_en_get_header_size(struct mbuf *mb)
520 {
521 	struct ether_vlan_header *eh;
522         struct tcphdr *th;
523         struct ip *ip;
524         int ip_hlen, tcp_hlen;
525 	struct ip6_hdr *ip6;
526 	uint16_t eth_type;
527 	int eth_hdr_len;
528 
529 	eh = mtod(mb, struct ether_vlan_header *);
530 	if (mb->m_len < ETHER_HDR_LEN)
531 		return (0);
532 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
533 		eth_type = ntohs(eh->evl_proto);
534 		eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
535 	} else {
536 		eth_type = ntohs(eh->evl_encap_proto);
537 		eth_hdr_len = ETHER_HDR_LEN;
538 	}
539 	if (mb->m_len < eth_hdr_len)
540 		return (0);
541 	switch (eth_type) {
542 	case ETHERTYPE_IP:
543 		ip = (struct ip *)(mb->m_data + eth_hdr_len);
544 		if (mb->m_len < eth_hdr_len + sizeof(*ip))
545 			return (0);
546 		if (ip->ip_p != IPPROTO_TCP)
547 			return (0);
548 		ip_hlen = ip->ip_hl << 2;
549 		eth_hdr_len += ip_hlen;
550 		break;
551 	case ETHERTYPE_IPV6:
552 		ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
553 		if (mb->m_len < eth_hdr_len + sizeof(*ip6))
554 			return (0);
555 		if (ip6->ip6_nxt != IPPROTO_TCP)
556 			return (0);
557 		eth_hdr_len += sizeof(*ip6);
558 		break;
559 	default:
560 		return (0);
561 	}
562 	if (mb->m_len < eth_hdr_len + sizeof(*th))
563 		return (0);
564 	th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
565 	tcp_hlen = th->th_off << 2;
566 	eth_hdr_len += tcp_hlen;
567 	if (mb->m_len < eth_hdr_len)
568 		return (0);
569 	return (eth_hdr_len);
570 }
571 
572 static volatile struct mlx4_wqe_data_seg *
573 mlx4_en_store_inline_data(volatile struct mlx4_wqe_data_seg *dseg,
574     struct mbuf *mb, int len, __be32 owner_bit)
575 {
576 	uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
577 	const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
578 
579 	if (unlikely(len < MIN_PKT_LEN)) {
580 		m_copydata(mb, 0, len, inl + 4);
581 		memset(inl + 4 + len, 0, MIN_PKT_LEN - len);
582 		dseg += DIV_ROUND_UP(4 + MIN_PKT_LEN, DS_SIZE_ALIGNMENT);
583 	} else if (len <= spc) {
584 		m_copydata(mb, 0, len, inl + 4);
585 		dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
586 	} else {
587 		m_copydata(mb, 0, spc, inl + 4);
588 		m_copydata(mb, spc, len - spc, inl + 8 + spc);
589 		dseg += DIV_ROUND_UP(8 + len, DS_SIZE_ALIGNMENT);
590 	}
591 	return (dseg);
592 }
593 
594 static void
595 mlx4_en_store_inline_header(volatile struct mlx4_wqe_data_seg *dseg,
596     int len, __be32 owner_bit)
597 {
598 	uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
599 	const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
600 
601 	if (unlikely(len < MIN_PKT_LEN)) {
602 		*(volatile uint32_t *)inl =
603 		    SET_BYTE_COUNT((1U << 31) | MIN_PKT_LEN);
604 	} else if (len <= spc) {
605 		*(volatile uint32_t *)inl =
606 		    SET_BYTE_COUNT((1U << 31) | len);
607 	} else {
608 		*(volatile uint32_t *)(inl + 4 + spc) =
609 		    SET_BYTE_COUNT((1U << 31) | (len - spc));
610 		wmb();
611 		*(volatile uint32_t *)inl =
612 		    SET_BYTE_COUNT((1U << 31) | spc);
613 	}
614 }
615 
616 static uint32_t hashrandom;
617 static void hashrandom_init(void *arg)
618 {
619 	/*
620 	 * It is assumed that the random subsystem has been
621 	 * initialized when this function is called:
622 	 */
623 	hashrandom = m_ether_tcpip_hash_init();
624 }
625 SYSINIT(hashrandom_init, SI_SUB_RANDOM, SI_ORDER_ANY, &hashrandom_init, NULL);
626 
627 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
628 {
629 	struct mlx4_en_priv *priv = netdev_priv(dev);
630 	u32 rings_p_up = priv->num_tx_rings_p_up;
631 	u32 up = 0;
632 	u32 queue_index;
633 
634 #if (MLX4_EN_NUM_UP > 1)
635 	/* Obtain VLAN information if present */
636 	if (mb->m_flags & M_VLANTAG) {
637 		u32 vlan_tag = mb->m_pkthdr.ether_vtag;
638 	        up = (vlan_tag >> 13) % MLX4_EN_NUM_UP;
639 	}
640 #endif
641 	queue_index = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 | MBUF_HASHFLAG_L4, mb, hashrandom);
642 
643 	return ((queue_index % rings_p_up) + (up * rings_p_up));
644 }
645 
646 static void mlx4_bf_copy(void __iomem *dst, volatile unsigned long *src, unsigned bytecnt)
647 {
648 	__iowrite64_copy(dst, __DEVOLATILE(void *, src), bytecnt / 8);
649 }
650 
651 static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp)
652 {
653 	enum {
654 		DS_FACT = TXBB_SIZE / DS_SIZE_ALIGNMENT,
655 		CTRL_FLAGS = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
656 		    MLX4_WQE_CTRL_SOLICITED),
657 	};
658 	bus_dma_segment_t segs[MLX4_EN_TX_MAX_MBUF_FRAGS];
659 	volatile struct mlx4_wqe_data_seg *dseg;
660 	volatile struct mlx4_wqe_data_seg *dseg_inline;
661 	volatile struct mlx4_en_tx_desc *tx_desc;
662 	struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
663 	struct ifnet *ifp = priv->dev;
664 	struct mlx4_en_tx_info *tx_info;
665 	struct mbuf *mb = *mbp;
666 	struct mbuf *m;
667 	__be32 owner_bit;
668 	int nr_segs;
669 	int pad;
670 	int err;
671 	u32 bf_size;
672 	u32 bf_prod;
673 	u32 opcode;
674 	u16 index;
675 	u16 ds_cnt;
676 	u16 ihs;
677 
678 	if (unlikely(!priv->port_up)) {
679 		err = EINVAL;
680 		goto tx_drop;
681 	}
682 
683 	/* check if TX ring is full */
684 	if (unlikely(mlx4_en_tx_ring_is_full(ring))) {
685 		/* every full native Tx ring stops queue */
686 		if (ring->blocked == 0)
687 			atomic_add_int(&priv->blocked, 1);
688 		/* Set HW-queue-is-full flag */
689 		atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
690 		priv->port_stats.queue_stopped++;
691 		ring->blocked = 1;
692 		ring->queue_stopped++;
693 
694 		/* Use interrupts to find out when queue opened */
695 		mlx4_en_arm_cq(priv, priv->tx_cq[tx_ind]);
696 		return (ENOBUFS);
697 	}
698 
699 	/* sanity check we are not wrapping around */
700 	KASSERT(((~ring->prod) & ring->size_mask) >=
701 	    (MLX4_EN_TX_WQE_MAX_WQEBBS - 1), ("Wrapping around TX ring"));
702 
703 	/* Track current inflight packets for performance analysis */
704 	AVG_PERF_COUNTER(priv->pstats.inflight_avg,
705 			 (u32) (ring->prod - ring->cons - 1));
706 
707 	/* Track current mbuf packet header length */
708 	AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, mb->m_pkthdr.len);
709 
710 	/* Grab an index and try to transmit packet */
711 	owner_bit = (ring->prod & ring->size) ?
712 		cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0;
713 	index = ring->prod & ring->size_mask;
714 	tx_desc = (volatile struct mlx4_en_tx_desc *)
715 	    (ring->buf + index * TXBB_SIZE);
716 	tx_info = &ring->tx_info[index];
717 	dseg = &tx_desc->data;
718 
719 	/* send a copy of the frame to the BPF listener, if any */
720 	if (ifp != NULL && ifp->if_bpf != NULL)
721 		ETHER_BPF_MTAP(ifp, mb);
722 
723 	/* get default flags */
724 	tx_desc->ctrl.srcrb_flags = CTRL_FLAGS;
725 
726 	if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
727 		tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
728 
729 	if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP |
730 	    CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
731 		tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM);
732 
733 	/* do statistics */
734 	if (likely(tx_desc->ctrl.srcrb_flags != CTRL_FLAGS)) {
735 		priv->port_stats.tx_chksum_offload++;
736 		ring->tx_csum++;
737 	}
738 
739 	/* check for VLAN tag */
740 	if (mb->m_flags & M_VLANTAG) {
741 		tx_desc->ctrl.vlan_tag = cpu_to_be16(mb->m_pkthdr.ether_vtag);
742 		tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
743 	} else {
744 		tx_desc->ctrl.vlan_tag = 0;
745 		tx_desc->ctrl.ins_vlan = 0;
746 	}
747 
748 	if (unlikely(mlx4_is_mfunc(priv->mdev->dev) || priv->validate_loopback)) {
749 		/*
750 		 * Copy destination MAC address to WQE. This allows
751 		 * loopback in eSwitch, so that VFs and PF can
752 		 * communicate with each other:
753 		 */
754 		m_copydata(mb, 0, 2, __DEVOLATILE(void *, &tx_desc->ctrl.srcrb_flags16[0]));
755 		m_copydata(mb, 2, 4, __DEVOLATILE(void *, &tx_desc->ctrl.imm));
756 	} else {
757 		/* clear immediate field */
758 		tx_desc->ctrl.imm = 0;
759 	}
760 
761 	/* Handle LSO (TSO) packets */
762 	if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
763 		u32 payload_len;
764 		u32 mss = mb->m_pkthdr.tso_segsz;
765 		u32 num_pkts;
766 
767 		opcode = cpu_to_be32(MLX4_OPCODE_LSO | MLX4_WQE_CTRL_RR) |
768 		    owner_bit;
769 		ihs = mlx4_en_get_header_size(mb);
770 		if (unlikely(ihs > MAX_INLINE)) {
771 			ring->oversized_packets++;
772 			err = EINVAL;
773 			goto tx_drop;
774 		}
775 		tx_desc->lso.mss_hdr_size = cpu_to_be32((mss << 16) | ihs);
776 		payload_len = mb->m_pkthdr.len - ihs;
777 		if (unlikely(payload_len == 0))
778 			num_pkts = 1;
779 		else
780 			num_pkts = DIV_ROUND_UP(payload_len, mss);
781 		ring->bytes += payload_len + (num_pkts * ihs);
782 		ring->packets += num_pkts;
783 		ring->tso_packets++;
784 		/* store pointer to inline header */
785 		dseg_inline = dseg;
786 		/* copy data inline */
787 		dseg = mlx4_en_store_inline_lso_data(dseg,
788 		    mb, ihs, owner_bit);
789 	} else {
790 		opcode = cpu_to_be32(MLX4_OPCODE_SEND) |
791 		    owner_bit;
792 		ihs = mlx4_en_get_inline_hdr_size(ring, mb);
793 		ring->bytes += max_t (unsigned int,
794 		    mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
795 		ring->packets++;
796 		/* store pointer to inline header */
797 		dseg_inline = dseg;
798 		/* copy data inline */
799 		dseg = mlx4_en_store_inline_data(dseg,
800 		    mb, ihs, owner_bit);
801 	}
802 	m_adj(mb, ihs);
803 
804 	err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
805 	    mb, segs, &nr_segs, BUS_DMA_NOWAIT);
806 	if (unlikely(err == EFBIG)) {
807 		/* Too many mbuf fragments */
808 		ring->defrag_attempts++;
809 		m = m_defrag(mb, M_NOWAIT);
810 		if (m == NULL) {
811 			ring->oversized_packets++;
812 			goto tx_drop;
813 		}
814 		mb = m;
815 		/* Try again */
816 		err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
817 		    mb, segs, &nr_segs, BUS_DMA_NOWAIT);
818 	}
819 	/* catch errors */
820 	if (unlikely(err != 0)) {
821 		ring->oversized_packets++;
822 		goto tx_drop;
823 	}
824 	/* If there were no errors and we didn't load anything, don't sync. */
825 	if (nr_segs != 0) {
826 		/* make sure all mbuf data is written to RAM */
827 		bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
828 		    BUS_DMASYNC_PREWRITE);
829 	} else {
830 		/* All data was inlined, free the mbuf. */
831 		bus_dmamap_unload(ring->dma_tag, tx_info->dma_map);
832 		m_freem(mb);
833 		mb = NULL;
834 	}
835 
836 	/* compute number of DS needed */
837 	ds_cnt = (dseg - ((volatile struct mlx4_wqe_data_seg *)tx_desc)) + nr_segs;
838 
839 	/*
840 	 * Check if the next request can wrap around and fill the end
841 	 * of the current request with zero immediate data:
842 	 */
843 	pad = DIV_ROUND_UP(ds_cnt, DS_FACT);
844 	pad = (~(ring->prod + pad)) & ring->size_mask;
845 
846 	if (unlikely(pad < (MLX4_EN_TX_WQE_MAX_WQEBBS - 1))) {
847 		/*
848 		 * Compute the least number of DS blocks we need to
849 		 * pad in order to achieve a TX ring wraparound:
850 		 */
851 		pad = (DS_FACT * (pad + 1));
852 	} else {
853 		/*
854 		 * The hardware will automatically jump to the next
855 		 * TXBB. No need for padding.
856 		 */
857 		pad = 0;
858 	}
859 
860 	/* compute total number of DS blocks */
861 	ds_cnt += pad;
862 	/*
863 	 * When modifying this code, please ensure that the following
864 	 * computation is always less than or equal to 0x3F:
865 	 *
866 	 * ((MLX4_EN_TX_WQE_MAX_WQEBBS - 1) * DS_FACT) +
867 	 * (MLX4_EN_TX_WQE_MAX_WQEBBS * DS_FACT)
868 	 *
869 	 * Else the "ds_cnt" variable can become too big.
870 	 */
871 	tx_desc->ctrl.fence_size = (ds_cnt & 0x3f);
872 
873 	/* store pointer to mbuf */
874 	tx_info->mb = mb;
875 	tx_info->nr_txbb = DIV_ROUND_UP(ds_cnt, DS_FACT);
876 	bf_size = ds_cnt * DS_SIZE_ALIGNMENT;
877 	bf_prod = ring->prod;
878 
879 	/* compute end of "dseg" array */
880 	dseg += nr_segs + pad;
881 
882 	/* pad using zero immediate dseg */
883 	while (pad--) {
884 		dseg--;
885 		dseg->addr = 0;
886 		dseg->lkey = 0;
887 		wmb();
888 		dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0);
889 	}
890 
891 	/* fill segment list */
892 	while (nr_segs--) {
893 		if (unlikely(segs[nr_segs].ds_len == 0)) {
894 			dseg--;
895 			dseg->addr = 0;
896 			dseg->lkey = 0;
897 			wmb();
898 			dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0);
899 		} else {
900 			dseg--;
901 			dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr);
902 			dseg->lkey = cpu_to_be32(priv->mdev->mr.key);
903 			wmb();
904 			dseg->byte_count = SET_BYTE_COUNT((uint32_t)segs[nr_segs].ds_len);
905 		}
906 	}
907 
908 	wmb();
909 
910 	/* write owner bits in reverse order */
911 	if ((opcode & cpu_to_be32(0x1F)) == cpu_to_be32(MLX4_OPCODE_LSO))
912 		mlx4_en_store_inline_lso_header(dseg_inline, ihs, owner_bit);
913 	else
914 		mlx4_en_store_inline_header(dseg_inline, ihs, owner_bit);
915 
916 	/* update producer counter */
917 	ring->prod += tx_info->nr_txbb;
918 
919 	if (ring->bf_enabled && bf_size <= MAX_BF &&
920 	    (tx_desc->ctrl.ins_vlan != MLX4_WQE_CTRL_INS_CVLAN)) {
921 
922 		/* store doorbell number */
923 		*(volatile __be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
924 
925 		/* or in producer number for this WQE */
926 		opcode |= cpu_to_be32((bf_prod & 0xffff) << 8);
927 
928 		/*
929 		 * Ensure the new descriptor hits memory before
930 		 * setting ownership of this descriptor to HW:
931 		 */
932 		wmb();
933 		tx_desc->ctrl.owner_opcode = opcode;
934 		wmb();
935 		mlx4_bf_copy(((u8 *)ring->bf.reg) + ring->bf.offset,
936 		     (volatile unsigned long *) &tx_desc->ctrl, bf_size);
937 		wmb();
938 		ring->bf.offset ^= ring->bf.buf_size;
939 	} else {
940 		/*
941 		 * Ensure the new descriptor hits memory before
942 		 * setting ownership of this descriptor to HW:
943 		 */
944 		wmb();
945 		tx_desc->ctrl.owner_opcode = opcode;
946 		wmb();
947 		writel(cpu_to_be32(ring->doorbell_qpn),
948 		    ((u8 *)ring->bf.uar->map) + MLX4_SEND_DOORBELL);
949 	}
950 
951 	return (0);
952 tx_drop:
953 	*mbp = NULL;
954 	m_freem(mb);
955 	return (err);
956 }
957 
958 static int
959 mlx4_en_transmit_locked(struct ifnet *dev, int tx_ind, struct mbuf *m)
960 {
961 	struct mlx4_en_priv *priv = netdev_priv(dev);
962 	struct mlx4_en_tx_ring *ring;
963 	struct mbuf *next;
964 	int enqueued, err = 0;
965 
966 	ring = priv->tx_ring[tx_ind];
967 	if ((dev->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
968 	    IFF_DRV_RUNNING || priv->port_up == 0) {
969 		if (m != NULL)
970 			err = drbr_enqueue(dev, ring->br, m);
971 		return (err);
972 	}
973 
974 	enqueued = 0;
975 	if (m != NULL)
976 		/*
977 		 * If we can't insert mbuf into drbr, try to xmit anyway.
978 		 * We keep the error we got so we could return that after xmit.
979 		 */
980 		err = drbr_enqueue(dev, ring->br, m);
981 
982 	/* Process the queue */
983 	while ((next = drbr_peek(dev, ring->br)) != NULL) {
984 		if (mlx4_en_xmit(priv, tx_ind, &next) != 0) {
985 			if (next == NULL) {
986 				drbr_advance(dev, ring->br);
987 			} else {
988 				drbr_putback(dev, ring->br, next);
989 			}
990 			break;
991 		}
992 		drbr_advance(dev, ring->br);
993 		enqueued++;
994 		if ((dev->if_drv_flags & IFF_DRV_RUNNING) == 0)
995 			break;
996 	}
997 
998 	if (enqueued > 0)
999 		ring->watchdog_time = ticks;
1000 
1001 	return (err);
1002 }
1003 
1004 void
1005 mlx4_en_tx_que(void *context, int pending)
1006 {
1007 	struct mlx4_en_tx_ring *ring;
1008 	struct mlx4_en_priv *priv;
1009 	struct net_device *dev;
1010 	struct mlx4_en_cq *cq;
1011 	int tx_ind;
1012 	cq = context;
1013 	dev = cq->dev;
1014 	priv = dev->if_softc;
1015 	tx_ind = cq->ring;
1016 	ring = priv->tx_ring[tx_ind];
1017 
1018 	if (priv->port_up != 0 &&
1019 	    (dev->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1020 		mlx4_en_xmit_poll(priv, tx_ind);
1021 		spin_lock(&ring->tx_lock);
1022                 if (!drbr_empty(dev, ring->br))
1023 			mlx4_en_transmit_locked(dev, tx_ind, NULL);
1024 		spin_unlock(&ring->tx_lock);
1025 	}
1026 }
1027 
1028 int
1029 mlx4_en_transmit(struct ifnet *dev, struct mbuf *m)
1030 {
1031 	struct mlx4_en_priv *priv = netdev_priv(dev);
1032 	struct mlx4_en_tx_ring *ring;
1033 	struct mlx4_en_cq *cq;
1034 	int i, err = 0;
1035 
1036 	if (priv->port_up == 0) {
1037 		m_freem(m);
1038 		return (ENETDOWN);
1039 	}
1040 
1041 	/* Compute which queue to use */
1042 	if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
1043 		i = (m->m_pkthdr.flowid % 128) % priv->tx_ring_num;
1044 	}
1045 	else {
1046 		i = mlx4_en_select_queue(dev, m);
1047 	}
1048 
1049 	ring = priv->tx_ring[i];
1050 	if (spin_trylock(&ring->tx_lock)) {
1051 		err = mlx4_en_transmit_locked(dev, i, m);
1052 		spin_unlock(&ring->tx_lock);
1053 		/* Poll CQ here */
1054 		mlx4_en_xmit_poll(priv, i);
1055 	} else {
1056 		err = drbr_enqueue(dev, ring->br, m);
1057 		cq = priv->tx_cq[i];
1058 		taskqueue_enqueue(cq->tq, &cq->cq_task);
1059 	}
1060 
1061 #if __FreeBSD_version >= 1100000
1062 	if (unlikely(err != 0))
1063 		if_inc_counter(dev, IFCOUNTER_IQDROPS, 1);
1064 #endif
1065 	return (err);
1066 }
1067 
1068 /*
1069  * Flush ring buffers.
1070  */
1071 void
1072 mlx4_en_qflush(struct ifnet *dev)
1073 {
1074 	struct mlx4_en_priv *priv = netdev_priv(dev);
1075 	struct mlx4_en_tx_ring *ring;
1076 	struct mbuf *m;
1077 
1078 	if (priv->port_up == 0)
1079 		return;
1080 
1081 	for (int i = 0; i < priv->tx_ring_num; i++) {
1082 		ring = priv->tx_ring[i];
1083 		spin_lock(&ring->tx_lock);
1084 		while ((m = buf_ring_dequeue_sc(ring->br)) != NULL)
1085 			m_freem(m);
1086 		spin_unlock(&ring->tx_lock);
1087 	}
1088 	if_qflush(dev);
1089 }
1090