xref: /freebsd/sys/dev/mlx4/mlx4_en/en.h (revision f1951fd745b894fe6586c298874af98544a5e272)
1 /*
2  * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36 
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/kobject.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/if_ether.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
47 #endif
48 
49 #include <dev/mlx4/device.h>
50 #include <dev/mlx4/qp.h>
51 #include <dev/mlx4/cq.h>
52 #include <dev/mlx4/srq.h>
53 #include <dev/mlx4/doorbell.h>
54 #include <dev/mlx4/cmd.h>
55 
56 #include <netinet/tcp_lro.h>
57 
58 #include "en_port.h"
59 #include <dev/mlx4/stats.h>
60 
61 #define DRV_NAME	"mlx4_en"
62 
63 #define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
64 
65 /*
66  * Device constants
67  */
68 
69 
70 #define MLX4_EN_PAGE_SHIFT	12
71 #define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
72 #define	MLX4_NET_IP_ALIGN	2	/* bytes */
73 #define DEF_RX_RINGS		16
74 #define MAX_RX_RINGS		128
75 #define MIN_RX_RINGS		4
76 #define TXBB_SIZE		64
77 #define HEADROOM		(2048 / TXBB_SIZE + 1)
78 #define INIT_OWNER_BIT		0xffffffff
79 #define STAMP_STRIDE		64
80 #define STAMP_DWORDS		(STAMP_STRIDE / 4)
81 #define STAMP_SHIFT		31
82 #define STAMP_VAL		0x7fffffff
83 #define STATS_DELAY		(HZ / 4)
84 #define SERVICE_TASK_DELAY	(HZ / 4)
85 #define MAX_NUM_OF_FS_RULES	256
86 
87 #define MLX4_EN_FILTER_HASH_SHIFT 4
88 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89 
90 #ifdef CONFIG_NET_RX_BUSY_POLL
91 #define LL_EXTENDED_STATS
92 #endif
93 
94 /* vlan valid range */
95 #define VLAN_MIN_VALUE		1
96 #define VLAN_MAX_VALUE		4094
97 
98 /*
99  * OS related constants and tunables
100  */
101 
102 #define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)
103 
104 #define MLX4_EN_ALLOC_SIZE     PAGE_ALIGN(PAGE_SIZE)
105 #define MLX4_EN_ALLOC_ORDER    get_order(MLX4_EN_ALLOC_SIZE)
106 
107 enum mlx4_en_alloc_type {
108 	MLX4_EN_ALLOC_NEW = 0,
109 	MLX4_EN_ALLOC_REPLACEMENT = 1,
110 };
111 
112 /* Maximum ring sizes */
113 #define MLX4_EN_DEF_TX_QUEUE_SIZE       4096
114 
115 /* Minimum packet number till arming the CQ */
116 #define MLX4_EN_MIN_RX_ARM	2048
117 #define MLX4_EN_MIN_TX_ARM	2048
118 
119 /* Maximum ring sizes */
120 #define MLX4_EN_MAX_TX_SIZE	8192
121 #define MLX4_EN_MAX_RX_SIZE	8192
122 
123 /* Minimum ring sizes */
124 #define MLX4_EN_MIN_RX_SIZE	(4096 / TXBB_SIZE)
125 #define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)
126 
127 #define MLX4_EN_SMALL_PKT_SIZE		64
128 
129 #define MLX4_EN_MAX_TX_RING_P_UP	32
130 #define MLX4_EN_NUM_UP			1
131 
132 #define MAX_TX_RINGS			(MLX4_EN_MAX_TX_RING_P_UP * \
133 					MLX4_EN_NUM_UP)
134 
135 #define MLX4_EN_NO_VLAN			0xffff
136 
137 #define MLX4_EN_DEF_TX_RING_SIZE	1024
138 #define MLX4_EN_DEF_RX_RING_SIZE  	1024
139 
140 /* Target number of bytes to coalesce with interrupt moderation */
141 #define MLX4_EN_RX_COAL_TARGET	44
142 #define MLX4_EN_RX_COAL_TIME	0x10
143 
144 #define MLX4_EN_TX_COAL_PKTS	64
145 #define MLX4_EN_TX_COAL_TIME	64
146 
147 #define MLX4_EN_RX_RATE_LOW		400000
148 #define MLX4_EN_RX_COAL_TIME_LOW	0
149 #define MLX4_EN_RX_RATE_HIGH		450000
150 #define MLX4_EN_RX_COAL_TIME_HIGH	128
151 #define MLX4_EN_RX_SIZE_THRESH		1024
152 #define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
153 #define MLX4_EN_SAMPLE_INTERVAL		0
154 #define MLX4_EN_AVG_PKT_SMALL		256
155 
156 #define MLX4_EN_AUTO_CONF	0xffff
157 
158 #define MLX4_EN_DEF_RX_PAUSE	1
159 #define MLX4_EN_DEF_TX_PAUSE	1
160 
161 /* Interval between successive polls in the Tx routine when polling is used
162    instead of interrupts (in per-core Tx rings) - should be power of 2 */
163 #define MLX4_EN_TX_POLL_MODER	16
164 #define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)
165 
166 #define MLX4_EN_64_ALIGN	(64 - NET_SKB_PAD)
167 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
168 #define HEADER_COPY_SIZE       (128)
169 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN)
170 
171 #define MLX4_EN_MIN_MTU		46
172 #define ETH_BCAST		0xffffffffffffULL
173 
174 #define MLX4_EN_LOOPBACK_RETRIES	5
175 #define MLX4_EN_LOOPBACK_TIMEOUT	100
176 
177 #ifdef MLX4_EN_PERF_STAT
178 /* Number of samples to 'average' */
179 #define AVG_SIZE			128
180 #define AVG_FACTOR			1024
181 
182 #define INC_PERF_COUNTER(cnt)		(++(cnt))
183 #define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
184 #define AVG_PERF_COUNTER(cnt, sample) \
185 	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
186 #define GET_PERF_COUNTER(cnt)		(cnt)
187 #define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)
188 
189 #else
190 
191 #define INC_PERF_COUNTER(cnt)		do {} while (0)
192 #define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
193 #define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
194 #define GET_PERF_COUNTER(cnt)		(0)
195 #define GET_AVG_PERF_COUNTER(cnt)	(0)
196 #endif /* MLX4_EN_PERF_STAT */
197 
198 /* Constants for TX flow */
199 enum {
200 	MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
201 	MAX_BF = 256,
202 	MIN_PKT_LEN = 17,
203 };
204 
205 /*
206  * Configurables
207  */
208 
209 enum cq_type {
210 	RX = 0,
211 	TX = 1,
212 };
213 
214 
215 /*
216  * Useful macros
217  */
218 #define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
219 #define XNOR(x, y)		(!(x) == !(y))
220 #define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)
221 
222 struct mlx4_en_tx_info {
223 	bus_dmamap_t dma_map;
224         struct mbuf *mb;
225         u32 nr_txbb;
226 	u32 nr_bytes;
227 };
228 
229 
230 #define MLX4_EN_BIT_DESC_OWN	0x80000000
231 #define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
232 #define MLX4_EN_MEMTYPE_PAD	0x100
233 #define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)
234 
235 
236 struct mlx4_en_tx_desc {
237 	struct mlx4_wqe_ctrl_seg ctrl;
238 	union {
239 		struct mlx4_wqe_data_seg data; /* at least one data segment */
240 		struct mlx4_wqe_lso_seg lso;
241 		struct mlx4_wqe_inline_seg inl;
242 	};
243 };
244 
245 #define MLX4_EN_USE_SRQ		0x01000000
246 
247 #define MLX4_EN_RX_BUDGET 64
248 
249 #define	MLX4_EN_TX_MAX_DESC_SIZE 512	/* bytes */
250 #define	MLX4_EN_TX_MAX_MBUF_SIZE 65536	/* bytes */
251 #define	MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536	/* bytes */
252 #define	MLX4_EN_TX_MAX_MBUF_FRAGS \
253     ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
254 #define	MLX4_EN_TX_WQE_MAX_WQEBBS			\
255     (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */
256 
257 #define MLX4_EN_CX3_LOW_ID	0x1000
258 #define MLX4_EN_CX3_HIGH_ID	0x1005
259 
260 struct mlx4_en_tx_ring {
261         spinlock_t tx_lock;
262 	bus_dma_tag_t dma_tag;
263 	struct mlx4_hwq_resources wqres;
264 	u32 size ; /* number of TXBBs */
265 	u32 size_mask;
266 	u16 stride;
267 	u16 cqn;	/* index of port CQ associated with this ring */
268 	u32 prod;
269 	u32 cons;
270 	u32 buf_size;
271 	u32 doorbell_qpn;
272 	u8 *buf;
273 	u16 poll_cnt;
274 	int blocked;
275 	struct mlx4_en_tx_info *tx_info;
276 	u8 queue_index;
277 	struct buf_ring *br;
278 	u32 last_nr_txbb;
279 	struct mlx4_qp qp;
280 	struct mlx4_qp_context context;
281 	int qpn;
282 	enum mlx4_qp_state qp_state;
283 	struct mlx4_srq dummy;
284 	u64 bytes;
285 	u64 packets;
286 	u64 tx_csum;
287 	u64 queue_stopped;
288 	u64 oversized_packets;
289 	u64 wake_queue;
290 	u64 tso_packets;
291 	u64 defrag_attempts;
292 	struct mlx4_bf bf;
293 	bool bf_enabled;
294 	int hwtstamp_tx_type;
295 	spinlock_t comp_lock;
296 	int inline_thold;
297 	u64 watchdog_time;
298 };
299 
300 struct mlx4_en_rx_desc {
301 	/* actual number of entries depends on rx ring stride */
302 	struct mlx4_wqe_data_seg data[0];
303 };
304 
305 struct mlx4_en_rx_mbuf {
306 	bus_dmamap_t dma_map;
307 	struct mbuf *mbuf;
308 };
309 
310 struct mlx4_en_rx_spare {
311 	bus_dmamap_t dma_map;
312 	struct mbuf *mbuf;
313 	u64 paddr_be;
314 };
315 
316 struct mlx4_en_rx_ring {
317 	struct mlx4_hwq_resources wqres;
318 	bus_dma_tag_t dma_tag;
319 	struct mlx4_en_rx_spare spare;
320 	u32 size ;	/* number of Rx descs*/
321 	u32 actual_size;
322 	u32 size_mask;
323 	u16 stride;
324 	u16 log_stride;
325 	u16 cqn;	/* index of port CQ associated with this ring */
326 	u32 prod;
327 	u32 cons;
328 	u32 buf_size;
329 	u8  fcs_del;
330 	u32 rx_mb_size;
331 	int qpn;
332 	u8 *buf;
333 	struct mlx4_en_rx_mbuf *mbuf;
334 	u64 errors;
335 	u64 bytes;
336 	u64 packets;
337 #ifdef LL_EXTENDED_STATS
338 	u64 yields;
339 	u64 misses;
340 	u64 cleaned;
341 #endif
342 	u64 csum_ok;
343 	u64 csum_none;
344 	int hwtstamp_rx_filter;
345 	int numa_node;
346 	struct lro_ctrl lro;
347 };
348 
349 static inline int mlx4_en_can_lro(__be16 status)
350 {
351 	const __be16 status_all = cpu_to_be16(
352 			MLX4_CQE_STATUS_IPV4    |
353 			MLX4_CQE_STATUS_IPV4F   |
354 			MLX4_CQE_STATUS_IPV6    |
355 			MLX4_CQE_STATUS_IPV4OPT |
356 			MLX4_CQE_STATUS_TCP     |
357 			MLX4_CQE_STATUS_UDP     |
358 			MLX4_CQE_STATUS_IPOK);
359 	const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
360 			MLX4_CQE_STATUS_IPV4    |
361 			MLX4_CQE_STATUS_IPOK    |
362 			MLX4_CQE_STATUS_TCP);
363 	const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
364 			MLX4_CQE_STATUS_IPV6    |
365 			MLX4_CQE_STATUS_IPOK    |
366 			MLX4_CQE_STATUS_TCP);
367 
368 	status &= status_all;
369 	return (status == status_ipv4_ipok_tcp ||
370 			status == status_ipv6_ipok_tcp);
371 }
372 
373 struct mlx4_en_cq {
374 	struct mlx4_cq          mcq;
375 	struct mlx4_hwq_resources wqres;
376 	int                     ring;
377 	spinlock_t              lock;
378 	struct net_device      *dev;
379         /* Per-core Tx cq processing support */
380         struct timer_list timer;
381 	int size;
382 	int buf_size;
383 	unsigned vector;
384 	enum cq_type is_tx;
385 	u16 moder_time;
386 	u16 moder_cnt;
387 	struct mlx4_cqe *buf;
388 	struct task cq_task;
389 	struct taskqueue *tq;
390 #define MLX4_EN_OPCODE_ERROR	0x1e
391 	u32 tot_rx;
392 	u32 tot_tx;
393 	u32 curr_poll_rx_cpu_id;
394 
395 #ifdef CONFIG_NET_RX_BUSY_POLL
396 	unsigned int state;
397 #define MLX4_EN_CQ_STATE_IDLE        0
398 #define MLX4_EN_CQ_STATE_NAPI     1    /* NAPI owns this CQ */
399 #define MLX4_EN_CQ_STATE_POLL     2    /* poll owns this CQ */
400 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
401 #define MLX4_EN_CQ_STATE_NAPI_YIELD  4    /* NAPI yielded this CQ */
402 #define MLX4_EN_CQ_STATE_POLL_YIELD  8    /* poll yielded this CQ */
403 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
404 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
405 	spinlock_t poll_lock; /* protects from LLS/napi conflicts */
406 #endif  /* CONFIG_NET_RX_BUSY_POLL */
407 };
408 
409 struct mlx4_en_port_profile {
410 	u32 flags;
411 	u32 tx_ring_num;
412 	u32 rx_ring_num;
413 	u32 tx_ring_size;
414 	u32 rx_ring_size;
415 	u8 rx_pause;
416 	u8 rx_ppp;
417 	u8 tx_pause;
418 	u8 tx_ppp;
419 	int rss_rings;
420 	int inline_thold;
421 };
422 
423 struct mlx4_en_profile {
424 	int rss_xor;
425 	int udp_rss;
426 	u8 rss_mask;
427 	u32 active_ports;
428 	u32 small_pkt_int;
429 	u8 no_reset;
430 	u8 num_tx_rings_p_up;
431 	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
432 };
433 
434 struct mlx4_en_dev {
435 	struct mlx4_dev		*dev;
436 	struct pci_dev		*pdev;
437 	struct mutex		state_lock;
438 	struct net_device	*pndev[MLX4_MAX_PORTS + 1];
439 	u32			port_cnt;
440 	bool			device_up;
441 	struct mlx4_en_profile	profile;
442 	u32			LSO_support;
443 	struct workqueue_struct *workqueue;
444 	struct device		*dma_device;
445 	void __iomem		*uar_map;
446 	struct mlx4_uar		priv_uar;
447 	struct mlx4_mr		mr;
448 	u32			priv_pdn;
449 	spinlock_t		uar_lock;
450 	u8			mac_removed[MLX4_MAX_PORTS + 1];
451 	unsigned long		last_overflow_check;
452 	unsigned long		overflow_period;
453 };
454 
455 
456 struct mlx4_en_rss_map {
457 	int base_qpn;
458 	struct mlx4_qp qps[MAX_RX_RINGS];
459 	enum mlx4_qp_state state[MAX_RX_RINGS];
460 	struct mlx4_qp indir_qp;
461 	enum mlx4_qp_state indir_state;
462 };
463 
464 enum mlx4_en_port_flag {
465 	MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
466 	MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
467 };
468 
469 struct mlx4_en_port_state {
470 	int link_state;
471 	int link_speed;
472 	int transceiver;
473 	u32 flags;
474 };
475 
476 enum mlx4_en_addr_list_act {
477 	MLX4_ADDR_LIST_NONE,
478 	MLX4_ADDR_LIST_REM,
479 	MLX4_ADDR_LIST_ADD,
480 };
481 
482 struct mlx4_en_addr_list {
483 	struct list_head	list;
484 	enum mlx4_en_addr_list_act	action;
485 	u8			addr[ETH_ALEN];
486 	u64			reg_id;
487 	u64			tunnel_reg_id;
488 };
489 
490 #ifdef CONFIG_MLX4_EN_DCB
491 /* Minimal TC BW - setting to 0 will block traffic */
492 #define MLX4_EN_BW_MIN 1
493 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
494 
495 #define MLX4_EN_TC_VENDOR 0
496 #define MLX4_EN_TC_ETS 7
497 
498 #endif
499 
500 
501 enum {
502 	MLX4_EN_FLAG_PROMISC		= (1 << 0),
503 	MLX4_EN_FLAG_MC_PROMISC		= (1 << 1),
504 	/* whether we need to enable hardware loopback by putting dmac
505 	 * in Tx WQE
506 	 */
507 	MLX4_EN_FLAG_ENABLE_HW_LOOPBACK	= (1 << 2),
508 	/* whether we need to drop packets that hardware loopback-ed */
509 	MLX4_EN_FLAG_RX_FILTER_NEEDED	= (1 << 3),
510 	MLX4_EN_FLAG_FORCE_PROMISC	= (1 << 4),
511 #ifdef CONFIG_MLX4_EN_DCB
512 	MLX4_EN_FLAG_DCB_ENABLED	= (1 << 5)
513 #endif
514 };
515 
516 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
517 #define MLX4_EN_MAC_HASH_IDX 5
518 
519 struct en_port {
520 	struct kobject		kobj;
521 	struct mlx4_dev		*dev;
522 	u8			port_num;
523 	u8			vport_num;
524 };
525 
526 struct mlx4_en_priv {
527 	struct mlx4_en_dev *mdev;
528 	struct mlx4_en_port_profile *prof;
529 	struct net_device *dev;
530 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
531 	struct mlx4_en_port_state port_state;
532 	spinlock_t stats_lock;
533 	/* To allow rules removal while port is going down */
534 	struct list_head ethtool_list;
535 
536 	unsigned long last_moder_packets[MAX_RX_RINGS];
537 	unsigned long last_moder_tx_packets;
538 	unsigned long last_moder_bytes[MAX_RX_RINGS];
539 	unsigned long last_moder_jiffies;
540 	int last_moder_time[MAX_RX_RINGS];
541 	u16 rx_usecs;
542 	u16 rx_frames;
543 	u16 tx_usecs;
544 	u16 tx_frames;
545 	u32 pkt_rate_low;
546 	u32 rx_usecs_low;
547 	u32 pkt_rate_high;
548 	u32 rx_usecs_high;
549 	u32 sample_interval;
550 	u32 adaptive_rx_coal;
551 	u32 msg_enable;
552 	u32 loopback_ok;
553 	u32 validate_loopback;
554 
555 	struct mlx4_hwq_resources res;
556 	int link_state;
557 	int last_link_state;
558 	bool port_up;
559 	int port;
560 	int registered;
561 	int gone;
562 	int allocated;
563 	int stride;
564 	unsigned char current_mac[ETH_ALEN + 2];
565         u64 mac;
566 	int mac_index;
567 	unsigned max_mtu;
568 	int base_qpn;
569 	int cqe_factor;
570 
571 	struct mlx4_en_rss_map rss_map;
572 	u32 flags;
573 	u8 num_tx_rings_p_up;
574 	u32 tx_ring_num;
575 	u32 rx_ring_num;
576 	u32 rx_mb_size;
577 
578 	struct mlx4_en_tx_ring **tx_ring;
579 	struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
580 	struct mlx4_en_cq **tx_cq;
581 	struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
582 	struct mlx4_qp drop_qp;
583 	struct work_struct rx_mode_task;
584 	struct work_struct watchdog_task;
585 	struct work_struct linkstate_task;
586 	struct delayed_work stats_task;
587 	struct delayed_work service_task;
588 	struct mlx4_en_perf_stats pstats;
589 	struct mlx4_en_pkt_stats pkstats;
590 	struct mlx4_en_pkt_stats pkstats_last;
591 	struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
592 	struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
593 	struct mlx4_en_flow_stats_rx rx_flowstats;
594 	struct mlx4_en_flow_stats_tx tx_flowstats;
595 	struct mlx4_en_port_stats port_stats;
596 	struct mlx4_en_vport_stats vport_stats;
597 	struct mlx4_en_vf_stats vf_stats;
598 	struct list_head mc_list;
599 	struct list_head uc_list;
600 	struct list_head curr_mc_list;
601 	struct list_head curr_uc_list;
602 	u64 broadcast_id;
603 	struct mlx4_en_stat_out_mbox hw_stats;
604 	int vids[128];
605 	bool wol;
606 	struct device *ddev;
607 	struct dentry *dev_root;
608 	u32 counter_index;
609 	eventhandler_tag vlan_attach;
610 	eventhandler_tag vlan_detach;
611 	struct callout watchdog_timer;
612         struct ifmedia media;
613 	volatile int blocked;
614 	struct sysctl_oid *conf_sysctl;
615 	struct sysctl_oid *stat_sysctl;
616 	struct sysctl_ctx_list conf_ctx;
617 	struct sysctl_ctx_list stat_ctx;
618 
619 #ifdef CONFIG_MLX4_EN_DCB
620 	struct ieee_ets ets;
621 	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
622 	u8 dcbx_cap;
623 #endif
624 #ifdef CONFIG_RFS_ACCEL
625 	spinlock_t filters_lock;
626 	int last_filter_id;
627 	struct list_head filters;
628 	struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
629 #endif
630 	u64 tunnel_reg_id;
631 	struct en_port *vf_ports[MLX4_MAX_NUM_VF];
632 	unsigned long last_ifq_jiffies;
633 	u64 if_counters_rx_errors;
634 	u64 if_counters_rx_no_buffer;
635 };
636 
637 enum mlx4_en_wol {
638 	MLX4_EN_WOL_MAGIC = (1ULL << 61),
639 	MLX4_EN_WOL_ENABLED = (1ULL << 62),
640 };
641 
642 struct mlx4_mac_entry {
643 	struct hlist_node hlist;
644 	unsigned char mac[ETH_ALEN + 2];
645 	u64 reg_id;
646 };
647 
648 static inline struct mlx4_cqe *mlx4_en_get_cqe(u8 *buf, int idx, int cqe_sz)
649 {
650 	return (struct mlx4_cqe *)(buf + idx * cqe_sz);
651 }
652 
653 #ifdef CONFIG_NET_RX_BUSY_POLL
654 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
655 {
656 	spin_lock_init(&cq->poll_lock);
657 	cq->state = MLX4_EN_CQ_STATE_IDLE;
658 }
659 
660 /* called from the device poll rutine to get ownership of a cq */
661 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
662 {
663 	int rc = true;
664 	spin_lock(&cq->poll_lock);
665 	if (cq->state & MLX4_CQ_LOCKED) {
666 		WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
667 		cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
668 		rc = false;
669 	} else
670 		/* we don't care if someone yielded */
671 		cq->state = MLX4_EN_CQ_STATE_NAPI;
672 	spin_unlock(&cq->poll_lock);
673 	return rc;
674 }
675 
676 /* returns true is someone tried to get the cq while napi had it */
677 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
678 {
679 	int rc = false;
680 	spin_lock(&cq->poll_lock);
681 	WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
682 			       MLX4_EN_CQ_STATE_NAPI_YIELD));
683 
684 	if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
685 		rc = true;
686 	cq->state = MLX4_EN_CQ_STATE_IDLE;
687 	spin_unlock(&cq->poll_lock);
688 	return rc;
689 }
690 
691 /* called from mlx4_en_low_latency_poll() */
692 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
693 {
694 	int rc = true;
695 	spin_lock_bh(&cq->poll_lock);
696 	if ((cq->state & MLX4_CQ_LOCKED)) {
697 		struct net_device *dev = cq->dev;
698 		struct mlx4_en_priv *priv = netdev_priv(dev);
699 		struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
700 
701 		cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
702 		rc = false;
703 #ifdef LL_EXTENDED_STATS
704 		rx_ring->yields++;
705 #endif
706 	} else
707 		/* preserve yield marks */
708 		cq->state |= MLX4_EN_CQ_STATE_POLL;
709 	spin_unlock_bh(&cq->poll_lock);
710 	return rc;
711 }
712 
713 /* returns true if someone tried to get the cq while it was locked */
714 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
715 {
716 	int rc = false;
717 	spin_lock_bh(&cq->poll_lock);
718 	WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
719 
720 	if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
721 		rc = true;
722 	cq->state = MLX4_EN_CQ_STATE_IDLE;
723 	spin_unlock_bh(&cq->poll_lock);
724 	return rc;
725 }
726 
727 /* true if a socket is polling, even if it did not get the lock */
728 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
729 {
730 	WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
731 	return cq->state & CQ_USER_PEND;
732 }
733 #else
734 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
735 {
736 }
737 
738 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
739 {
740 	return true;
741 }
742 
743 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
744 {
745 	return false;
746 }
747 
748 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
749 {
750 	return false;
751 }
752 
753 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
754 {
755 	return false;
756 }
757 
758 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
759 {
760 	return false;
761 }
762 #endif /* CONFIG_NET_RX_BUSY_POLL */
763 
764 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
765 
766 void mlx4_en_destroy_netdev(struct net_device *dev);
767 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
768 			struct mlx4_en_port_profile *prof);
769 
770 int mlx4_en_start_port(struct net_device *dev);
771 void mlx4_en_stop_port(struct net_device *dev);
772 
773 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
774 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
775 
776 int mlx4_en_pre_config(struct mlx4_en_priv *priv);
777 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
778 		      int entries, int ring, enum cq_type mode, int node);
779 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
780 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
781 			int cq_idx);
782 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
783 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
784 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
785 
786 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
787 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb);
788 
789 int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m);
790 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
791 			   struct mlx4_en_tx_ring **pring,
792 			   u32 size, u16 stride, int node, int queue_idx);
793 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
794 			     struct mlx4_en_tx_ring **pring);
795 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
796 			     struct mlx4_en_tx_ring *ring,
797 			     int cq, int user_prio);
798 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
799 				struct mlx4_en_tx_ring *ring);
800 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
801 void mlx4_en_qflush(struct ifnet *dev);
802 
803 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
804 			   struct mlx4_en_rx_ring **pring,
805 			   u32 size, int node);
806 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
807 			     struct mlx4_en_rx_ring **pring,
808 			     u32 size, u16 stride);
809 void mlx4_en_tx_que(void *context, int pending);
810 void mlx4_en_rx_que(void *context, int pending);
811 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
812 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
813 				struct mlx4_en_rx_ring *ring);
814 int mlx4_en_process_rx_cq(struct net_device *dev,
815 			  struct mlx4_en_cq *cq,
816 			  int budget);
817 void mlx4_en_poll_tx_cq(unsigned long data);
818 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
819 		int is_tx, int rss, int qpn, int cqn, int user_prio,
820 		struct mlx4_qp_context *context);
821 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
822 int mlx4_en_map_buffer(struct mlx4_buf *buf);
823 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
824 void mlx4_en_calc_rx_buf(struct net_device *dev);
825 
826 const u32 *mlx4_en_get_rss_key(struct mlx4_en_priv *priv, u16 *keylen);
827 u8 mlx4_en_get_rss_mask(struct mlx4_en_priv *priv);
828 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
829 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
830 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
831 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
832 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
833 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
834 
835 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
836 
837 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
838 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
839 int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port);
840 void mlx4_en_create_debug_files(struct mlx4_en_priv *priv);
841 void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv);
842 int mlx4_en_register_debugfs(void);
843 void mlx4_en_unregister_debugfs(void);
844 
845 #ifdef CONFIG_MLX4_EN_DCB
846 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
847 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
848 #endif
849 
850 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
851 
852 #ifdef CONFIG_RFS_ACCEL
853 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
854 			     struct mlx4_en_rx_ring *rx_ring);
855 #endif
856 
857 #define MLX4_EN_NUM_SELF_TEST	5
858 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
859 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
860 
861 /*
862  * Functions for time stamping
863  */
864 #define SKBTX_HW_TSTAMP (1 << 0)
865 #define SKBTX_IN_PROGRESS (1 << 2)
866 
867 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
868 
869 /* Functions for caching and restoring statistics */
870 int mlx4_en_get_sset_count(struct net_device *dev, int sset);
871 void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv,
872 				    u64 *data);
873 
874 /*
875  * Globals
876  */
877 extern const struct ethtool_ops mlx4_en_ethtool_ops;
878 
879 /*
880  * Defines for link speed - needed by selftest
881  */
882 #define MLX4_EN_LINK_SPEED_1G	1000
883 #define MLX4_EN_LINK_SPEED_10G	10000
884 #define MLX4_EN_LINK_SPEED_40G	40000
885 
886 enum {
887         NETIF_MSG_DRV           = 0x0001,
888         NETIF_MSG_PROBE         = 0x0002,
889         NETIF_MSG_LINK          = 0x0004,
890         NETIF_MSG_TIMER         = 0x0008,
891         NETIF_MSG_IFDOWN        = 0x0010,
892         NETIF_MSG_IFUP          = 0x0020,
893         NETIF_MSG_RX_ERR        = 0x0040,
894         NETIF_MSG_TX_ERR        = 0x0080,
895         NETIF_MSG_TX_QUEUED     = 0x0100,
896         NETIF_MSG_INTR          = 0x0200,
897         NETIF_MSG_TX_DONE       = 0x0400,
898         NETIF_MSG_RX_STATUS     = 0x0800,
899         NETIF_MSG_PKTDATA       = 0x1000,
900         NETIF_MSG_HW            = 0x2000,
901         NETIF_MSG_WOL           = 0x4000,
902 };
903 
904 
905 /*
906  * printk / logging functions
907  */
908 
909 #define en_print(level, priv, format, arg...)                   \
910         {                                                       \
911         if ((priv)->registered)                                 \
912                 printk(level "%s: %s: " format, DRV_NAME,       \
913                         (priv)->dev->if_xname, ## arg); \
914         else                                                    \
915                 printk(level "%s: %s: Port %d: " format,        \
916                         DRV_NAME, dev_name(&(priv)->mdev->pdev->dev), \
917                         (priv)->port, ## arg);                  \
918         }
919 
920 
921 #define en_dbg(mlevel, priv, format, arg...)			\
922 do {								\
923 	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
924 		en_print(KERN_DEBUG, priv, format, ##arg);	\
925 } while (0)
926 #define en_warn(priv, format, arg...)			\
927 	en_print(KERN_WARNING, priv, format, ##arg)
928 #define en_err(priv, format, arg...)			\
929 	en_print(KERN_ERR, priv, format, ##arg)
930 #define en_info(priv, format, arg...)			\
931 	en_print(KERN_INFO, priv, format, ## arg)
932 
933 #define mlx4_err(mdev, format, arg...)			\
934 	pr_err("%s %s: " format, DRV_NAME,		\
935 	       dev_name(&(mdev)->pdev->dev), ##arg)
936 #define mlx4_info(mdev, format, arg...)			\
937 	pr_info("%s %s: " format, DRV_NAME,		\
938 		dev_name(&(mdev)->pdev->dev), ##arg)
939 #define mlx4_warn(mdev, format, arg...)			\
940 	pr_warning("%s %s: " format, DRV_NAME,		\
941 		   dev_name(&(mdev)->pdev->dev), ##arg)
942 
943 #endif
944