xref: /freebsd/sys/dev/mlx4/mlx4_core/mlx4.h (revision a25896ca1270e25b657ceaa8d47d5699515f5c25)
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
5  * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7  *
8  * This software is available to you under a choice of one of two
9  * licenses.  You may choose to be licensed under the terms of the GNU
10  * General Public License (GPL) Version 2, available from the file
11  * COPYING in the main directory of this source tree, or the
12  * OpenIB.org BSD license below:
13  *
14  *     Redistribution and use in source and binary forms, with or
15  *     without modification, are permitted provided that the following
16  *     conditions are met:
17  *
18  *      - Redistributions of source code must retain the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer.
21  *
22  *      - Redistributions in binary form must reproduce the above
23  *        copyright notice, this list of conditions and the following
24  *        disclaimer in the documentation and/or other materials
25  *        provided with the distribution.
26  *
27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34  * SOFTWARE.
35  */
36 
37 #ifndef MLX4_H
38 #define MLX4_H
39 
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/device.h>
47 #include <linux/rwsem.h>
48 #include <dev/mlx4/device.h>
49 #include <dev/mlx4/driver.h>
50 #include <dev/mlx4/doorbell.h>
51 #include <dev/mlx4/cmd.h>
52 #include <dev/mlx4/mlx4_core/fw_qos.h>
53 
54 #define DRV_NAME	"mlx4_core"
55 #define PFX		DRV_NAME ": "
56 #define DRV_VERSION	"3.4.1"
57 #define DRV_RELDATE	"October 2017"
58 
59 #define MLX4_FS_UDP_UC_EN		(1 << 1)
60 #define MLX4_FS_TCP_UC_EN		(1 << 2)
61 #define MLX4_FS_NUM_OF_L2_ADDR		8
62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE	7
63 #define MLX4_FS_NUM_MCG			(1 << 17)
64 
65 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
66 
67 #define MLX4_QUERY_IF_STAT_RESET	BIT(31)
68 
69 enum {
70 	MLX4_HCR_BASE		= 0x80680,
71 	MLX4_HCR_SIZE		= 0x0001c,
72 	MLX4_CLR_INT_SIZE	= 0x00008,
73 	MLX4_SLAVE_COMM_BASE	= 0x0,
74 	MLX4_COMM_PAGESIZE	= 0x1000,
75 	MLX4_CLOCK_SIZE		= 0x00008,
76 	MLX4_COMM_CHAN_CAPS	= 0x8,
77 	MLX4_COMM_CHAN_FLAGS	= 0xc
78 };
79 
80 enum {
81 	MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
82 	MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
83 	MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
84 	MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
85 	MLX4_MTT_ENTRY_PER_SEG	= 8,
86 };
87 
88 enum {
89 	MLX4_NUM_PDS		= 1 << 15
90 };
91 
92 enum {
93 	MLX4_CMPT_TYPE_QP	= 0,
94 	MLX4_CMPT_TYPE_SRQ	= 1,
95 	MLX4_CMPT_TYPE_CQ	= 2,
96 	MLX4_CMPT_TYPE_EQ	= 3,
97 	MLX4_CMPT_NUM_TYPE
98 };
99 
100 enum {
101 	MLX4_CMPT_SHIFT		= 24,
102 	MLX4_NUM_CMPTS		= MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
103 };
104 
105 enum mlx4_mpt_state {
106 	MLX4_MPT_DISABLED = 0,
107 	MLX4_MPT_EN_HW,
108 	MLX4_MPT_EN_SW
109 };
110 
111 #define MLX4_COMM_TIME		10000
112 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
113 #define MLX4_COMM_CMD_NA_OP    0x0
114 
115 
116 enum {
117 	MLX4_COMM_CMD_RESET,
118 	MLX4_COMM_CMD_VHCR0,
119 	MLX4_COMM_CMD_VHCR1,
120 	MLX4_COMM_CMD_VHCR2,
121 	MLX4_COMM_CMD_VHCR_EN,
122 	MLX4_COMM_CMD_VHCR_POST,
123 	MLX4_COMM_CMD_FLR = 254
124 };
125 
126 enum {
127 	MLX4_VF_SMI_DISABLED,
128 	MLX4_VF_SMI_ENABLED
129 };
130 
131 /*The flag indicates that the slave should delay the RESET cmd*/
132 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
133 /*indicates how many retries will be done if we are in the middle of FLR*/
134 #define NUM_OF_RESET_RETRIES	10
135 #define SLEEP_TIME_IN_RESET	(2 * 1000)
136 enum mlx4_resource {
137 	RES_QP,
138 	RES_CQ,
139 	RES_SRQ,
140 	RES_XRCD,
141 	RES_MPT,
142 	RES_MTT,
143 	RES_MAC,
144 	RES_VLAN,
145 	RES_NPORT_ID,
146 	RES_COUNTER,
147 	RES_FS_RULE,
148 	RES_EQ,
149 	MLX4_NUM_OF_RESOURCE_TYPE
150 };
151 
152 enum mlx4_alloc_mode {
153 	RES_OP_RESERVE,
154 	RES_OP_RESERVE_AND_MAP,
155 	RES_OP_MAP_ICM,
156 };
157 
158 enum mlx4_res_tracker_free_type {
159 	RES_TR_FREE_ALL,
160 	RES_TR_FREE_SLAVES_ONLY,
161 	RES_TR_FREE_STRUCTS_ONLY,
162 };
163 
164 /*
165  *Virtual HCR structures.
166  * mlx4_vhcr is the sw representation, in machine endianness
167  *
168  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
169  * to FW to go through communication channel.
170  * It is big endian, and has the same structure as the physical HCR
171  * used by command interface
172  */
173 struct mlx4_vhcr {
174 	u64	in_param;
175 	u64	out_param;
176 	u32	in_modifier;
177 	u32	errno;
178 	u16	op;
179 	u16	token;
180 	u8	op_modifier;
181 	u8	e_bit;
182 };
183 
184 struct mlx4_vhcr_cmd {
185 	__be64 in_param;
186 	__be32 in_modifier;
187 	u32 reserved1;
188 	__be64 out_param;
189 	__be16 token;
190 	u16 reserved;
191 	u8 status;
192 	u8 flags;
193 	__be16 opcode;
194 };
195 
196 struct mlx4_cmd_info {
197 	u16 opcode;
198 	bool has_inbox;
199 	bool has_outbox;
200 	bool out_is_imm;
201 	bool encode_slave_id;
202 	int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
203 		      struct mlx4_cmd_mailbox *inbox);
204 	int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 		       struct mlx4_cmd_mailbox *inbox,
206 		       struct mlx4_cmd_mailbox *outbox,
207 		       struct mlx4_cmd_info *cmd);
208 };
209 
210 #ifdef CONFIG_MLX4_DEBUG
211 extern int mlx4_debug_level;
212 #else /* CONFIG_MLX4_DEBUG */
213 #define mlx4_debug_level	(0)
214 #endif /* CONFIG_MLX4_DEBUG */
215 
216 #define mlx4_dbg(mdev, format, ...)					\
217 do {									\
218 	if (mlx4_debug_level)						\
219 		dev_printk(KERN_DEBUG,					\
220 			   &(mdev)->persist->pdev->dev, format,		\
221 			   ##__VA_ARGS__);				\
222 } while (0)
223 
224 #define mlx4_err(mdev, format, ...)					\
225 	dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
226 #define mlx4_info(mdev, format, ...)					\
227 	dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
228 #define mlx4_warn(mdev, format, ...)					\
229 	dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
230 
231 extern int mlx4_log_num_mgm_entry_size;
232 extern int log_mtts_per_seg;
233 extern int mlx4_internal_err_reset;
234 
235 #define MLX4_MAX_NUM_SLAVES	(min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
236 				     MLX4_MFUNC_MAX))
237 #define ALL_SLAVES 0xff
238 
239 struct mlx4_bitmap {
240 	u32			last;
241 	u32			top;
242 	u32			max;
243 	u32                     reserved_top;
244 	u32			mask;
245 	u32			avail;
246 	u32			effective_len;
247 	spinlock_t		lock;
248 	unsigned long	       *table;
249 };
250 
251 struct mlx4_buddy {
252 	unsigned long	      **bits;
253 	unsigned int	       *num_free;
254 	u32			max_order;
255 	spinlock_t		lock;
256 };
257 
258 struct mlx4_icm;
259 
260 struct mlx4_icm_table {
261 	u64			virt;
262 	int			num_icm;
263 	u32			num_obj;
264 	int			obj_size;
265 	int			lowmem;
266 	int			coherent;
267 	struct mutex		mutex;
268 	struct mlx4_icm	      **icm;
269 };
270 
271 #define MLX4_MPT_FLAG_SW_OWNS	    (0xfUL << 28)
272 #define MLX4_MPT_FLAG_FREE	    (0x3UL << 28)
273 #define MLX4_MPT_FLAG_MIO	    (1 << 17)
274 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
275 #define MLX4_MPT_FLAG_PHYSICAL	    (1 <<  9)
276 #define MLX4_MPT_FLAG_REGION	    (1 <<  8)
277 
278 #define MLX4_MPT_PD_MASK	    (0x1FFFFUL)
279 #define MLX4_MPT_PD_VF_MASK	    (0xFE0000UL)
280 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
281 #define MLX4_MPT_PD_FLAG_RAE	    (1 << 28)
282 #define MLX4_MPT_PD_FLAG_EN_INV	    (3 << 24)
283 
284 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
285 
286 #define MLX4_MPT_STATUS_SW		0xF0
287 #define MLX4_MPT_STATUS_HW		0x00
288 
289 #define MLX4_CQE_SIZE_MASK_STRIDE	0x3
290 #define MLX4_EQE_SIZE_MASK_STRIDE	0x30
291 
292 #define MLX4_EQ_ASYNC			0
293 #define MLX4_EQ_TO_CQ_VECTOR(vector)	((vector) - \
294 					 !!((int)(vector) >= MLX4_EQ_ASYNC))
295 #define MLX4_CQ_TO_EQ_VECTOR(vector)	((vector) + \
296 					 !!((int)(vector) >= MLX4_EQ_ASYNC))
297 
298 /*
299  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
300  */
301 struct mlx4_mpt_entry {
302 	__be32 flags;
303 	__be32 qpn;
304 	__be32 key;
305 	__be32 pd_flags;
306 	__be64 start;
307 	__be64 length;
308 	__be32 lkey;
309 	__be32 win_cnt;
310 	u8	reserved1[3];
311 	u8	mtt_rep;
312 	__be64 mtt_addr;
313 	__be32 mtt_sz;
314 	__be32 entity_size;
315 	__be32 first_byte_offset;
316 } __packed;
317 
318 /*
319  * Must be packed because start is 64 bits but only aligned to 32 bits.
320  */
321 struct mlx4_eq_context {
322 	__be32			flags;
323 	u16			reserved1[3];
324 	__be16			page_offset;
325 	u8			log_eq_size;
326 	u8			reserved2[4];
327 	u8			eq_period;
328 	u8			reserved3;
329 	u8			eq_max_count;
330 	u8			reserved4[3];
331 	u8			intr;
332 	u8			log_page_size;
333 	u8			reserved5[2];
334 	u8			mtt_base_addr_h;
335 	__be32			mtt_base_addr_l;
336 	u32			reserved6[2];
337 	__be32			consumer_index;
338 	__be32			producer_index;
339 	u32			reserved7[4];
340 };
341 
342 struct mlx4_cq_context {
343 	__be32			flags;
344 	u16			reserved1[3];
345 	__be16			page_offset;
346 	__be32			logsize_usrpage;
347 	__be16			cq_period;
348 	__be16			cq_max_count;
349 	u8			reserved2[3];
350 	u8			comp_eqn;
351 	u8			log_page_size;
352 	u8			reserved3[2];
353 	u8			mtt_base_addr_h;
354 	__be32			mtt_base_addr_l;
355 	__be32			last_notified_index;
356 	__be32			solicit_producer_index;
357 	__be32			consumer_index;
358 	__be32			producer_index;
359 	u32			reserved4[2];
360 	__be64			db_rec_addr;
361 };
362 
363 struct mlx4_srq_context {
364 	__be32			state_logsize_srqn;
365 	u8			logstride;
366 	u8			reserved1;
367 	__be16			xrcd;
368 	__be32			pg_offset_cqn;
369 	u32			reserved2;
370 	u8			log_page_size;
371 	u8			reserved3[2];
372 	u8			mtt_base_addr_h;
373 	__be32			mtt_base_addr_l;
374 	__be32			pd;
375 	__be16			limit_watermark;
376 	__be16			wqe_cnt;
377 	u16			reserved4;
378 	__be16			wqe_counter;
379 	u32			reserved5;
380 	__be64			db_rec_addr;
381 };
382 
383 struct mlx4_eq {
384 	struct mlx4_dev	       *dev;
385 	void __iomem	       *doorbell;
386 	int			eqn;
387 	u32			cons_index;
388 	u16			irq;
389 	u16			have_irq;
390 	int			nent;
391 	struct mlx4_buf_list   *page_list;
392 	struct mlx4_mtt		mtt;
393 	u32			ncqs;
394 	struct mlx4_active_ports actv_ports;
395 	u32			ref_count;
396 	int			affinity_cpu_id;
397 };
398 
399 struct mlx4_slave_eqe {
400 	u8 type;
401 	u8 port;
402 	u32 param;
403 };
404 
405 struct mlx4_slave_event_eq_info {
406 	int eqn;
407 	u16 token;
408 };
409 
410 struct mlx4_profile {
411 	int			num_qp;
412 	int			rdmarc_per_qp;
413 	int			num_srq;
414 	int			num_cq;
415 	int			num_mcg;
416 	int			num_mpt;
417 	unsigned		num_mtt;
418 };
419 
420 struct mlx4_fw {
421 	u64			clr_int_base;
422 	u64			catas_offset;
423 	u64			comm_base;
424 	u64			clock_offset;
425 	struct mlx4_icm	       *fw_icm;
426 	struct mlx4_icm	       *aux_icm;
427 	u32			catas_size;
428 	u16			fw_pages;
429 	u8			clr_int_bar;
430 	u8			catas_bar;
431 	u8			comm_bar;
432 	u8			clock_bar;
433 };
434 
435 struct mlx4_comm {
436 	u32			slave_write;
437 	u32			slave_read;
438 };
439 
440 enum {
441 	MLX4_MCAST_CONFIG       = 0,
442 	MLX4_MCAST_DISABLE      = 1,
443 	MLX4_MCAST_ENABLE       = 2,
444 };
445 
446 #define VLAN_FLTR_SIZE	128
447 
448 struct mlx4_vlan_fltr {
449 	__be32 entry[VLAN_FLTR_SIZE];
450 };
451 
452 struct mlx4_mcast_entry {
453 	struct list_head list;
454 	u64 addr;
455 };
456 
457 struct mlx4_promisc_qp {
458 	struct list_head list;
459 	u32 qpn;
460 };
461 
462 struct mlx4_steer_index {
463 	struct list_head list;
464 	unsigned int index;
465 	struct list_head duplicates;
466 };
467 
468 #define MLX4_EVENT_TYPES_NUM 64
469 
470 struct mlx4_slave_state {
471 	u8 comm_toggle;
472 	u8 last_cmd;
473 	u8 init_port_mask;
474 	bool active;
475 	bool old_vlan_api;
476 	bool vst_qinq_supported;
477 	u8 function;
478 	dma_addr_t vhcr_dma;
479 	u16 mtu[MLX4_MAX_PORTS + 1];
480 	__be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
481 	struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
482 	struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
483 	struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
484 	/* event type to eq number lookup */
485 	struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
486 	u16 eq_pi;
487 	u16 eq_ci;
488 	spinlock_t lock;
489 	/*initialized via the kzalloc*/
490 	u8 is_slave_going_down;
491 	u32 cookie;
492 	enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
493 };
494 
495 #define MLX4_VGT 4095
496 #define NO_INDX  (-1)
497 
498 struct mlx4_vport_state {
499 	u64 mac;
500 	u16 default_vlan;
501 	u8  default_qos;
502 	__be16 vlan_proto;
503 	u32 tx_rate;
504 	bool spoofchk;
505 	u8 qos_vport;
506 	__be64 guid;
507 };
508 
509 struct mlx4_vf_admin_state {
510 	struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
511 	u8 enable_smi[MLX4_MAX_PORTS + 1];
512 };
513 
514 struct mlx4_vport_oper_state {
515 	struct mlx4_vport_state state;
516 	int mac_idx;
517 	int vlan_idx;
518 };
519 
520 struct mlx4_vf_oper_state {
521 	struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
522 	u8 smi_enabled[MLX4_MAX_PORTS + 1];
523 };
524 
525 struct slave_list {
526 	struct mutex mutex;
527 	struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
528 };
529 
530 struct resource_allocator {
531 	spinlock_t alloc_lock; /* protect quotas */
532 	union {
533 		int res_reserved;
534 		int res_port_rsvd[MLX4_MAX_PORTS];
535 	};
536 	union {
537 		int res_free;
538 		int res_port_free[MLX4_MAX_PORTS];
539 	};
540 	int *quota;
541 	int *allocated;
542 	int *guaranteed;
543 };
544 
545 struct mlx4_resource_tracker {
546 	spinlock_t lock;
547 	/* tree for each resources */
548 	struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
549 	/* num_of_slave's lists, one per slave */
550 	struct slave_list *slave_list;
551 	struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
552 };
553 
554 #define SLAVE_EVENT_EQ_SIZE	128
555 struct mlx4_slave_event_eq {
556 	u32 eqn;
557 	u32 cons;
558 	u32 prod;
559 	spinlock_t event_lock;
560 	struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
561 };
562 
563 struct mlx4_qos_manager {
564 	int num_of_qos_vfs;
565 	DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
566 };
567 
568 struct mlx4_master_qp0_state {
569 	int proxy_qp0_active;
570 	int qp0_active;
571 	int port_active;
572 };
573 
574 struct mlx4_mfunc_master_ctx {
575 	struct mlx4_slave_state *slave_state;
576 	struct mlx4_vf_admin_state *vf_admin;
577 	struct mlx4_vf_oper_state *vf_oper;
578 	struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
579 	int			init_port_ref[MLX4_MAX_PORTS + 1];
580 	u16			max_mtu[MLX4_MAX_PORTS + 1];
581 	u8			pptx;
582 	u8			pprx;
583 	int			disable_mcast_ref[MLX4_MAX_PORTS + 1];
584 	struct mlx4_resource_tracker res_tracker;
585 	struct workqueue_struct *comm_wq;
586 	struct work_struct	comm_work;
587 	struct work_struct	slave_event_work;
588 	struct work_struct	slave_flr_event_work;
589 	spinlock_t		slave_state_lock;
590 	__be32			comm_arm_bit_vector[4];
591 	struct mlx4_eqe		cmd_eqe;
592 	struct mlx4_slave_event_eq slave_eq;
593 	struct mutex		gen_eqe_mutex[MLX4_MFUNC_MAX];
594 	struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
595 };
596 
597 struct mlx4_mfunc {
598 	struct mlx4_comm __iomem       *comm;
599 	struct mlx4_vhcr_cmd	       *vhcr;
600 	dma_addr_t			vhcr_dma;
601 
602 	struct mlx4_mfunc_master_ctx	master;
603 };
604 
605 #define MGM_QPN_MASK       0x00FFFFFF
606 #define MGM_BLCK_LB_BIT    30
607 
608 struct mlx4_mgm {
609 	__be32			next_gid_index;
610 	__be32			members_count;
611 	u32			reserved[2];
612 	u8			gid[16];
613 	__be32			qp[MLX4_MAX_QP_PER_MGM];
614 };
615 
616 struct mlx4_cmd {
617 	struct pci_pool	       *pool;
618 	void __iomem	       *hcr;
619 	struct mutex		slave_cmd_mutex;
620 	struct semaphore	poll_sem;
621 	struct semaphore	event_sem;
622 	struct rw_semaphore	switch_sem;
623 	int			max_cmds;
624 	spinlock_t		context_lock;
625 	int			free_head;
626 	struct mlx4_cmd_context *context;
627 	u16			token_mask;
628 	u8			use_events;
629 	u8			toggle;
630 	u8			comm_toggle;
631 	u8			initialized;
632 };
633 
634 enum {
635 	MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
636 	MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
637 	MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
638 };
639 struct mlx4_vf_immed_vlan_work {
640 	struct work_struct	work;
641 	struct mlx4_priv	*priv;
642 	int			flags;
643 	int			slave;
644 	int			vlan_ix;
645 	int			orig_vlan_ix;
646 	u8			port;
647 	u8			qos;
648 	u8                      qos_vport;
649 	u16			vlan_id;
650 	u16			orig_vlan_id;
651 	__be16			vlan_proto;
652 };
653 
654 
655 struct mlx4_uar_table {
656 	struct mlx4_bitmap	bitmap;
657 };
658 
659 struct mlx4_mr_table {
660 	struct mlx4_bitmap	mpt_bitmap;
661 	struct mlx4_buddy	mtt_buddy;
662 	u64			mtt_base;
663 	u64			mpt_base;
664 	struct mlx4_icm_table	mtt_table;
665 	struct mlx4_icm_table	dmpt_table;
666 };
667 
668 struct mlx4_cq_table {
669 	struct mlx4_bitmap	bitmap;
670 	spinlock_t		lock;
671 	struct radix_tree_root	tree;
672 	struct mlx4_icm_table	table;
673 	struct mlx4_icm_table	cmpt_table;
674 };
675 
676 struct mlx4_eq_table {
677 	struct mlx4_bitmap	bitmap;
678 	char		       *irq_names;
679 	void __iomem	       *clr_int;
680 	void __iomem	      **uar_map;
681 	u32			clr_mask;
682 	struct mlx4_eq	       *eq;
683 	struct mlx4_icm_table	table;
684 	struct mlx4_icm_table	cmpt_table;
685 	int			have_irq;
686 	u8			inta_pin;
687 };
688 
689 struct mlx4_srq_table {
690 	struct mlx4_bitmap	bitmap;
691 	spinlock_t		lock;
692 	struct radix_tree_root	tree;
693 	struct mlx4_icm_table	table;
694 	struct mlx4_icm_table	cmpt_table;
695 };
696 
697 enum mlx4_qp_table_zones {
698 	MLX4_QP_TABLE_ZONE_GENERAL,
699 	MLX4_QP_TABLE_ZONE_RSS,
700 	MLX4_QP_TABLE_ZONE_RAW_ETH,
701 	MLX4_QP_TABLE_ZONE_NUM
702 };
703 
704 struct mlx4_qp_table {
705 	struct mlx4_bitmap	*bitmap_gen;
706 	struct mlx4_zone_allocator *zones;
707 	u32			zones_uids[MLX4_QP_TABLE_ZONE_NUM];
708 	u32			rdmarc_base;
709 	int			rdmarc_shift;
710 	spinlock_t		lock;
711 	struct mlx4_icm_table	qp_table;
712 	struct mlx4_icm_table	auxc_table;
713 	struct mlx4_icm_table	altc_table;
714 	struct mlx4_icm_table	rdmarc_table;
715 	struct mlx4_icm_table	cmpt_table;
716 };
717 
718 struct mlx4_mcg_table {
719 	struct mutex		mutex;
720 	struct mlx4_bitmap	bitmap;
721 	struct mlx4_icm_table	table;
722 };
723 
724 struct mlx4_catas_err {
725 	u32 __iomem	       *map;
726 	struct timer_list	timer;
727 	struct list_head	list;
728 };
729 
730 #define MLX4_MAX_MAC_NUM	128
731 #define MLX4_MAC_TABLE_SIZE	(MLX4_MAX_MAC_NUM << 3)
732 
733 struct mlx4_mac_table {
734 	__be64			entries[MLX4_MAX_MAC_NUM];
735 	int			refs[MLX4_MAX_MAC_NUM];
736 	bool			is_dup[MLX4_MAX_MAC_NUM];
737 	struct mutex		mutex;
738 	int			total;
739 	int			max;
740 };
741 
742 #define MLX4_ROCE_GID_ENTRY_SIZE	16
743 
744 struct mlx4_roce_gid_entry {
745 	u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
746 };
747 
748 struct mlx4_roce_gid_table {
749 	struct mlx4_roce_gid_entry	roce_gids[MLX4_ROCE_MAX_GIDS];
750 	struct mutex			mutex;
751 };
752 
753 #define MLX4_MAX_VLAN_NUM	128
754 #define MLX4_VLAN_TABLE_SIZE	(MLX4_MAX_VLAN_NUM << 2)
755 
756 struct mlx4_vlan_table {
757 	__be32			entries[MLX4_MAX_VLAN_NUM];
758 	int			refs[MLX4_MAX_VLAN_NUM];
759 	int			is_dup[MLX4_MAX_VLAN_NUM];
760 	struct mutex		mutex;
761 	int			total;
762 	int			max;
763 };
764 
765 #define SET_PORT_GEN_ALL_VALID		0x7
766 #define SET_PORT_PROMISC_SHIFT		31
767 #define SET_PORT_MC_PROMISC_SHIFT	30
768 
769 enum {
770 	MCAST_DIRECT_ONLY	= 0,
771 	MCAST_DIRECT		= 1,
772 	MCAST_DEFAULT		= 2
773 };
774 
775 struct mlx4_set_port_general_context {
776 	u16 reserved1;
777 	u8 v_ignore_fcs;
778 	u8 flags;
779 	union {
780 		u8 ignore_fcs;
781 		u8 roce_mode;
782 	};
783 	u8 reserved2;
784 	__be16 mtu;
785 	u8 pptx;
786 	u8 pfctx;
787 	u16 reserved3;
788 	u8 pprx;
789 	u8 pfcrx;
790 	u16 reserved4;
791 	u32 reserved5;
792 	u8 phv_en;
793 	u8 reserved6[3];
794 };
795 
796 struct mlx4_set_port_rqp_calc_context {
797 	__be32 base_qpn;
798 	u8 rererved;
799 	u8 n_mac;
800 	u8 n_vlan;
801 	u8 n_prio;
802 	u8 reserved2[3];
803 	u8 mac_miss;
804 	u8 intra_no_vlan;
805 	u8 no_vlan;
806 	u8 intra_vlan_miss;
807 	u8 vlan_miss;
808 	u8 reserved3[3];
809 	u8 no_vlan_prio;
810 	__be32 promisc;
811 	__be32 mcast;
812 };
813 
814 struct mlx4_port_info {
815 	struct mlx4_dev	       *dev;
816 	int			port;
817 	char			dev_name[16];
818 	struct device_attribute port_attr;
819 	enum mlx4_port_type	tmp_type;
820 	char			dev_mtu_name[16];
821 	struct device_attribute port_mtu_attr;
822 	struct mlx4_mac_table	mac_table;
823 	struct mlx4_vlan_table	vlan_table;
824 	struct mlx4_roce_gid_table gid_table;
825 	int			base_qpn;
826 };
827 
828 struct mlx4_sense {
829 	struct mlx4_dev		*dev;
830 	u8			do_sense_port[MLX4_MAX_PORTS + 1];
831 	u8			sense_allowed[MLX4_MAX_PORTS + 1];
832 	struct delayed_work	sense_poll;
833 	int			gone;
834 };
835 
836 struct mlx4_msix_ctl {
837 	DECLARE_BITMAP(pool_bm, MAX_MSIX);
838 	struct mutex	pool_lock;
839 };
840 
841 struct mlx4_steer {
842 	struct list_head promisc_qps[MLX4_NUM_STEERS];
843 	struct list_head steer_entries[MLX4_NUM_STEERS];
844 };
845 
846 enum {
847 	MLX4_PCI_DEV_IS_VF		= 1 << 0,
848 	MLX4_PCI_DEV_FORCE_SENSE_PORT	= 1 << 1,
849 };
850 
851 enum {
852 	MLX4_NO_RR	= 0,
853 	MLX4_USE_RR	= 1,
854 };
855 
856 struct mlx4_priv {
857 	struct mlx4_dev		dev;
858 
859 	struct list_head	dev_list;
860 	struct list_head	ctx_list;
861 	spinlock_t		ctx_lock;
862 
863 	int			pci_dev_data;
864 	int                     removed;
865 
866 	struct list_head        pgdir_list;
867 	struct mutex            pgdir_mutex;
868 
869 	struct mlx4_fw		fw;
870 	struct mlx4_cmd		cmd;
871 	struct mlx4_mfunc	mfunc;
872 
873 	struct mlx4_bitmap	pd_bitmap;
874 	struct mlx4_bitmap	xrcd_bitmap;
875 	struct mlx4_uar_table	uar_table;
876 	struct mlx4_mr_table	mr_table;
877 	struct mlx4_cq_table	cq_table;
878 	struct mlx4_eq_table	eq_table;
879 	struct mlx4_srq_table	srq_table;
880 	struct mlx4_qp_table	qp_table;
881 	struct mlx4_mcg_table	mcg_table;
882 	struct mlx4_bitmap	counters_bitmap;
883 	int			def_counter[MLX4_MAX_PORTS];
884 
885 	struct mlx4_catas_err	catas_err;
886 
887 	void __iomem	       *clr_base;
888 
889 	struct mlx4_uar		driver_uar;
890 	void __iomem	       *kar;
891 	struct mlx4_port_info	port[MLX4_MAX_PORTS + 1];
892 	struct mlx4_sense       sense;
893 	struct mutex		port_mutex;
894 	struct mlx4_msix_ctl	msix_ctl;
895 	struct mlx4_steer	*steer;
896 	struct list_head	bf_list;
897 	struct mutex		bf_mutex;
898 	struct io_mapping	*bf_mapping;
899 	void __iomem            *clock_mapping;
900 	int			reserved_mtts;
901 	int			fs_hash_mode;
902 	u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
903 	struct mlx4_port_map	v2p; /* cached port mapping configuration */
904 	struct mutex		bond_mutex; /* for bond mode */
905 	__be64			slave_node_guids[MLX4_MFUNC_MAX];
906 
907 	atomic_t		opreq_count;
908 	struct work_struct	opreq_task;
909 };
910 
911 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
912 {
913 	return container_of(dev, struct mlx4_priv, dev);
914 }
915 
916 #define MLX4_SENSE_RANGE	(HZ * 3)
917 
918 extern struct workqueue_struct *mlx4_wq;
919 
920 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
921 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
922 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
923 			    int align, u32 skip_mask);
924 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
925 			    int use_rr);
926 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
927 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
928 		     u32 reserved_bot, u32 resetrved_top);
929 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
930 
931 int mlx4_reset(struct mlx4_dev *dev);
932 
933 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
934 void mlx4_free_eq_table(struct mlx4_dev *dev);
935 
936 int mlx4_init_pd_table(struct mlx4_dev *dev);
937 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
938 int mlx4_init_uar_table(struct mlx4_dev *dev);
939 int mlx4_init_mr_table(struct mlx4_dev *dev);
940 int mlx4_init_eq_table(struct mlx4_dev *dev);
941 int mlx4_init_cq_table(struct mlx4_dev *dev);
942 int mlx4_init_qp_table(struct mlx4_dev *dev);
943 int mlx4_init_srq_table(struct mlx4_dev *dev);
944 int mlx4_init_mcg_table(struct mlx4_dev *dev);
945 
946 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
947 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
948 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
949 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
950 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
951 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
952 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
953 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
954 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
955 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
956 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
957 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
958 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
959 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
960 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
961 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
962 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
963 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
964 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
965 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
966 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
967 
968 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
969 			   struct mlx4_vhcr *vhcr,
970 			   struct mlx4_cmd_mailbox *inbox,
971 			   struct mlx4_cmd_mailbox *outbox,
972 			   struct mlx4_cmd_info *cmd);
973 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
974 			   struct mlx4_vhcr *vhcr,
975 			   struct mlx4_cmd_mailbox *inbox,
976 			   struct mlx4_cmd_mailbox *outbox,
977 			   struct mlx4_cmd_info *cmd);
978 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
979 			   struct mlx4_vhcr *vhcr,
980 			   struct mlx4_cmd_mailbox *inbox,
981 			   struct mlx4_cmd_mailbox *outbox,
982 			   struct mlx4_cmd_info *cmd);
983 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
984 			   struct mlx4_vhcr *vhcr,
985 			   struct mlx4_cmd_mailbox *inbox,
986 			   struct mlx4_cmd_mailbox *outbox,
987 			   struct mlx4_cmd_info *cmd);
988 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
989 			   struct mlx4_vhcr *vhcr,
990 			   struct mlx4_cmd_mailbox *inbox,
991 			   struct mlx4_cmd_mailbox *outbox,
992 			   struct mlx4_cmd_info *cmd);
993 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
994 			  struct mlx4_vhcr *vhcr,
995 			  struct mlx4_cmd_mailbox *inbox,
996 			  struct mlx4_cmd_mailbox *outbox,
997 			  struct mlx4_cmd_info *cmd);
998 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
999 			    struct mlx4_vhcr *vhcr,
1000 			    struct mlx4_cmd_mailbox *inbox,
1001 			    struct mlx4_cmd_mailbox *outbox,
1002 			    struct mlx4_cmd_info *cmd);
1003 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1004 		     struct mlx4_vhcr *vhcr,
1005 		     struct mlx4_cmd_mailbox *inbox,
1006 		     struct mlx4_cmd_mailbox *outbox,
1007 		     struct mlx4_cmd_info *cmd);
1008 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1009 			    int *base, u8 flags);
1010 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1011 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1012 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1013 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1014 		     int start_index, int npages, u64 *page_list);
1015 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1016 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1017 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1018 			  struct mlx4_counter *data);
1019 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1020 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1021 
1022 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1023 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1024 int mlx4_catas_init(struct mlx4_dev *dev);
1025 void mlx4_catas_end(struct mlx4_dev *dev);
1026 int mlx4_restart_one(struct pci_dev *pdev);
1027 int mlx4_register_device(struct mlx4_dev *dev);
1028 void mlx4_unregister_device(struct mlx4_dev *dev);
1029 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1030 			 unsigned long param);
1031 
1032 struct mlx4_dev_cap;
1033 struct mlx4_init_hca_param;
1034 
1035 u64 mlx4_make_profile(struct mlx4_dev *dev,
1036 		      struct mlx4_profile *request,
1037 		      struct mlx4_dev_cap *dev_cap,
1038 		      struct mlx4_init_hca_param *init_hca);
1039 void mlx4_master_comm_channel(struct work_struct *work);
1040 void mlx4_gen_slave_eqe(struct work_struct *work);
1041 void mlx4_master_handle_slave_flr(struct work_struct *work);
1042 
1043 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1044 			   struct mlx4_vhcr *vhcr,
1045 			   struct mlx4_cmd_mailbox *inbox,
1046 			   struct mlx4_cmd_mailbox *outbox,
1047 			   struct mlx4_cmd_info *cmd);
1048 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1049 			  struct mlx4_vhcr *vhcr,
1050 			  struct mlx4_cmd_mailbox *inbox,
1051 			  struct mlx4_cmd_mailbox *outbox,
1052 			  struct mlx4_cmd_info *cmd);
1053 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1054 			struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1055 			struct mlx4_cmd_mailbox *outbox,
1056 			struct mlx4_cmd_info *cmd);
1057 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1058 			  struct mlx4_vhcr *vhcr,
1059 			  struct mlx4_cmd_mailbox *inbox,
1060 			  struct mlx4_cmd_mailbox *outbox,
1061 			  struct mlx4_cmd_info *cmd);
1062 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1063 			    struct mlx4_vhcr *vhcr,
1064 			    struct mlx4_cmd_mailbox *inbox,
1065 			    struct mlx4_cmd_mailbox *outbox,
1066 			  struct mlx4_cmd_info *cmd);
1067 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1068 			  struct mlx4_vhcr *vhcr,
1069 			  struct mlx4_cmd_mailbox *inbox,
1070 			  struct mlx4_cmd_mailbox *outbox,
1071 			  struct mlx4_cmd_info *cmd);
1072 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1073 			  struct mlx4_vhcr *vhcr,
1074 			  struct mlx4_cmd_mailbox *inbox,
1075 			  struct mlx4_cmd_mailbox *outbox,
1076 			  struct mlx4_cmd_info *cmd);
1077 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1078 			  struct mlx4_vhcr *vhcr,
1079 			  struct mlx4_cmd_mailbox *inbox,
1080 			  struct mlx4_cmd_mailbox *outbox,
1081 			  struct mlx4_cmd_info *cmd);
1082 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1083 			  struct mlx4_vhcr *vhcr,
1084 			  struct mlx4_cmd_mailbox *inbox,
1085 			  struct mlx4_cmd_mailbox *outbox,
1086 			  struct mlx4_cmd_info *cmd);
1087 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1088 			  struct mlx4_vhcr *vhcr,
1089 			  struct mlx4_cmd_mailbox *inbox,
1090 			  struct mlx4_cmd_mailbox *outbox,
1091 			   struct mlx4_cmd_info *cmd);
1092 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1093 			   struct mlx4_vhcr *vhcr,
1094 			   struct mlx4_cmd_mailbox *inbox,
1095 			   struct mlx4_cmd_mailbox *outbox,
1096 			   struct mlx4_cmd_info *cmd);
1097 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1098 			   struct mlx4_vhcr *vhcr,
1099 			   struct mlx4_cmd_mailbox *inbox,
1100 			   struct mlx4_cmd_mailbox *outbox,
1101 			   struct mlx4_cmd_info *cmd);
1102 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1103 			   struct mlx4_vhcr *vhcr,
1104 			   struct mlx4_cmd_mailbox *inbox,
1105 			   struct mlx4_cmd_mailbox *outbox,
1106 			   struct mlx4_cmd_info *cmd);
1107 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1108 			 struct mlx4_vhcr *vhcr,
1109 			 struct mlx4_cmd_mailbox *inbox,
1110 			 struct mlx4_cmd_mailbox *outbox,
1111 			 struct mlx4_cmd_info *cmd);
1112 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1113 			struct mlx4_vhcr *vhcr,
1114 			struct mlx4_cmd_mailbox *inbox,
1115 			struct mlx4_cmd_mailbox *outbox,
1116 			struct mlx4_cmd_info *cmd);
1117 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1118 			     struct mlx4_vhcr *vhcr,
1119 			     struct mlx4_cmd_mailbox *inbox,
1120 			     struct mlx4_cmd_mailbox *outbox,
1121 			     struct mlx4_cmd_info *cmd);
1122 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1123 			      struct mlx4_vhcr *vhcr,
1124 			      struct mlx4_cmd_mailbox *inbox,
1125 			      struct mlx4_cmd_mailbox *outbox,
1126 			      struct mlx4_cmd_info *cmd);
1127 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1128 			     struct mlx4_vhcr *vhcr,
1129 			     struct mlx4_cmd_mailbox *inbox,
1130 			     struct mlx4_cmd_mailbox *outbox,
1131 			     struct mlx4_cmd_info *cmd);
1132 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1133 			    struct mlx4_vhcr *vhcr,
1134 			    struct mlx4_cmd_mailbox *inbox,
1135 			    struct mlx4_cmd_mailbox *outbox,
1136 			    struct mlx4_cmd_info *cmd);
1137 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1138 			    struct mlx4_vhcr *vhcr,
1139 			    struct mlx4_cmd_mailbox *inbox,
1140 			    struct mlx4_cmd_mailbox *outbox,
1141 			    struct mlx4_cmd_info *cmd);
1142 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1143 			      struct mlx4_vhcr *vhcr,
1144 			      struct mlx4_cmd_mailbox *inbox,
1145 			      struct mlx4_cmd_mailbox *outbox,
1146 			      struct mlx4_cmd_info *cmd);
1147 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1148 			 struct mlx4_vhcr *vhcr,
1149 			 struct mlx4_cmd_mailbox *inbox,
1150 			 struct mlx4_cmd_mailbox *outbox,
1151 			 struct mlx4_cmd_info *cmd);
1152 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1153 			    struct mlx4_vhcr *vhcr,
1154 			    struct mlx4_cmd_mailbox *inbox,
1155 			    struct mlx4_cmd_mailbox *outbox,
1156 			    struct mlx4_cmd_info *cmd);
1157 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1158 			    struct mlx4_vhcr *vhcr,
1159 			    struct mlx4_cmd_mailbox *inbox,
1160 			    struct mlx4_cmd_mailbox *outbox,
1161 			    struct mlx4_cmd_info *cmd);
1162 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1163 			    struct mlx4_vhcr *vhcr,
1164 			    struct mlx4_cmd_mailbox *inbox,
1165 			    struct mlx4_cmd_mailbox *outbox,
1166 			    struct mlx4_cmd_info *cmd);
1167 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1168 			 struct mlx4_vhcr *vhcr,
1169 			 struct mlx4_cmd_mailbox *inbox,
1170 			 struct mlx4_cmd_mailbox *outbox,
1171 			 struct mlx4_cmd_info *cmd);
1172 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1173 			  struct mlx4_vhcr *vhcr,
1174 			  struct mlx4_cmd_mailbox *inbox,
1175 			  struct mlx4_cmd_mailbox *outbox,
1176 			  struct mlx4_cmd_info *cmd);
1177 
1178 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1179 
1180 enum {
1181 	MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1182 	MLX4_CMD_CLEANUP_POOL	= 1UL << 1,
1183 	MLX4_CMD_CLEANUP_HCR	= 1UL << 2,
1184 	MLX4_CMD_CLEANUP_VHCR	= 1UL << 3,
1185 	MLX4_CMD_CLEANUP_ALL	= (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1186 };
1187 
1188 int mlx4_cmd_init(struct mlx4_dev *dev);
1189 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1190 int mlx4_multi_func_init(struct mlx4_dev *dev);
1191 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1192 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1193 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1194 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1195 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1196 
1197 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1198 		  u16 op, unsigned long timeout);
1199 
1200 void mlx4_cq_tasklet_cb(unsigned long data);
1201 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1202 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1203 
1204 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1205 
1206 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1207 
1208 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1209 
1210 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1211 		    enum mlx4_port_type *type);
1212 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1213 			 enum mlx4_port_type *stype,
1214 			 enum mlx4_port_type *defaults);
1215 void mlx4_start_sense(struct mlx4_dev *dev);
1216 void mlx4_stop_sense(struct mlx4_dev *dev);
1217 void mlx4_sense_init(struct mlx4_dev *dev);
1218 int mlx4_check_port_params(struct mlx4_dev *dev,
1219 			   enum mlx4_port_type *port_type);
1220 int mlx4_change_port_types(struct mlx4_dev *dev,
1221 			   enum mlx4_port_type *port_types);
1222 
1223 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1224 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1225 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1226 			      struct mlx4_roce_gid_table *table);
1227 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1228 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1229 int mlx4_bond_vlan_table(struct mlx4_dev *dev);
1230 int mlx4_unbond_vlan_table(struct mlx4_dev *dev);
1231 int mlx4_bond_mac_table(struct mlx4_dev *dev);
1232 int mlx4_unbond_mac_table(struct mlx4_dev *dev);
1233 
1234 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1235 /* resource tracker functions*/
1236 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1237 				    enum mlx4_resource resource_type,
1238 				    u64 resource_id, int *slave);
1239 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1240 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1241 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1242 
1243 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1244 				enum mlx4_res_tracker_free_type type);
1245 
1246 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1247 			  struct mlx4_vhcr *vhcr,
1248 			  struct mlx4_cmd_mailbox *inbox,
1249 			  struct mlx4_cmd_mailbox *outbox,
1250 			  struct mlx4_cmd_info *cmd);
1251 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1252 			  struct mlx4_vhcr *vhcr,
1253 			  struct mlx4_cmd_mailbox *inbox,
1254 			  struct mlx4_cmd_mailbox *outbox,
1255 			  struct mlx4_cmd_info *cmd);
1256 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1257 			   struct mlx4_vhcr *vhcr,
1258 			   struct mlx4_cmd_mailbox *inbox,
1259 			   struct mlx4_cmd_mailbox *outbox,
1260 			   struct mlx4_cmd_info *cmd);
1261 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1262 			    struct mlx4_vhcr *vhcr,
1263 			    struct mlx4_cmd_mailbox *inbox,
1264 			    struct mlx4_cmd_mailbox *outbox,
1265 			    struct mlx4_cmd_info *cmd);
1266 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1267 			       struct mlx4_vhcr *vhcr,
1268 			       struct mlx4_cmd_mailbox *inbox,
1269 			       struct mlx4_cmd_mailbox *outbox,
1270 			       struct mlx4_cmd_info *cmd);
1271 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1272 			    struct mlx4_vhcr *vhcr,
1273 			    struct mlx4_cmd_mailbox *inbox,
1274 			    struct mlx4_cmd_mailbox *outbox,
1275 			    struct mlx4_cmd_info *cmd);
1276 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1277 
1278 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1279 				    int *gid_tbl_len, int *pkey_tbl_len);
1280 
1281 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1282 			   struct mlx4_vhcr *vhcr,
1283 			   struct mlx4_cmd_mailbox *inbox,
1284 			   struct mlx4_cmd_mailbox *outbox,
1285 			   struct mlx4_cmd_info *cmd);
1286 
1287 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1288 			   struct mlx4_vhcr *vhcr,
1289 			   struct mlx4_cmd_mailbox *inbox,
1290 			   struct mlx4_cmd_mailbox *outbox,
1291 			   struct mlx4_cmd_info *cmd);
1292 
1293 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1294 			 struct mlx4_vhcr *vhcr,
1295 			 struct mlx4_cmd_mailbox *inbox,
1296 			 struct mlx4_cmd_mailbox *outbox,
1297 			 struct mlx4_cmd_info *cmd);
1298 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1299 			  enum mlx4_protocol prot, enum mlx4_steer_type steer);
1300 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1301 			  int block_mcast_loopback, enum mlx4_protocol prot,
1302 			  enum mlx4_steer_type steer);
1303 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1304 			      u8 gid[16], u8 port,
1305 			      int block_mcast_loopback,
1306 			      enum mlx4_protocol prot, u64 *reg_id);
1307 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1308 				struct mlx4_vhcr *vhcr,
1309 				struct mlx4_cmd_mailbox *inbox,
1310 				struct mlx4_cmd_mailbox *outbox,
1311 				struct mlx4_cmd_info *cmd);
1312 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1313 			       struct mlx4_vhcr *vhcr,
1314 			       struct mlx4_cmd_mailbox *inbox,
1315 			       struct mlx4_cmd_mailbox *outbox,
1316 			       struct mlx4_cmd_info *cmd);
1317 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1318 				     int port, void *buf);
1319 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1320 				   struct mlx4_vhcr *vhcr,
1321 				   struct mlx4_cmd_mailbox *inbox,
1322 				   struct mlx4_cmd_mailbox *outbox,
1323 				struct mlx4_cmd_info *cmd);
1324 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1325 			    struct mlx4_vhcr *vhcr,
1326 			    struct mlx4_cmd_mailbox *inbox,
1327 			    struct mlx4_cmd_mailbox *outbox,
1328 			    struct mlx4_cmd_info *cmd);
1329 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1330 			       struct mlx4_vhcr *vhcr,
1331 			       struct mlx4_cmd_mailbox *inbox,
1332 			       struct mlx4_cmd_mailbox *outbox,
1333 			       struct mlx4_cmd_info *cmd);
1334 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1335 					 struct mlx4_vhcr *vhcr,
1336 					 struct mlx4_cmd_mailbox *inbox,
1337 					 struct mlx4_cmd_mailbox *outbox,
1338 					 struct mlx4_cmd_info *cmd);
1339 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1340 					 struct mlx4_vhcr *vhcr,
1341 					 struct mlx4_cmd_mailbox *inbox,
1342 					 struct mlx4_cmd_mailbox *outbox,
1343 					 struct mlx4_cmd_info *cmd);
1344 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1345 			    struct mlx4_vhcr *vhcr,
1346 			    struct mlx4_cmd_mailbox *inbox,
1347 			    struct mlx4_cmd_mailbox *outbox,
1348 			    struct mlx4_cmd_info *cmd);
1349 
1350 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1351 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1352 
1353 static inline void set_param_l(u64 *arg, u32 val)
1354 {
1355 	*arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1356 }
1357 
1358 static inline void set_param_h(u64 *arg, u32 val)
1359 {
1360 	*arg = (*arg & 0xffffffff) | ((u64) val << 32);
1361 }
1362 
1363 static inline u32 get_param_l(u64 *arg)
1364 {
1365 	return (u32) (*arg & 0xffffffff);
1366 }
1367 
1368 static inline u32 get_param_h(u64 *arg)
1369 {
1370 	return (u32)(*arg >> 32);
1371 }
1372 
1373 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1374 {
1375 	return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1376 }
1377 
1378 #define NOT_MASKED_PD_BITS 17
1379 
1380 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1381 
1382 void mlx4_init_quotas(struct mlx4_dev *dev);
1383 
1384 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */
1385 void mlx4_replace_zero_macs(struct mlx4_dev *dev);
1386 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1387 /* Returns the VF index of slave */
1388 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1389 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1390 int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1391 int mlx4_bond_fs_rules(struct mlx4_dev *dev);
1392 int mlx4_unbond_fs_rules(struct mlx4_dev *dev);
1393 
1394 enum mlx4_zone_flags {
1395 	MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO	= 1UL << 0,
1396 	MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO	= 1UL << 1,
1397 	MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO	= 1UL << 2,
1398 	MLX4_ZONE_USE_RR			= 1UL << 3,
1399 };
1400 
1401 enum mlx4_zone_alloc_flags {
1402 	/* No two objects could overlap between zones. UID
1403 	 * could be left unused. If this flag is given and
1404 	 * two overlapped zones are used, an object will be free'd
1405 	 * from the smallest possible matching zone.
1406 	 */
1407 	MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP	= 1UL << 0,
1408 };
1409 
1410 struct mlx4_zone_allocator;
1411 
1412 /* Create a new zone allocator */
1413 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1414 
1415 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1416  * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1417  * Similarly, when searching for an object to free, this offset it taken into
1418  * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1419  * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1420  * When an allocation fails, <zone_alloc> tries to allocate from other zones
1421  * according to the policy set by <flags>. <puid> is the unique identifier
1422  * received to this zone.
1423  */
1424 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1425 		      struct mlx4_bitmap *bitmap,
1426 		      u32 flags,
1427 		      int priority,
1428 		      int offset,
1429 		      u32 *puid);
1430 
1431 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1432 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1433 
1434 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1435  * the attached bitmaps.
1436  */
1437 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1438 
1439 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1440  * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1441  * allocated from is returned in <puid>. If the allocation fails, a negative
1442  * number is returned. Otherwise, the offset of the first object is returned.
1443  */
1444 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1445 			    int align, u32 skip_mask, u32 *puid);
1446 
1447 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1448  * <zones>.
1449  */
1450 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1451 			   u32 uid, u32 obj, u32 count);
1452 
1453 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1454  * specifying the uid when freeing an object, zone allocator could figure it by
1455  * itself. Other parameters are similar to mlx4_zone_free.
1456  */
1457 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1458 
1459 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1460 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1461 
1462 #endif /* MLX4_H */
1463