1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/device.h> 47 #include <linux/rwsem.h> 48 #include <dev/mlx4/device.h> 49 #include <dev/mlx4/driver.h> 50 #include <dev/mlx4/doorbell.h> 51 #include <dev/mlx4/cmd.h> 52 #include <dev/mlx4/mlx4_core/fw_qos.h> 53 54 #define DRV_NAME "mlx4_core" 55 #define PFX DRV_NAME ": " 56 #ifndef DRV_VERSION 57 #define DRV_VERSION "3.7.0" 58 #endif 59 #define DRV_RELDATE "July 2021" 60 61 #define MLX4_FS_UDP_UC_EN (1 << 1) 62 #define MLX4_FS_TCP_UC_EN (1 << 2) 63 #define MLX4_FS_NUM_OF_L2_ADDR 8 64 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 65 #define MLX4_FS_NUM_MCG (1 << 17) 66 67 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 68 69 #define MLX4_QUERY_IF_STAT_RESET BIT(31) 70 71 enum { 72 MLX4_HCR_BASE = 0x80680, 73 MLX4_HCR_SIZE = 0x0001c, 74 MLX4_CLR_INT_SIZE = 0x00008, 75 MLX4_SLAVE_COMM_BASE = 0x0, 76 MLX4_COMM_PAGESIZE = 0x1000, 77 MLX4_CLOCK_SIZE = 0x00008, 78 MLX4_COMM_CHAN_CAPS = 0x8, 79 MLX4_COMM_CHAN_FLAGS = 0xc 80 }; 81 82 enum { 83 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 84 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 85 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 86 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 87 MLX4_MTT_ENTRY_PER_SEG = 8, 88 }; 89 90 enum { 91 MLX4_NUM_PDS = 1 << 15 92 }; 93 94 enum { 95 MLX4_CMPT_TYPE_QP = 0, 96 MLX4_CMPT_TYPE_SRQ = 1, 97 MLX4_CMPT_TYPE_CQ = 2, 98 MLX4_CMPT_TYPE_EQ = 3, 99 MLX4_CMPT_NUM_TYPE 100 }; 101 102 enum { 103 MLX4_CMPT_SHIFT = 24, 104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 105 }; 106 107 enum mlx4_mpt_state { 108 MLX4_MPT_DISABLED = 0, 109 MLX4_MPT_EN_HW, 110 MLX4_MPT_EN_SW 111 }; 112 113 #define MLX4_COMM_TIME 10000 114 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 115 #define MLX4_COMM_CMD_NA_OP 0x0 116 117 118 enum { 119 MLX4_COMM_CMD_RESET, 120 MLX4_COMM_CMD_VHCR0, 121 MLX4_COMM_CMD_VHCR1, 122 MLX4_COMM_CMD_VHCR2, 123 MLX4_COMM_CMD_VHCR_EN, 124 MLX4_COMM_CMD_VHCR_POST, 125 MLX4_COMM_CMD_FLR = 254 126 }; 127 128 enum { 129 MLX4_VF_SMI_DISABLED, 130 MLX4_VF_SMI_ENABLED 131 }; 132 133 /*The flag indicates that the slave should delay the RESET cmd*/ 134 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 135 /*indicates how many retries will be done if we are in the middle of FLR*/ 136 #define NUM_OF_RESET_RETRIES 10 137 #define SLEEP_TIME_IN_RESET (2 * 1000) 138 enum mlx4_resource { 139 RES_QP, 140 RES_CQ, 141 RES_SRQ, 142 RES_XRCD, 143 RES_MPT, 144 RES_MTT, 145 RES_MAC, 146 RES_VLAN, 147 RES_NPORT_ID, 148 RES_COUNTER, 149 RES_FS_RULE, 150 RES_EQ, 151 MLX4_NUM_OF_RESOURCE_TYPE 152 }; 153 154 enum mlx4_alloc_mode { 155 RES_OP_RESERVE, 156 RES_OP_RESERVE_AND_MAP, 157 RES_OP_MAP_ICM, 158 }; 159 160 enum mlx4_res_tracker_free_type { 161 RES_TR_FREE_ALL, 162 RES_TR_FREE_SLAVES_ONLY, 163 RES_TR_FREE_STRUCTS_ONLY, 164 }; 165 166 /* 167 *Virtual HCR structures. 168 * mlx4_vhcr is the sw representation, in machine endianness 169 * 170 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 171 * to FW to go through communication channel. 172 * It is big endian, and has the same structure as the physical HCR 173 * used by command interface 174 */ 175 struct mlx4_vhcr { 176 u64 in_param; 177 u64 out_param; 178 u32 in_modifier; 179 u32 errno; 180 u16 op; 181 u16 token; 182 u8 op_modifier; 183 u8 e_bit; 184 }; 185 186 struct mlx4_vhcr_cmd { 187 __be64 in_param; 188 __be32 in_modifier; 189 u32 reserved1; 190 __be64 out_param; 191 __be16 token; 192 u16 reserved; 193 u8 status; 194 u8 flags; 195 __be16 opcode; 196 }; 197 198 struct mlx4_cmd_info { 199 u16 opcode; 200 bool has_inbox; 201 bool has_outbox; 202 bool out_is_imm; 203 bool encode_slave_id; 204 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 205 struct mlx4_cmd_mailbox *inbox); 206 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 207 struct mlx4_cmd_mailbox *inbox, 208 struct mlx4_cmd_mailbox *outbox, 209 struct mlx4_cmd_info *cmd); 210 }; 211 212 #ifdef CONFIG_MLX4_DEBUG 213 extern int mlx4_debug_level; 214 #else /* CONFIG_MLX4_DEBUG */ 215 #define mlx4_debug_level (0) 216 #endif /* CONFIG_MLX4_DEBUG */ 217 218 #define mlx4_dbg(mdev, format, ...) \ 219 do { \ 220 if (mlx4_debug_level) \ 221 dev_printk(KERN_DEBUG, \ 222 &(mdev)->persist->pdev->dev, format, \ 223 ##__VA_ARGS__); \ 224 } while (0) 225 226 #define mlx4_err(mdev, format, ...) \ 227 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 228 #define mlx4_info(mdev, format, ...) \ 229 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 230 #define mlx4_warn(mdev, format, ...) \ 231 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 232 233 extern int mlx4_log_num_mgm_entry_size; 234 extern int log_mtts_per_seg; 235 extern int mlx4_internal_err_reset; 236 237 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 238 MLX4_MFUNC_MAX)) 239 #define ALL_SLAVES 0xff 240 241 struct mlx4_bitmap { 242 u32 last; 243 u32 top; 244 u32 max; 245 u32 reserved_top; 246 u32 mask; 247 u32 avail; 248 u32 effective_len; 249 spinlock_t lock; 250 unsigned long *table; 251 }; 252 253 struct mlx4_buddy { 254 unsigned long **bits; 255 unsigned int *num_free; 256 u32 max_order; 257 spinlock_t lock; 258 }; 259 260 struct mlx4_icm; 261 262 struct mlx4_icm_table { 263 u64 virt; 264 int num_icm; 265 u32 num_obj; 266 int obj_size; 267 int lowmem; 268 int coherent; 269 struct mutex mutex; 270 struct mlx4_icm **icm; 271 }; 272 273 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 274 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 275 #define MLX4_MPT_FLAG_MIO (1 << 17) 276 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 277 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 278 #define MLX4_MPT_FLAG_REGION (1 << 8) 279 280 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 281 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 282 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 283 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 284 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 285 286 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 287 288 #define MLX4_MPT_STATUS_SW 0xF0 289 #define MLX4_MPT_STATUS_HW 0x00 290 291 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 292 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 293 294 #define MLX4_EQ_ASYNC 0 295 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \ 296 !!((int)(vector) >= MLX4_EQ_ASYNC)) 297 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \ 298 !!((int)(vector) >= MLX4_EQ_ASYNC)) 299 300 /* 301 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 302 */ 303 struct mlx4_mpt_entry { 304 __be32 flags; 305 __be32 qpn; 306 __be32 key; 307 __be32 pd_flags; 308 __be64 start; 309 __be64 length; 310 __be32 lkey; 311 __be32 win_cnt; 312 u8 reserved1[3]; 313 u8 mtt_rep; 314 __be64 mtt_addr; 315 __be32 mtt_sz; 316 __be32 entity_size; 317 __be32 first_byte_offset; 318 } __packed; 319 320 /* 321 * Must be packed because start is 64 bits but only aligned to 32 bits. 322 */ 323 struct mlx4_eq_context { 324 __be32 flags; 325 u16 reserved1[3]; 326 __be16 page_offset; 327 u8 log_eq_size; 328 u8 reserved2[4]; 329 u8 eq_period; 330 u8 reserved3; 331 u8 eq_max_count; 332 u8 reserved4[3]; 333 u8 intr; 334 u8 log_page_size; 335 u8 reserved5[2]; 336 u8 mtt_base_addr_h; 337 __be32 mtt_base_addr_l; 338 u32 reserved6[2]; 339 __be32 consumer_index; 340 __be32 producer_index; 341 u32 reserved7[4]; 342 }; 343 344 struct mlx4_cq_context { 345 __be32 flags; 346 u16 reserved1[3]; 347 __be16 page_offset; 348 __be32 logsize_usrpage; 349 __be16 cq_period; 350 __be16 cq_max_count; 351 u8 reserved2[3]; 352 u8 comp_eqn; 353 u8 log_page_size; 354 u8 reserved3[2]; 355 u8 mtt_base_addr_h; 356 __be32 mtt_base_addr_l; 357 __be32 last_notified_index; 358 __be32 solicit_producer_index; 359 __be32 consumer_index; 360 __be32 producer_index; 361 u32 reserved4[2]; 362 __be64 db_rec_addr; 363 }; 364 365 struct mlx4_srq_context { 366 __be32 state_logsize_srqn; 367 u8 logstride; 368 u8 reserved1; 369 __be16 xrcd; 370 __be32 pg_offset_cqn; 371 u32 reserved2; 372 u8 log_page_size; 373 u8 reserved3[2]; 374 u8 mtt_base_addr_h; 375 __be32 mtt_base_addr_l; 376 __be32 pd; 377 __be16 limit_watermark; 378 __be16 wqe_cnt; 379 u16 reserved4; 380 __be16 wqe_counter; 381 u32 reserved5; 382 __be64 db_rec_addr; 383 }; 384 385 struct mlx4_eq { 386 struct mlx4_dev *dev; 387 void __iomem *doorbell; 388 int eqn; 389 u32 cons_index; 390 u16 irq; 391 u16 have_irq; 392 int nent; 393 struct mlx4_buf_list *page_list; 394 struct mlx4_mtt mtt; 395 u32 ncqs; 396 struct mlx4_active_ports actv_ports; 397 u32 ref_count; 398 int affinity_cpu_id; 399 }; 400 401 struct mlx4_slave_eqe { 402 u8 type; 403 u8 port; 404 u32 param; 405 }; 406 407 struct mlx4_slave_event_eq_info { 408 int eqn; 409 u16 token; 410 }; 411 412 struct mlx4_profile { 413 int num_qp; 414 int rdmarc_per_qp; 415 int num_srq; 416 int num_cq; 417 int num_mcg; 418 int num_mpt; 419 unsigned num_mtt; 420 }; 421 422 struct mlx4_fw { 423 u64 clr_int_base; 424 u64 catas_offset; 425 u64 comm_base; 426 u64 clock_offset; 427 struct mlx4_icm *fw_icm; 428 struct mlx4_icm *aux_icm; 429 u32 catas_size; 430 u16 fw_pages; 431 u8 clr_int_bar; 432 u8 catas_bar; 433 u8 comm_bar; 434 u8 clock_bar; 435 }; 436 437 struct mlx4_comm { 438 u32 slave_write; 439 u32 slave_read; 440 }; 441 442 enum { 443 MLX4_MCAST_CONFIG = 0, 444 MLX4_MCAST_DISABLE = 1, 445 MLX4_MCAST_ENABLE = 2, 446 }; 447 448 #define VLAN_FLTR_SIZE 128 449 450 struct mlx4_vlan_fltr { 451 __be32 entry[VLAN_FLTR_SIZE]; 452 }; 453 454 struct mlx4_mcast_entry { 455 struct list_head list; 456 u64 addr; 457 }; 458 459 struct mlx4_promisc_qp { 460 struct list_head list; 461 u32 qpn; 462 }; 463 464 struct mlx4_steer_index { 465 struct list_head list; 466 unsigned int index; 467 struct list_head duplicates; 468 }; 469 470 #define MLX4_EVENT_TYPES_NUM 64 471 472 struct mlx4_slave_state { 473 u8 comm_toggle; 474 u8 last_cmd; 475 u8 init_port_mask; 476 bool active; 477 bool old_vlan_api; 478 bool vst_qinq_supported; 479 u8 function; 480 dma_addr_t vhcr_dma; 481 u16 mtu[MLX4_MAX_PORTS + 1]; 482 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 483 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 484 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 485 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 486 /* event type to eq number lookup */ 487 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 488 u16 eq_pi; 489 u16 eq_ci; 490 spinlock_t lock; 491 /*initialized via the kzalloc*/ 492 u8 is_slave_going_down; 493 u32 cookie; 494 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 495 }; 496 497 #define MLX4_VGT 4095 498 #define NO_INDX (-1) 499 500 struct mlx4_vport_state { 501 u64 mac; 502 u16 default_vlan; 503 u8 default_qos; 504 __be16 vlan_proto; 505 u32 tx_rate; 506 bool spoofchk; 507 u8 qos_vport; 508 __be64 guid; 509 }; 510 511 struct mlx4_vf_admin_state { 512 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 513 u8 enable_smi[MLX4_MAX_PORTS + 1]; 514 }; 515 516 struct mlx4_vport_oper_state { 517 struct mlx4_vport_state state; 518 int mac_idx; 519 int vlan_idx; 520 }; 521 522 struct mlx4_vf_oper_state { 523 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 524 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 525 }; 526 527 struct slave_list { 528 struct mutex mutex; 529 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 530 }; 531 532 struct resource_allocator { 533 spinlock_t alloc_lock; /* protect quotas */ 534 union { 535 int res_reserved; 536 int res_port_rsvd[MLX4_MAX_PORTS]; 537 }; 538 union { 539 int res_free; 540 int res_port_free[MLX4_MAX_PORTS]; 541 }; 542 int *quota; 543 int *allocated; 544 int *guaranteed; 545 }; 546 547 struct mlx4_resource_tracker { 548 spinlock_t lock; 549 /* tree for each resources */ 550 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 551 /* num_of_slave's lists, one per slave */ 552 struct slave_list *slave_list; 553 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 554 }; 555 556 #define SLAVE_EVENT_EQ_SIZE 128 557 struct mlx4_slave_event_eq { 558 u32 eqn; 559 u32 cons; 560 u32 prod; 561 spinlock_t event_lock; 562 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 563 }; 564 565 struct mlx4_qos_manager { 566 int num_of_qos_vfs; 567 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); 568 }; 569 570 struct mlx4_master_qp0_state { 571 int proxy_qp0_active; 572 int qp0_active; 573 int port_active; 574 }; 575 576 struct mlx4_mfunc_master_ctx { 577 struct mlx4_slave_state *slave_state; 578 struct mlx4_vf_admin_state *vf_admin; 579 struct mlx4_vf_oper_state *vf_oper; 580 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 581 int init_port_ref[MLX4_MAX_PORTS + 1]; 582 u16 max_mtu[MLX4_MAX_PORTS + 1]; 583 u8 pptx; 584 u8 pprx; 585 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 586 struct mlx4_resource_tracker res_tracker; 587 struct workqueue_struct *comm_wq; 588 struct work_struct comm_work; 589 struct work_struct slave_event_work; 590 struct work_struct slave_flr_event_work; 591 spinlock_t slave_state_lock; 592 __be32 comm_arm_bit_vector[4]; 593 struct mlx4_eqe cmd_eqe; 594 struct mlx4_slave_event_eq slave_eq; 595 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 596 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; 597 }; 598 599 struct mlx4_mfunc { 600 struct mlx4_comm __iomem *comm; 601 struct mlx4_vhcr_cmd *vhcr; 602 dma_addr_t vhcr_dma; 603 604 struct mlx4_mfunc_master_ctx master; 605 }; 606 607 #define MGM_QPN_MASK 0x00FFFFFF 608 #define MGM_BLCK_LB_BIT 30 609 610 struct mlx4_mgm { 611 __be32 next_gid_index; 612 __be32 members_count; 613 u32 reserved[2]; 614 u8 gid[16]; 615 __be32 qp[MLX4_MAX_QP_PER_MGM]; 616 }; 617 618 struct mlx4_cmd { 619 struct pci_pool *pool; 620 void __iomem *hcr; 621 struct mutex slave_cmd_mutex; 622 struct semaphore poll_sem; 623 struct semaphore event_sem; 624 struct rw_semaphore switch_sem; 625 int max_cmds; 626 spinlock_t context_lock; 627 int free_head; 628 struct mlx4_cmd_context *context; 629 u16 token_mask; 630 u8 use_events; 631 u8 toggle; 632 u8 comm_toggle; 633 u8 initialized; 634 }; 635 636 enum { 637 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 638 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 639 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 640 }; 641 struct mlx4_vf_immed_vlan_work { 642 struct work_struct work; 643 struct mlx4_priv *priv; 644 int flags; 645 int slave; 646 int vlan_ix; 647 int orig_vlan_ix; 648 u8 port; 649 u8 qos; 650 u8 qos_vport; 651 u16 vlan_id; 652 u16 orig_vlan_id; 653 __be16 vlan_proto; 654 }; 655 656 657 struct mlx4_uar_table { 658 struct mlx4_bitmap bitmap; 659 }; 660 661 struct mlx4_mr_table { 662 struct mlx4_bitmap mpt_bitmap; 663 struct mlx4_buddy mtt_buddy; 664 u64 mtt_base; 665 u64 mpt_base; 666 struct mlx4_icm_table mtt_table; 667 struct mlx4_icm_table dmpt_table; 668 }; 669 670 struct mlx4_cq_table { 671 struct mlx4_bitmap bitmap; 672 spinlock_t lock; 673 struct radix_tree_root tree; 674 struct mlx4_icm_table table; 675 struct mlx4_icm_table cmpt_table; 676 }; 677 678 struct mlx4_eq_table { 679 struct mlx4_bitmap bitmap; 680 char *irq_names; 681 void __iomem *clr_int; 682 void __iomem **uar_map; 683 u32 clr_mask; 684 struct mlx4_eq *eq; 685 struct mlx4_icm_table table; 686 struct mlx4_icm_table cmpt_table; 687 int have_irq; 688 u8 inta_pin; 689 }; 690 691 struct mlx4_srq_table { 692 struct mlx4_bitmap bitmap; 693 spinlock_t lock; 694 struct radix_tree_root tree; 695 struct mlx4_icm_table table; 696 struct mlx4_icm_table cmpt_table; 697 }; 698 699 enum mlx4_qp_table_zones { 700 MLX4_QP_TABLE_ZONE_GENERAL, 701 MLX4_QP_TABLE_ZONE_RSS, 702 MLX4_QP_TABLE_ZONE_RAW_ETH, 703 MLX4_QP_TABLE_ZONE_NUM 704 }; 705 706 struct mlx4_qp_table { 707 struct mlx4_bitmap *bitmap_gen; 708 struct mlx4_zone_allocator *zones; 709 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 710 u32 rdmarc_base; 711 int rdmarc_shift; 712 spinlock_t lock; 713 struct mlx4_icm_table qp_table; 714 struct mlx4_icm_table auxc_table; 715 struct mlx4_icm_table altc_table; 716 struct mlx4_icm_table rdmarc_table; 717 struct mlx4_icm_table cmpt_table; 718 }; 719 720 struct mlx4_mcg_table { 721 struct mutex mutex; 722 struct mlx4_bitmap bitmap; 723 struct mlx4_icm_table table; 724 }; 725 726 struct mlx4_catas_err { 727 u32 __iomem *map; 728 struct timer_list timer; 729 struct list_head list; 730 }; 731 732 #define MLX4_MAX_MAC_NUM 128 733 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 734 735 struct mlx4_mac_table { 736 __be64 entries[MLX4_MAX_MAC_NUM]; 737 int refs[MLX4_MAX_MAC_NUM]; 738 bool is_dup[MLX4_MAX_MAC_NUM]; 739 struct mutex mutex; 740 int total; 741 int max; 742 }; 743 744 #define MLX4_ROCE_GID_ENTRY_SIZE 16 745 746 struct mlx4_roce_gid_entry { 747 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 748 }; 749 750 struct mlx4_roce_gid_table { 751 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 752 struct mutex mutex; 753 }; 754 755 #define MLX4_MAX_VLAN_NUM 128 756 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 757 758 struct mlx4_vlan_table { 759 __be32 entries[MLX4_MAX_VLAN_NUM]; 760 int refs[MLX4_MAX_VLAN_NUM]; 761 int is_dup[MLX4_MAX_VLAN_NUM]; 762 struct mutex mutex; 763 int total; 764 int max; 765 }; 766 767 #define SET_PORT_GEN_ALL_VALID 0x7 768 #define SET_PORT_PROMISC_SHIFT 31 769 #define SET_PORT_MC_PROMISC_SHIFT 30 770 771 enum { 772 MCAST_DIRECT_ONLY = 0, 773 MCAST_DIRECT = 1, 774 MCAST_DEFAULT = 2 775 }; 776 777 struct mlx4_set_port_general_context { 778 u16 reserved1; 779 u8 v_ignore_fcs; 780 u8 flags; 781 union { 782 u8 ignore_fcs; 783 u8 roce_mode; 784 }; 785 u8 reserved2; 786 __be16 mtu; 787 u8 pptx; 788 u8 pfctx; 789 u16 reserved3; 790 u8 pprx; 791 u8 pfcrx; 792 u16 reserved4; 793 u32 reserved5; 794 u8 phv_en; 795 u8 reserved6[3]; 796 }; 797 798 struct mlx4_set_port_rqp_calc_context { 799 __be32 base_qpn; 800 u8 rererved; 801 u8 n_mac; 802 u8 n_vlan; 803 u8 n_prio; 804 u8 reserved2[3]; 805 u8 mac_miss; 806 u8 intra_no_vlan; 807 u8 no_vlan; 808 u8 intra_vlan_miss; 809 u8 vlan_miss; 810 u8 reserved3[3]; 811 u8 no_vlan_prio; 812 __be32 promisc; 813 __be32 mcast; 814 }; 815 816 struct mlx4_port_info { 817 struct mlx4_dev *dev; 818 int port; 819 char dev_name[16]; 820 struct device_attribute port_attr; 821 enum mlx4_port_type tmp_type; 822 char dev_mtu_name[16]; 823 struct device_attribute port_mtu_attr; 824 struct mlx4_mac_table mac_table; 825 struct mlx4_vlan_table vlan_table; 826 struct mlx4_roce_gid_table gid_table; 827 int base_qpn; 828 }; 829 830 struct mlx4_sense { 831 struct mlx4_dev *dev; 832 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 833 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 834 struct delayed_work sense_poll; 835 int gone; 836 }; 837 838 struct mlx4_msix_ctl { 839 DECLARE_BITMAP(pool_bm, MAX_MSIX); 840 struct mutex pool_lock; 841 }; 842 843 struct mlx4_steer { 844 struct list_head promisc_qps[MLX4_NUM_STEERS]; 845 struct list_head steer_entries[MLX4_NUM_STEERS]; 846 }; 847 848 enum { 849 MLX4_PCI_DEV_IS_VF = 1 << 0, 850 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 851 }; 852 853 enum { 854 MLX4_NO_RR = 0, 855 MLX4_USE_RR = 1, 856 }; 857 858 struct mlx4_priv { 859 struct mlx4_dev dev; 860 861 struct list_head dev_list; 862 struct list_head ctx_list; 863 spinlock_t ctx_lock; 864 865 int pci_dev_data; 866 int removed; 867 868 struct list_head pgdir_list; 869 struct mutex pgdir_mutex; 870 871 struct mlx4_fw fw; 872 struct mlx4_cmd cmd; 873 struct mlx4_mfunc mfunc; 874 875 struct mlx4_bitmap pd_bitmap; 876 struct mlx4_bitmap xrcd_bitmap; 877 struct mlx4_uar_table uar_table; 878 struct mlx4_mr_table mr_table; 879 struct mlx4_cq_table cq_table; 880 struct mlx4_eq_table eq_table; 881 struct mlx4_srq_table srq_table; 882 struct mlx4_qp_table qp_table; 883 struct mlx4_mcg_table mcg_table; 884 struct mlx4_bitmap counters_bitmap; 885 int def_counter[MLX4_MAX_PORTS]; 886 887 struct mlx4_catas_err catas_err; 888 889 void __iomem *clr_base; 890 891 struct mlx4_uar driver_uar; 892 void __iomem *kar; 893 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 894 struct mlx4_sense sense; 895 struct mutex port_mutex; 896 struct mlx4_msix_ctl msix_ctl; 897 struct mlx4_steer *steer; 898 struct list_head bf_list; 899 struct mutex bf_mutex; 900 struct io_mapping *bf_mapping; 901 void __iomem *clock_mapping; 902 int reserved_mtts; 903 int fs_hash_mode; 904 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 905 struct mlx4_port_map v2p; /* cached port mapping configuration */ 906 struct mutex bond_mutex; /* for bond mode */ 907 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 908 909 atomic_t opreq_count; 910 struct work_struct opreq_task; 911 }; 912 913 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 914 { 915 return container_of(dev, struct mlx4_priv, dev); 916 } 917 918 #define MLX4_SENSE_RANGE (HZ * 3) 919 920 extern struct workqueue_struct *mlx4_wq; 921 922 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 923 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 924 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 925 int align, u32 skip_mask); 926 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 927 int use_rr); 928 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 929 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 930 u32 reserved_bot, u32 resetrved_top); 931 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 932 933 int mlx4_reset(struct mlx4_dev *dev); 934 935 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 936 void mlx4_free_eq_table(struct mlx4_dev *dev); 937 938 int mlx4_init_pd_table(struct mlx4_dev *dev); 939 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 940 int mlx4_init_uar_table(struct mlx4_dev *dev); 941 int mlx4_init_mr_table(struct mlx4_dev *dev); 942 int mlx4_init_eq_table(struct mlx4_dev *dev); 943 int mlx4_init_cq_table(struct mlx4_dev *dev); 944 int mlx4_init_qp_table(struct mlx4_dev *dev); 945 int mlx4_init_srq_table(struct mlx4_dev *dev); 946 int mlx4_init_mcg_table(struct mlx4_dev *dev); 947 948 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 949 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 950 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 951 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 952 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 953 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 954 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 955 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 956 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 957 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 958 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 959 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 960 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 961 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 962 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 963 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 964 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 965 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 966 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 967 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 968 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 969 970 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 971 struct mlx4_vhcr *vhcr, 972 struct mlx4_cmd_mailbox *inbox, 973 struct mlx4_cmd_mailbox *outbox, 974 struct mlx4_cmd_info *cmd); 975 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 976 struct mlx4_vhcr *vhcr, 977 struct mlx4_cmd_mailbox *inbox, 978 struct mlx4_cmd_mailbox *outbox, 979 struct mlx4_cmd_info *cmd); 980 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 981 struct mlx4_vhcr *vhcr, 982 struct mlx4_cmd_mailbox *inbox, 983 struct mlx4_cmd_mailbox *outbox, 984 struct mlx4_cmd_info *cmd); 985 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 986 struct mlx4_vhcr *vhcr, 987 struct mlx4_cmd_mailbox *inbox, 988 struct mlx4_cmd_mailbox *outbox, 989 struct mlx4_cmd_info *cmd); 990 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 991 struct mlx4_vhcr *vhcr, 992 struct mlx4_cmd_mailbox *inbox, 993 struct mlx4_cmd_mailbox *outbox, 994 struct mlx4_cmd_info *cmd); 995 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 996 struct mlx4_vhcr *vhcr, 997 struct mlx4_cmd_mailbox *inbox, 998 struct mlx4_cmd_mailbox *outbox, 999 struct mlx4_cmd_info *cmd); 1000 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 1001 struct mlx4_vhcr *vhcr, 1002 struct mlx4_cmd_mailbox *inbox, 1003 struct mlx4_cmd_mailbox *outbox, 1004 struct mlx4_cmd_info *cmd); 1005 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 1006 struct mlx4_vhcr *vhcr, 1007 struct mlx4_cmd_mailbox *inbox, 1008 struct mlx4_cmd_mailbox *outbox, 1009 struct mlx4_cmd_info *cmd); 1010 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1011 int *base, u8 flags); 1012 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1013 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1014 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1015 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1016 int start_index, int npages, u64 *page_list); 1017 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1018 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1019 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, 1020 struct mlx4_counter *data); 1021 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1022 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1023 1024 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1025 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1026 int mlx4_catas_init(struct mlx4_dev *dev); 1027 void mlx4_catas_end(struct mlx4_dev *dev); 1028 int mlx4_restart_one(struct pci_dev *pdev); 1029 int mlx4_register_device(struct mlx4_dev *dev); 1030 void mlx4_unregister_device(struct mlx4_dev *dev); 1031 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1032 unsigned long param); 1033 1034 struct mlx4_dev_cap; 1035 struct mlx4_init_hca_param; 1036 1037 u64 mlx4_make_profile(struct mlx4_dev *dev, 1038 struct mlx4_profile *request, 1039 struct mlx4_dev_cap *dev_cap, 1040 struct mlx4_init_hca_param *init_hca); 1041 void mlx4_master_comm_channel(struct work_struct *work); 1042 void mlx4_gen_slave_eqe(struct work_struct *work); 1043 void mlx4_master_handle_slave_flr(struct work_struct *work); 1044 1045 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1046 struct mlx4_vhcr *vhcr, 1047 struct mlx4_cmd_mailbox *inbox, 1048 struct mlx4_cmd_mailbox *outbox, 1049 struct mlx4_cmd_info *cmd); 1050 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1051 struct mlx4_vhcr *vhcr, 1052 struct mlx4_cmd_mailbox *inbox, 1053 struct mlx4_cmd_mailbox *outbox, 1054 struct mlx4_cmd_info *cmd); 1055 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1056 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1057 struct mlx4_cmd_mailbox *outbox, 1058 struct mlx4_cmd_info *cmd); 1059 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1060 struct mlx4_vhcr *vhcr, 1061 struct mlx4_cmd_mailbox *inbox, 1062 struct mlx4_cmd_mailbox *outbox, 1063 struct mlx4_cmd_info *cmd); 1064 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1065 struct mlx4_vhcr *vhcr, 1066 struct mlx4_cmd_mailbox *inbox, 1067 struct mlx4_cmd_mailbox *outbox, 1068 struct mlx4_cmd_info *cmd); 1069 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1070 struct mlx4_vhcr *vhcr, 1071 struct mlx4_cmd_mailbox *inbox, 1072 struct mlx4_cmd_mailbox *outbox, 1073 struct mlx4_cmd_info *cmd); 1074 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1075 struct mlx4_vhcr *vhcr, 1076 struct mlx4_cmd_mailbox *inbox, 1077 struct mlx4_cmd_mailbox *outbox, 1078 struct mlx4_cmd_info *cmd); 1079 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1080 struct mlx4_vhcr *vhcr, 1081 struct mlx4_cmd_mailbox *inbox, 1082 struct mlx4_cmd_mailbox *outbox, 1083 struct mlx4_cmd_info *cmd); 1084 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1085 struct mlx4_vhcr *vhcr, 1086 struct mlx4_cmd_mailbox *inbox, 1087 struct mlx4_cmd_mailbox *outbox, 1088 struct mlx4_cmd_info *cmd); 1089 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1090 struct mlx4_vhcr *vhcr, 1091 struct mlx4_cmd_mailbox *inbox, 1092 struct mlx4_cmd_mailbox *outbox, 1093 struct mlx4_cmd_info *cmd); 1094 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1095 struct mlx4_vhcr *vhcr, 1096 struct mlx4_cmd_mailbox *inbox, 1097 struct mlx4_cmd_mailbox *outbox, 1098 struct mlx4_cmd_info *cmd); 1099 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1100 struct mlx4_vhcr *vhcr, 1101 struct mlx4_cmd_mailbox *inbox, 1102 struct mlx4_cmd_mailbox *outbox, 1103 struct mlx4_cmd_info *cmd); 1104 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1105 struct mlx4_vhcr *vhcr, 1106 struct mlx4_cmd_mailbox *inbox, 1107 struct mlx4_cmd_mailbox *outbox, 1108 struct mlx4_cmd_info *cmd); 1109 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1110 struct mlx4_vhcr *vhcr, 1111 struct mlx4_cmd_mailbox *inbox, 1112 struct mlx4_cmd_mailbox *outbox, 1113 struct mlx4_cmd_info *cmd); 1114 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1115 struct mlx4_vhcr *vhcr, 1116 struct mlx4_cmd_mailbox *inbox, 1117 struct mlx4_cmd_mailbox *outbox, 1118 struct mlx4_cmd_info *cmd); 1119 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1120 struct mlx4_vhcr *vhcr, 1121 struct mlx4_cmd_mailbox *inbox, 1122 struct mlx4_cmd_mailbox *outbox, 1123 struct mlx4_cmd_info *cmd); 1124 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1125 struct mlx4_vhcr *vhcr, 1126 struct mlx4_cmd_mailbox *inbox, 1127 struct mlx4_cmd_mailbox *outbox, 1128 struct mlx4_cmd_info *cmd); 1129 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1130 struct mlx4_vhcr *vhcr, 1131 struct mlx4_cmd_mailbox *inbox, 1132 struct mlx4_cmd_mailbox *outbox, 1133 struct mlx4_cmd_info *cmd); 1134 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1135 struct mlx4_vhcr *vhcr, 1136 struct mlx4_cmd_mailbox *inbox, 1137 struct mlx4_cmd_mailbox *outbox, 1138 struct mlx4_cmd_info *cmd); 1139 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1140 struct mlx4_vhcr *vhcr, 1141 struct mlx4_cmd_mailbox *inbox, 1142 struct mlx4_cmd_mailbox *outbox, 1143 struct mlx4_cmd_info *cmd); 1144 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1145 struct mlx4_vhcr *vhcr, 1146 struct mlx4_cmd_mailbox *inbox, 1147 struct mlx4_cmd_mailbox *outbox, 1148 struct mlx4_cmd_info *cmd); 1149 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1150 struct mlx4_vhcr *vhcr, 1151 struct mlx4_cmd_mailbox *inbox, 1152 struct mlx4_cmd_mailbox *outbox, 1153 struct mlx4_cmd_info *cmd); 1154 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1155 struct mlx4_vhcr *vhcr, 1156 struct mlx4_cmd_mailbox *inbox, 1157 struct mlx4_cmd_mailbox *outbox, 1158 struct mlx4_cmd_info *cmd); 1159 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1160 struct mlx4_vhcr *vhcr, 1161 struct mlx4_cmd_mailbox *inbox, 1162 struct mlx4_cmd_mailbox *outbox, 1163 struct mlx4_cmd_info *cmd); 1164 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1165 struct mlx4_vhcr *vhcr, 1166 struct mlx4_cmd_mailbox *inbox, 1167 struct mlx4_cmd_mailbox *outbox, 1168 struct mlx4_cmd_info *cmd); 1169 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1170 struct mlx4_vhcr *vhcr, 1171 struct mlx4_cmd_mailbox *inbox, 1172 struct mlx4_cmd_mailbox *outbox, 1173 struct mlx4_cmd_info *cmd); 1174 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1175 struct mlx4_vhcr *vhcr, 1176 struct mlx4_cmd_mailbox *inbox, 1177 struct mlx4_cmd_mailbox *outbox, 1178 struct mlx4_cmd_info *cmd); 1179 1180 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1181 1182 enum { 1183 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1184 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1185 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1186 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1187 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1188 }; 1189 1190 int mlx4_cmd_init(struct mlx4_dev *dev); 1191 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1192 int mlx4_multi_func_init(struct mlx4_dev *dev); 1193 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1194 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1195 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1196 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1197 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1198 1199 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1200 u16 op, unsigned long timeout); 1201 1202 void mlx4_cq_tasklet_cb(unsigned long data); 1203 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1204 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1205 1206 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1207 1208 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1209 1210 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1211 1212 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1213 enum mlx4_port_type *type); 1214 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1215 enum mlx4_port_type *stype, 1216 enum mlx4_port_type *defaults); 1217 void mlx4_start_sense(struct mlx4_dev *dev); 1218 void mlx4_stop_sense(struct mlx4_dev *dev); 1219 void mlx4_sense_init(struct mlx4_dev *dev); 1220 int mlx4_check_port_params(struct mlx4_dev *dev, 1221 enum mlx4_port_type *port_type); 1222 int mlx4_change_port_types(struct mlx4_dev *dev, 1223 enum mlx4_port_type *port_types); 1224 1225 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1226 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1227 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1228 struct mlx4_roce_gid_table *table); 1229 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1230 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1231 int mlx4_bond_vlan_table(struct mlx4_dev *dev); 1232 int mlx4_unbond_vlan_table(struct mlx4_dev *dev); 1233 int mlx4_bond_mac_table(struct mlx4_dev *dev); 1234 int mlx4_unbond_mac_table(struct mlx4_dev *dev); 1235 1236 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1237 /* resource tracker functions*/ 1238 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1239 enum mlx4_resource resource_type, 1240 u64 resource_id, int *slave); 1241 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1242 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1243 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1244 1245 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1246 enum mlx4_res_tracker_free_type type); 1247 1248 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1249 struct mlx4_vhcr *vhcr, 1250 struct mlx4_cmd_mailbox *inbox, 1251 struct mlx4_cmd_mailbox *outbox, 1252 struct mlx4_cmd_info *cmd); 1253 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1254 struct mlx4_vhcr *vhcr, 1255 struct mlx4_cmd_mailbox *inbox, 1256 struct mlx4_cmd_mailbox *outbox, 1257 struct mlx4_cmd_info *cmd); 1258 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1259 struct mlx4_vhcr *vhcr, 1260 struct mlx4_cmd_mailbox *inbox, 1261 struct mlx4_cmd_mailbox *outbox, 1262 struct mlx4_cmd_info *cmd); 1263 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1264 struct mlx4_vhcr *vhcr, 1265 struct mlx4_cmd_mailbox *inbox, 1266 struct mlx4_cmd_mailbox *outbox, 1267 struct mlx4_cmd_info *cmd); 1268 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1269 struct mlx4_vhcr *vhcr, 1270 struct mlx4_cmd_mailbox *inbox, 1271 struct mlx4_cmd_mailbox *outbox, 1272 struct mlx4_cmd_info *cmd); 1273 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1274 struct mlx4_vhcr *vhcr, 1275 struct mlx4_cmd_mailbox *inbox, 1276 struct mlx4_cmd_mailbox *outbox, 1277 struct mlx4_cmd_info *cmd); 1278 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1279 1280 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1281 int *gid_tbl_len, int *pkey_tbl_len); 1282 1283 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1284 struct mlx4_vhcr *vhcr, 1285 struct mlx4_cmd_mailbox *inbox, 1286 struct mlx4_cmd_mailbox *outbox, 1287 struct mlx4_cmd_info *cmd); 1288 1289 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1290 struct mlx4_vhcr *vhcr, 1291 struct mlx4_cmd_mailbox *inbox, 1292 struct mlx4_cmd_mailbox *outbox, 1293 struct mlx4_cmd_info *cmd); 1294 1295 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1296 struct mlx4_vhcr *vhcr, 1297 struct mlx4_cmd_mailbox *inbox, 1298 struct mlx4_cmd_mailbox *outbox, 1299 struct mlx4_cmd_info *cmd); 1300 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1301 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1302 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1303 int block_mcast_loopback, enum mlx4_protocol prot, 1304 enum mlx4_steer_type steer); 1305 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1306 u8 gid[16], u8 port, 1307 int block_mcast_loopback, 1308 enum mlx4_protocol prot, u64 *reg_id); 1309 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1310 struct mlx4_vhcr *vhcr, 1311 struct mlx4_cmd_mailbox *inbox, 1312 struct mlx4_cmd_mailbox *outbox, 1313 struct mlx4_cmd_info *cmd); 1314 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1315 struct mlx4_vhcr *vhcr, 1316 struct mlx4_cmd_mailbox *inbox, 1317 struct mlx4_cmd_mailbox *outbox, 1318 struct mlx4_cmd_info *cmd); 1319 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1320 int port, void *buf); 1321 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1322 struct mlx4_vhcr *vhcr, 1323 struct mlx4_cmd_mailbox *inbox, 1324 struct mlx4_cmd_mailbox *outbox, 1325 struct mlx4_cmd_info *cmd); 1326 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1327 struct mlx4_vhcr *vhcr, 1328 struct mlx4_cmd_mailbox *inbox, 1329 struct mlx4_cmd_mailbox *outbox, 1330 struct mlx4_cmd_info *cmd); 1331 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1332 struct mlx4_vhcr *vhcr, 1333 struct mlx4_cmd_mailbox *inbox, 1334 struct mlx4_cmd_mailbox *outbox, 1335 struct mlx4_cmd_info *cmd); 1336 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1337 struct mlx4_vhcr *vhcr, 1338 struct mlx4_cmd_mailbox *inbox, 1339 struct mlx4_cmd_mailbox *outbox, 1340 struct mlx4_cmd_info *cmd); 1341 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1342 struct mlx4_vhcr *vhcr, 1343 struct mlx4_cmd_mailbox *inbox, 1344 struct mlx4_cmd_mailbox *outbox, 1345 struct mlx4_cmd_info *cmd); 1346 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1347 struct mlx4_vhcr *vhcr, 1348 struct mlx4_cmd_mailbox *inbox, 1349 struct mlx4_cmd_mailbox *outbox, 1350 struct mlx4_cmd_info *cmd); 1351 1352 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1353 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1354 1355 static inline void set_param_l(u64 *arg, u32 val) 1356 { 1357 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1358 } 1359 1360 static inline void set_param_h(u64 *arg, u32 val) 1361 { 1362 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1363 } 1364 1365 static inline u32 get_param_l(u64 *arg) 1366 { 1367 return (u32) (*arg & 0xffffffff); 1368 } 1369 1370 static inline u32 get_param_h(u64 *arg) 1371 { 1372 return (u32)(*arg >> 32); 1373 } 1374 1375 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1376 { 1377 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1378 } 1379 1380 #define NOT_MASKED_PD_BITS 17 1381 1382 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1383 1384 void mlx4_init_quotas(struct mlx4_dev *dev); 1385 1386 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */ 1387 void mlx4_replace_zero_macs(struct mlx4_dev *dev); 1388 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1389 /* Returns the VF index of slave */ 1390 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1391 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1392 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1393 int mlx4_bond_fs_rules(struct mlx4_dev *dev); 1394 int mlx4_unbond_fs_rules(struct mlx4_dev *dev); 1395 1396 enum mlx4_zone_flags { 1397 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1398 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1399 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1400 MLX4_ZONE_USE_RR = 1UL << 3, 1401 }; 1402 1403 enum mlx4_zone_alloc_flags { 1404 /* No two objects could overlap between zones. UID 1405 * could be left unused. If this flag is given and 1406 * two overlapped zones are used, an object will be free'd 1407 * from the smallest possible matching zone. 1408 */ 1409 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1410 }; 1411 1412 struct mlx4_zone_allocator; 1413 1414 /* Create a new zone allocator */ 1415 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1416 1417 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1418 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1419 * Similarly, when searching for an object to free, this offset it taken into 1420 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1421 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1422 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1423 * according to the policy set by <flags>. <puid> is the unique identifier 1424 * received to this zone. 1425 */ 1426 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1427 struct mlx4_bitmap *bitmap, 1428 u32 flags, 1429 int priority, 1430 int offset, 1431 u32 *puid); 1432 1433 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1434 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1435 1436 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1437 * the attached bitmaps. 1438 */ 1439 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1440 1441 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1442 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1443 * allocated from is returned in <puid>. If the allocation fails, a negative 1444 * number is returned. Otherwise, the offset of the first object is returned. 1445 */ 1446 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1447 int align, u32 skip_mask, u32 *puid); 1448 1449 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1450 * <zones>. 1451 */ 1452 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1453 u32 uid, u32 obj, u32 count); 1454 1455 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1456 * specifying the uid when freeing an object, zone allocator could figure it by 1457 * itself. Other parameters are similar to mlx4_zone_free. 1458 */ 1459 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1460 1461 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1462 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1463 1464 #endif /* MLX4_H */ 1465