1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef MLX4_FW_H 36 #define MLX4_FW_H 37 38 #include "mlx4.h" 39 #include "icm.h" 40 41 struct mlx4_mod_stat_cfg { 42 u8 log_pg_sz; 43 u8 log_pg_sz_m; 44 }; 45 46 struct mlx4_port_cap { 47 u8 link_state; 48 u8 supported_port_types; 49 u8 suggested_type; 50 u8 default_sense; 51 u8 log_max_macs; 52 u8 log_max_vlans; 53 int ib_mtu; 54 int max_port_width; 55 int max_vl; 56 int max_tc_eth; 57 int max_gids; 58 int max_pkeys; 59 u64 def_mac; 60 u16 eth_mtu; 61 int trans_type; 62 int vendor_oui; 63 u16 wavelength; 64 u64 trans_code; 65 u8 dmfs_optimized_state; 66 }; 67 68 struct mlx4_dev_cap { 69 int max_srq_sz; 70 int max_qp_sz; 71 int reserved_qps; 72 int max_qps; 73 int reserved_srqs; 74 int max_srqs; 75 int max_cq_sz; 76 int reserved_cqs; 77 int max_cqs; 78 int max_mpts; 79 int reserved_eqs; 80 int max_eqs; 81 int num_sys_eqs; 82 int reserved_mtts; 83 int reserved_mrws; 84 int max_requester_per_qp; 85 int max_responder_per_qp; 86 int max_rdma_global; 87 int local_ca_ack_delay; 88 int num_ports; 89 u32 max_msg_sz; 90 u16 stat_rate_support; 91 int fs_log_max_ucast_qp_range_size; 92 int fs_max_num_qp_per_entry; 93 u64 flags; 94 u64 flags2; 95 int reserved_uars; 96 int uar_size; 97 int min_page_sz; 98 int bf_reg_size; 99 int bf_regs_per_page; 100 int max_sq_sg; 101 int max_sq_desc_sz; 102 int max_rq_sg; 103 int max_rq_desc_sz; 104 int max_qp_per_mcg; 105 int reserved_mgms; 106 int max_mcgs; 107 int reserved_pds; 108 int max_pds; 109 int reserved_xrcds; 110 int max_xrcds; 111 int qpc_entry_sz; 112 int rdmarc_entry_sz; 113 int altc_entry_sz; 114 int aux_entry_sz; 115 int srq_entry_sz; 116 int cqc_entry_sz; 117 int eqc_entry_sz; 118 int dmpt_entry_sz; 119 int cmpt_entry_sz; 120 int mtt_entry_sz; 121 int resize_srq; 122 u32 bmme_flags; 123 u32 reserved_lkey; 124 u64 max_icm_sz; 125 int max_gso_sz; 126 int max_rss_tbl_sz; 127 u32 max_counters; 128 u32 dmfs_high_rate_qpn_base; 129 u32 dmfs_high_rate_qpn_range; 130 struct mlx4_rate_limit_caps rl_caps; 131 struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1]; 132 bool map_clock_to_user; 133 }; 134 135 struct mlx4_func_cap { 136 u8 num_ports; 137 u8 flags; 138 u32 pf_context_behaviour; 139 int qp_quota; 140 int cq_quota; 141 int srq_quota; 142 int mpt_quota; 143 int mtt_quota; 144 int max_eq; 145 int reserved_eq; 146 int mcg_quota; 147 u32 qp0_qkey; 148 u32 qp0_tunnel_qpn; 149 u32 qp0_proxy_qpn; 150 u32 qp1_tunnel_qpn; 151 u32 qp1_proxy_qpn; 152 u32 reserved_lkey; 153 u8 physical_port; 154 u8 flags0; 155 u8 flags1; 156 u64 phys_port_id; 157 u32 extra_flags; 158 }; 159 160 struct mlx4_func { 161 int bus; 162 int device; 163 int function; 164 int physical_function; 165 int rsvd_eqs; 166 int max_eq; 167 int rsvd_uars; 168 }; 169 170 struct mlx4_adapter { 171 char board_id[MLX4_BOARD_ID_LEN]; 172 u8 inta_pin; 173 }; 174 175 struct mlx4_init_hca_param { 176 u64 qpc_base; 177 u64 rdmarc_base; 178 u64 auxc_base; 179 u64 altc_base; 180 u64 srqc_base; 181 u64 cqc_base; 182 u64 eqc_base; 183 u64 mc_base; 184 u64 dmpt_base; 185 u64 cmpt_base; 186 u64 mtt_base; 187 u64 global_caps; 188 u16 log_mc_entry_sz; 189 u16 log_mc_hash_sz; 190 u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */ 191 u8 log_num_qps; 192 u8 log_num_srqs; 193 u8 log_num_cqs; 194 u8 log_num_eqs; 195 u16 num_sys_eqs; 196 u8 log_rd_per_qp; 197 u8 log_mc_table_sz; 198 u8 log_mpt_sz; 199 u8 log_uar_sz; 200 u8 mw_enabled; /* Enable memory windows */ 201 u8 uar_page_sz; /* log pg sz in 4k chunks */ 202 u8 steering_mode; /* for QUERY_HCA */ 203 u8 dmfs_high_steer_mode; /* for QUERY_HCA */ 204 u64 dev_cap_enabled; 205 u16 cqe_size; /* For use only when CQE stride feature enabled */ 206 u16 eqe_size; /* For use only when EQE stride feature enabled */ 207 u8 rss_ip_frags; 208 u8 phv_check_en; /* for QUERY_HCA */ 209 }; 210 211 struct mlx4_init_ib_param { 212 int port_width; 213 int vl_cap; 214 int mtu_cap; 215 u16 gid_cap; 216 u16 pkey_cap; 217 int set_guid0; 218 u64 guid0; 219 int set_node_guid; 220 u64 node_guid; 221 int set_si_guid; 222 u64 si_guid; 223 }; 224 225 struct mlx4_set_ib_param { 226 int set_si_guid; 227 int reset_qkey_viol; 228 u64 si_guid; 229 u32 cap_mask; 230 }; 231 232 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); 233 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); 234 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap); 235 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 236 struct mlx4_func_cap *func_cap); 237 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 238 struct mlx4_vhcr *vhcr, 239 struct mlx4_cmd_mailbox *inbox, 240 struct mlx4_cmd_mailbox *outbox, 241 struct mlx4_cmd_info *cmd); 242 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave); 243 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm); 244 int mlx4_UNMAP_FA(struct mlx4_dev *dev); 245 int mlx4_RUN_FW(struct mlx4_dev *dev); 246 int mlx4_QUERY_FW(struct mlx4_dev *dev); 247 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter); 248 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); 249 int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); 250 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic); 251 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt); 252 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages); 253 int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm); 254 int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev); 255 int mlx4_NOP(struct mlx4_dev *dev); 256 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg); 257 void mlx4_opreq_action(struct work_struct *work); 258 259 #endif /* MLX4_FW_H */ 260