1 /*- 2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Development sponsored by Microsemi, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* 31 * Microsemi / Vitesse VSC8501 (and similar). 32 */ 33 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/errno.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/malloc.h> 44 #include <sys/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/if.h> 48 #include <net/if_media.h> 49 50 #include <dev/mii/mii.h> 51 #include <dev/mii/miivar.h> 52 #include "miidevs.h" 53 #include "miibus_if.h" 54 55 #ifdef FDT 56 #include <dev/ofw/openfirm.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 #include <dev/mii/mii_fdt.h> 60 #endif 61 62 #define BIT(x) (1 << (x)) 63 64 /* Vitesse VSC8501 */ 65 #define VSC8501_EXTPAGE_REG 0x001f 66 67 #define VSC8501_EXTCTL1_REG 0x0017 68 #define VSC8501_EXTCTL1_RGMII_MODE (1u << 12) 69 70 #define VSC8501_INT_MASK 0x19 71 #define VSC8501_INT_MDINT BIT(15) 72 #define VSC8501_INT_SPD_CHG BIT(14) 73 #define VSC8501_INT_LINK_CHG BIT(13) 74 #define VSC8501_INT_FD_CHG BIT(12) 75 #define VSC8501_INT_AN_CMPL BIT(10) 76 77 #define VSC8501_INT_STS 0x1a 78 79 #define VSC8501_RGMII_CTRL_PAGE 0x02 80 #define VSC8501_RGMII_CTRL_REG 0x14 81 #define VSC8501_RGMII_DELAY_MASK 0x07 82 #define VSC8501_RGMII_DELAY_TXSHIFT 0 83 #define VSC8501_RGMII_DELAY_RXSHIFT 4 84 #define VSC8501_RGMII_RXCLOCK_DISABLE (1u << 11) 85 #define VSC8501_RGMII_RXSWAP (1u << 7) 86 #define VSC8501_RGMII_TXSWAP (1u << 3) 87 #define VSC8501_RGMII_LANESWAP (VSC8501_RGMII_RXSWAP | \ 88 VSC8501_RGMII_TXSWAP) 89 90 struct vscphy_softc { 91 mii_softc_t mii_sc; 92 device_t dev; 93 mii_contype_t contype; 94 int rxdelay; 95 int txdelay; 96 bool laneswap; 97 struct resource *irq_res; 98 void *irq_cookie; 99 }; 100 101 static void vscphy_reset(struct mii_softc *); 102 static int vscphy_service(struct mii_softc *, struct mii_data *, int); 103 104 static const struct mii_phydesc vscphys[] = { 105 MII_PHY_DESC(xxVITESSE, VSC8501), 106 MII_PHY_DESC(xxVITESSE, VSC8504), 107 MII_PHY_END 108 }; 109 110 static const struct mii_phy_funcs vscphy_funcs = { 111 vscphy_service, 112 ukphy_status, 113 vscphy_reset 114 }; 115 116 #ifdef FDT 117 static void 118 vscphy_fdt_get_config(struct vscphy_softc *vsc) 119 { 120 mii_fdt_phy_config_t *cfg; 121 pcell_t val; 122 123 cfg = mii_fdt_get_config(vsc->dev); 124 vsc->contype = cfg->con_type; 125 vsc->laneswap = (cfg->flags & MIIF_FDT_LANE_SWAP) && 126 !(cfg->flags & MIIF_FDT_NO_LANE_SWAP); 127 if (OF_getencprop(cfg->phynode, "rx-delay", &val, sizeof(val)) > 0) 128 vsc->rxdelay = val; 129 if (OF_getencprop(cfg->phynode, "tx-delay", &val, sizeof(val)) > 0) 130 vsc->txdelay = val; 131 vsc->mii_sc.mii_maxspeed = cfg->max_speed; 132 mii_fdt_free_config(cfg); 133 } 134 #endif 135 136 static inline int 137 vscphy_read(struct vscphy_softc *sc, u_int reg) 138 { 139 u_int val; 140 141 val = PHY_READ(&sc->mii_sc, reg); 142 return (val); 143 } 144 145 static inline void 146 vscphy_write(struct vscphy_softc *sc, u_int reg, u_int val) 147 { 148 149 PHY_WRITE(&sc->mii_sc, reg, val); 150 } 151 152 static void 153 vsc8501_setup_rgmii(struct vscphy_softc *vsc) 154 { 155 int reg; 156 157 vscphy_write(vsc, VSC8501_EXTPAGE_REG, VSC8501_RGMII_CTRL_PAGE); 158 159 reg = vscphy_read(vsc, VSC8501_RGMII_CTRL_REG); 160 reg &= ~VSC8501_RGMII_RXCLOCK_DISABLE; 161 reg &= ~VSC8501_RGMII_LANESWAP; 162 reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_TXSHIFT); 163 reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_RXSHIFT); 164 if (vsc->laneswap) 165 reg |= VSC8501_RGMII_LANESWAP; 166 if (vsc->contype == MII_CONTYPE_RGMII_ID || 167 vsc->contype == MII_CONTYPE_RGMII_TXID) { 168 reg |= vsc->txdelay << VSC8501_RGMII_DELAY_TXSHIFT; 169 } 170 if (vsc->contype == MII_CONTYPE_RGMII_ID || 171 vsc->contype == MII_CONTYPE_RGMII_RXID) { 172 reg |= vsc->rxdelay << VSC8501_RGMII_DELAY_RXSHIFT; 173 } 174 vscphy_write(vsc, VSC8501_RGMII_CTRL_REG, reg); 175 176 vscphy_write(vsc, VSC8501_EXTPAGE_REG, 0); 177 } 178 179 static void 180 vsc8501_reset(struct vscphy_softc *vsc) 181 { 182 int reg; 183 184 /* 185 * Must set whether the mac<->phy connection is RGMII first; changes to 186 * that bit take effect only after a softreset. 187 */ 188 reg = vscphy_read(vsc, VSC8501_EXTCTL1_REG); 189 if (mii_contype_is_rgmii(vsc->contype)) 190 reg |= VSC8501_EXTCTL1_RGMII_MODE; 191 else 192 reg &= ~VSC8501_EXTCTL1_RGMII_MODE; 193 vscphy_write(vsc, VSC8501_EXTCTL1_REG, reg); 194 195 mii_phy_reset(&vsc->mii_sc); 196 197 /* 198 * Setup rgmii control register if necessary, after softreset. 199 */ 200 if (mii_contype_is_rgmii(vsc->contype)) 201 vsc8501_setup_rgmii(vsc); 202 } 203 204 static void 205 vscphy_reset(struct mii_softc *sc) 206 { 207 struct vscphy_softc *vsc = (struct vscphy_softc *)sc; 208 209 switch (sc->mii_mpd_model) { 210 case MII_MODEL_xxVITESSE_VSC8501: 211 vsc8501_reset(vsc); 212 break; 213 default: 214 mii_phy_reset(sc); 215 break; 216 } 217 } 218 219 static int 220 vscphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 221 { 222 223 switch (cmd) { 224 case MII_POLLSTAT: 225 break; 226 227 case MII_MEDIACHG: 228 mii_phy_setmedia(sc); 229 break; 230 231 case MII_TICK: 232 if (mii_phy_tick(sc) == EJUSTRETURN) 233 return (0); 234 break; 235 } 236 237 /* Update the media status. */ 238 PHY_STATUS(sc); 239 240 /* Callback if something changed. */ 241 mii_phy_update(sc, cmd); 242 return (0); 243 } 244 245 static int 246 vscphy_probe(device_t dev) 247 { 248 249 return (mii_phy_dev_probe(dev, vscphys, BUS_PROBE_DEFAULT)); 250 } 251 252 static void 253 vscphy_intr(void *arg) 254 { 255 struct vscphy_softc *vsc; 256 uint32_t status; 257 258 vsc = (struct vscphy_softc *)arg; 259 260 status = vscphy_read(vsc, VSC8501_INT_STS); 261 status &= vscphy_read(vsc, VSC8501_INT_MASK); 262 263 if (!status) 264 return; 265 266 PHY_STATUS(&vsc->mii_sc); 267 mii_phy_update(&vsc->mii_sc, MII_MEDIACHG); 268 } 269 270 static int 271 vscphy_attach(device_t dev) 272 { 273 struct vscphy_softc *vsc; 274 uint32_t value; 275 int rid, error; 276 277 vsc = device_get_softc(dev); 278 vsc->dev = dev; 279 280 #ifdef FDT 281 vscphy_fdt_get_config(vsc); 282 #endif 283 284 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &vscphy_funcs, 1); 285 mii_phy_setmedia(&vsc->mii_sc); 286 287 rid = 0; 288 vsc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 289 RF_ACTIVE | RF_SHAREABLE); 290 if (vsc->irq_res == NULL) 291 goto no_irq; 292 293 error = bus_setup_intr(dev, vsc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 294 NULL, vscphy_intr, vsc, &vsc->irq_cookie); 295 if (error != 0) { 296 bus_release_resource(dev, SYS_RES_IRQ, 0, vsc->irq_res); 297 vsc->irq_res = NULL; 298 goto no_irq; 299 } 300 301 /* Ack and unmask all relevant interrupts. */ 302 (void)vscphy_read(vsc, VSC8501_INT_STS); 303 value = VSC8501_INT_MDINT | 304 VSC8501_INT_SPD_CHG | 305 VSC8501_INT_LINK_CHG | 306 VSC8501_INT_FD_CHG | 307 VSC8501_INT_AN_CMPL; 308 vscphy_write(vsc, VSC8501_INT_MASK, value); 309 310 no_irq: 311 return (0); 312 } 313 314 static int 315 vscphy_detach(device_t dev) 316 { 317 struct vscphy_softc *vsc; 318 319 vsc = device_get_softc(dev); 320 321 bus_teardown_intr(dev, vsc->irq_res, vsc->irq_cookie); 322 bus_release_resource(dev, SYS_RES_IRQ, 0, vsc->irq_res); 323 324 return (mii_phy_detach(dev)); 325 } 326 327 static device_method_t vscphy_methods[] = { 328 /* device interface */ 329 DEVMETHOD(device_probe, vscphy_probe), 330 DEVMETHOD(device_attach, vscphy_attach), 331 DEVMETHOD(device_detach, vscphy_detach), 332 DEVMETHOD(device_shutdown, bus_generic_shutdown), 333 DEVMETHOD_END 334 }; 335 336 static driver_t vscphy_driver = { 337 "vscphy", 338 vscphy_methods, 339 sizeof(struct vscphy_softc) 340 }; 341 342 DRIVER_MODULE(vscphy, miibus, vscphy_driver, 0, 0); 343