1 /*- 2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Development sponsored by Microsemi, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Microsemi / Vitesse VSC8501 (and similar). 34 */ 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/errno.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/malloc.h> 46 #include <sys/resource.h> 47 #include <sys/rman.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 #include "miibus_if.h" 56 57 #ifdef FDT 58 #include <dev/ofw/openfirm.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/mii/mii_fdt.h> 62 #endif 63 64 #define BIT(x) (1 << (x)) 65 66 /* Vitesse VSC8501 */ 67 #define VSC8501_EXTPAGE_REG 0x001f 68 69 #define VSC8501_EXTCTL1_REG 0x0017 70 #define VSC8501_EXTCTL1_RGMII_MODE (1u << 12) 71 72 #define VSC8501_INT_MASK 0x19 73 #define VSC8501_INT_MDINT BIT(15) 74 #define VSC8501_INT_SPD_CHG BIT(14) 75 #define VSC8501_INT_LINK_CHG BIT(13) 76 #define VSC8501_INT_FD_CHG BIT(12) 77 #define VSC8501_INT_AN_CMPL BIT(10) 78 79 #define VSC8501_INT_STS 0x1a 80 81 #define VSC8501_RGMII_CTRL_PAGE 0x02 82 #define VSC8501_RGMII_CTRL_REG 0x14 83 #define VSC8501_RGMII_DELAY_MASK 0x07 84 #define VSC8501_RGMII_DELAY_TXSHIFT 0 85 #define VSC8501_RGMII_DELAY_RXSHIFT 4 86 #define VSC8501_RGMII_RXCLOCK_DISABLE (1u << 11) 87 #define VSC8501_RGMII_RXSWAP (1u << 7) 88 #define VSC8501_RGMII_TXSWAP (1u << 3) 89 #define VSC8501_RGMII_LANESWAP (VSC8501_RGMII_RXSWAP | \ 90 VSC8501_RGMII_TXSWAP) 91 92 struct vscphy_softc { 93 mii_softc_t mii_sc; 94 device_t dev; 95 mii_contype_t contype; 96 int rxdelay; 97 int txdelay; 98 bool laneswap; 99 struct resource *irq_res; 100 void *irq_cookie; 101 }; 102 103 static void vscphy_reset(struct mii_softc *); 104 static int vscphy_service(struct mii_softc *, struct mii_data *, int); 105 106 static const struct mii_phydesc vscphys[] = { 107 MII_PHY_DESC(xxVITESSE, VSC8501), 108 MII_PHY_DESC(xxVITESSE, VSC8504), 109 MII_PHY_END 110 }; 111 112 static const struct mii_phy_funcs vscphy_funcs = { 113 vscphy_service, 114 ukphy_status, 115 vscphy_reset 116 }; 117 118 #ifdef FDT 119 static void 120 vscphy_fdt_get_config(struct vscphy_softc *vsc) 121 { 122 mii_fdt_phy_config_t *cfg; 123 pcell_t val; 124 125 cfg = mii_fdt_get_config(vsc->dev); 126 vsc->contype = cfg->con_type; 127 vsc->laneswap = (cfg->flags & MIIF_FDT_LANE_SWAP) && 128 !(cfg->flags & MIIF_FDT_NO_LANE_SWAP); 129 if (OF_getencprop(cfg->phynode, "rx-delay", &val, sizeof(val)) > 0) 130 vsc->rxdelay = val; 131 if (OF_getencprop(cfg->phynode, "tx-delay", &val, sizeof(val)) > 0) 132 vsc->txdelay = val; 133 vsc->mii_sc.mii_maxspeed = cfg->max_speed; 134 mii_fdt_free_config(cfg); 135 } 136 #endif 137 138 static inline int 139 vscphy_read(struct vscphy_softc *sc, u_int reg) 140 { 141 u_int val; 142 143 val = PHY_READ(&sc->mii_sc, reg); 144 return (val); 145 } 146 147 static inline void 148 vscphy_write(struct vscphy_softc *sc, u_int reg, u_int val) 149 { 150 151 PHY_WRITE(&sc->mii_sc, reg, val); 152 } 153 154 static void 155 vsc8501_setup_rgmii(struct vscphy_softc *vsc) 156 { 157 int reg; 158 159 vscphy_write(vsc, VSC8501_EXTPAGE_REG, VSC8501_RGMII_CTRL_PAGE); 160 161 reg = vscphy_read(vsc, VSC8501_RGMII_CTRL_REG); 162 reg &= ~VSC8501_RGMII_RXCLOCK_DISABLE; 163 reg &= ~VSC8501_RGMII_LANESWAP; 164 reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_TXSHIFT); 165 reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_RXSHIFT); 166 if (vsc->laneswap) 167 reg |= VSC8501_RGMII_LANESWAP; 168 if (vsc->contype == MII_CONTYPE_RGMII_ID || 169 vsc->contype == MII_CONTYPE_RGMII_TXID) { 170 reg |= vsc->txdelay << VSC8501_RGMII_DELAY_TXSHIFT; 171 } 172 if (vsc->contype == MII_CONTYPE_RGMII_ID || 173 vsc->contype == MII_CONTYPE_RGMII_RXID) { 174 reg |= vsc->rxdelay << VSC8501_RGMII_DELAY_RXSHIFT; 175 } 176 vscphy_write(vsc, VSC8501_RGMII_CTRL_REG, reg); 177 178 vscphy_write(vsc, VSC8501_EXTPAGE_REG, 0); 179 } 180 181 static void 182 vsc8501_reset(struct vscphy_softc *vsc) 183 { 184 int reg; 185 186 /* 187 * Must set whether the mac<->phy connection is RGMII first; changes to 188 * that bit take effect only after a softreset. 189 */ 190 reg = vscphy_read(vsc, VSC8501_EXTCTL1_REG); 191 if (mii_contype_is_rgmii(vsc->contype)) 192 reg |= VSC8501_EXTCTL1_RGMII_MODE; 193 else 194 reg &= ~VSC8501_EXTCTL1_RGMII_MODE; 195 vscphy_write(vsc, VSC8501_EXTCTL1_REG, reg); 196 197 mii_phy_reset(&vsc->mii_sc); 198 199 /* 200 * Setup rgmii control register if necessary, after softreset. 201 */ 202 if (mii_contype_is_rgmii(vsc->contype)) 203 vsc8501_setup_rgmii(vsc); 204 } 205 206 static void 207 vscphy_reset(struct mii_softc *sc) 208 { 209 struct vscphy_softc *vsc = (struct vscphy_softc *)sc; 210 211 switch (sc->mii_mpd_model) { 212 case MII_MODEL_xxVITESSE_VSC8501: 213 vsc8501_reset(vsc); 214 break; 215 default: 216 mii_phy_reset(sc); 217 break; 218 } 219 } 220 221 static int 222 vscphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 223 { 224 225 switch (cmd) { 226 case MII_POLLSTAT: 227 break; 228 229 case MII_MEDIACHG: 230 mii_phy_setmedia(sc); 231 break; 232 233 case MII_TICK: 234 if (mii_phy_tick(sc) == EJUSTRETURN) 235 return (0); 236 break; 237 } 238 239 /* Update the media status. */ 240 PHY_STATUS(sc); 241 242 /* Callback if something changed. */ 243 mii_phy_update(sc, cmd); 244 return (0); 245 } 246 247 static int 248 vscphy_probe(device_t dev) 249 { 250 251 return (mii_phy_dev_probe(dev, vscphys, BUS_PROBE_DEFAULT)); 252 } 253 254 static void 255 vscphy_intr(void *arg) 256 { 257 struct vscphy_softc *vsc; 258 uint32_t status; 259 260 vsc = (struct vscphy_softc *)arg; 261 262 status = vscphy_read(vsc, VSC8501_INT_STS); 263 status &= vscphy_read(vsc, VSC8501_INT_MASK); 264 265 if (!status) 266 return; 267 268 PHY_STATUS(&vsc->mii_sc); 269 mii_phy_update(&vsc->mii_sc, MII_MEDIACHG); 270 } 271 272 static int 273 vscphy_attach(device_t dev) 274 { 275 struct vscphy_softc *vsc; 276 uint32_t value; 277 int rid, error; 278 279 vsc = device_get_softc(dev); 280 vsc->dev = dev; 281 282 #ifdef FDT 283 vscphy_fdt_get_config(vsc); 284 #endif 285 286 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &vscphy_funcs, 1); 287 mii_phy_setmedia(&vsc->mii_sc); 288 289 rid = 0; 290 vsc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 291 RF_ACTIVE | RF_SHAREABLE); 292 if (vsc->irq_res == NULL) 293 goto no_irq; 294 295 error = bus_setup_intr(dev, vsc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 296 NULL, vscphy_intr, vsc, &vsc->irq_cookie); 297 if (error != 0) { 298 bus_release_resource(dev, SYS_RES_IRQ, 0, vsc->irq_res); 299 vsc->irq_res = NULL; 300 goto no_irq; 301 } 302 303 /* Ack and unmask all relevant interrupts. */ 304 (void)vscphy_read(vsc, VSC8501_INT_STS); 305 value = VSC8501_INT_MDINT | 306 VSC8501_INT_SPD_CHG | 307 VSC8501_INT_LINK_CHG | 308 VSC8501_INT_FD_CHG | 309 VSC8501_INT_AN_CMPL; 310 vscphy_write(vsc, VSC8501_INT_MASK, value); 311 312 no_irq: 313 return (0); 314 } 315 316 static int 317 vscphy_detach(device_t dev) 318 { 319 struct vscphy_softc *vsc; 320 321 vsc = device_get_softc(dev); 322 323 bus_teardown_intr(dev, vsc->irq_res, vsc->irq_cookie); 324 bus_release_resource(dev, SYS_RES_IRQ, 0, vsc->irq_res); 325 326 return (mii_phy_detach(dev)); 327 } 328 329 static device_method_t vscphy_methods[] = { 330 /* device interface */ 331 DEVMETHOD(device_probe, vscphy_probe), 332 DEVMETHOD(device_attach, vscphy_attach), 333 DEVMETHOD(device_detach, vscphy_detach), 334 DEVMETHOD(device_shutdown, bus_generic_shutdown), 335 DEVMETHOD_END 336 }; 337 338 static devclass_t vscphy_devclass; 339 340 static driver_t vscphy_driver = { 341 "vscphy", 342 vscphy_methods, 343 sizeof(struct vscphy_softc) 344 }; 345 346 DRIVER_MODULE(vscphy, miibus, vscphy_driver, vscphy_devclass, 0, 0); 347