xref: /freebsd/sys/dev/mii/truephy.c (revision aa0a1e58f0189b0fde359a8bda032887e72057fa)
1 /*-
2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
3  *
4  * This code is derived from software contributed to The DragonFly Project
5  * by Sepherosa Ziehau <sepherosa@gmail.com>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in
15  *    the documentation and/or other materials provided with the
16  *    distribution.
17  * 3. Neither the name of The DragonFly Project nor the names of its
18  *    contributors may be used to endorse or promote products derived
19  *    from this software without specific, prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  *
34  * $DragonFly: src/sys/dev/netif/mii_layer/truephy.c,v 1.3 2008/02/10 07:29:27 sephe Exp $
35  * $FreeBSD$
36  */
37 
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/errno.h>
43 #include <sys/module.h>
44 #include <sys/bus.h>
45 
46 #include <net/if.h>
47 #include <net/if_media.h>
48 #include <net/if_arp.h>
49 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
51 
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
54 #include "miidevs.h"
55 
56 #include <dev/mii/truephyreg.h>
57 
58 #include "miibus_if.h"
59 
60 #define	TRUEPHY_FRAMELEN(mtu)	\
61     (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + (mtu) + ETHER_CRC_LEN)
62 
63 static int	truephy_service(struct mii_softc *, struct mii_data *, int);
64 static int	truephy_attach(device_t);
65 static int	truephy_probe(device_t);
66 static void	truephy_reset(struct mii_softc *);
67 static void	truephy_status(struct mii_softc *);
68 
69 static device_method_t truephy_methods[] = {
70 	/* device interface */
71 	DEVMETHOD(device_probe,		truephy_probe),
72 	DEVMETHOD(device_attach,	truephy_attach),
73 	DEVMETHOD(device_detach,	mii_phy_detach),
74 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
75 	{ 0, 0 }
76 };
77 
78 static const struct mii_phydesc truephys[] = {
79 	MII_PHY_DESC(AGERE,	ET1011),
80 	MII_PHY_DESC(AGERE,	ET1011C),
81 	MII_PHY_END
82 };
83 
84 static devclass_t truephy_devclass;
85 
86 static driver_t truephy_driver = {
87 	"truephy",
88 	truephy_methods,
89 	sizeof(struct mii_softc)
90 };
91 
92 DRIVER_MODULE(truephy, miibus, truephy_driver, truephy_devclass, 0, 0);
93 
94 static const struct truephy_dsp {
95 	uint16_t	index;
96 	uint16_t	data;
97 } truephy_dspcode[] = {
98 	{ 0x880b,	0x0926 },	/* AfeIfCreg4B1000Msbs */
99 	{ 0x880c,	0x0926 },	/* AfeIfCreg4B100Msbs */
100 	{ 0x880d,	0x0926 },	/* AfeIfCreg4B10Msbs */
101 
102 	{ 0x880e,	0xb4d3 },	/* AfeIfCreg4B1000Lsbs */
103 	{ 0x880f,	0xb4d3 },	/* AfeIfCreg4B100Lsbs */
104 	{ 0x8810,	0xb4d3 },	/* AfeIfCreg4B10Lsbs */
105 
106 	{ 0x8805,	0xb03e },	/* AfeIfCreg3B1000Msbs */
107 	{ 0x8806,	0xb03e },	/* AfeIfCreg3B100Msbs */
108 	{ 0x8807,	0xff00 },	/* AfeIfCreg3B10Msbs */
109 
110 	{ 0x8808,	0xe090 },	/* AfeIfCreg3B1000Lsbs */
111 	{ 0x8809,	0xe110 },	/* AfeIfCreg3B100Lsbs */
112 	{ 0x880a,	0x0000 },	/* AfeIfCreg3B10Lsbs */
113 
114 	{ 0x300d,	1      },	/* DisableNorm */
115 
116 	{ 0x280c,	0x0180 },	/* LinkHoldEnd */
117 
118 	{ 0x1c21,	0x0002 },	/* AlphaM */
119 
120 	{ 0x3821,	6      },	/* FfeLkgTx0 */
121 	{ 0x381d,	1      },	/* FfeLkg1g4 */
122 	{ 0x381e,	1      },	/* FfeLkg1g5 */
123 	{ 0x381f,	1      },	/* FfeLkg1g6 */
124 	{ 0x3820,	1      },	/* FfeLkg1g7 */
125 
126 	{ 0x8402,	0x01f0 },	/* Btinact */
127 	{ 0x800e,	20     },	/* LftrainTime */
128 	{ 0x800f,	24     },	/* DvguardTime */
129 	{ 0x8010,	46     }	/* IdlguardTime */
130 };
131 
132 static int
133 truephy_probe(device_t dev)
134 {
135 
136 	return (mii_phy_dev_probe(dev, truephys, BUS_PROBE_DEFAULT));
137 }
138 
139 static int
140 truephy_attach(device_t dev)
141 {
142 	struct mii_softc *sc;
143 	struct mii_attach_args *ma;
144 	struct mii_data *mii;
145 
146 	sc = device_get_softc(dev);
147 	ma = device_get_ivars(dev);
148 
149 	sc->mii_phy = ma->mii_phyno;
150 	sc->mii_dev = device_get_parent(dev);
151 	mii = ma->mii_data;
152 	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
153 
154 	sc->mii_flags = miibus_get_flags(dev);
155 	sc->mii_inst = mii->mii_instance++;
156 	sc->mii_phy = ma->mii_phyno;
157 	sc->mii_service = truephy_service;
158 	sc->mii_pdata = mii;
159 
160 	sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
161 
162 	if (MII_MODEL(ma->mii_id2) == MII_MODEL_AGERE_ET1011)
163 		mii_phy_reset(sc);
164 	else
165 		truephy_reset(sc);
166 
167 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
168 	if (sc->mii_capabilities & BMSR_EXTSTAT) {
169 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
170 		/* No 1000baseT half-duplex support */
171 		sc->mii_extcapabilities &= ~EXTSR_1000THDX;
172 	}
173 
174 	device_printf(dev, " ");
175 	mii_phy_add_media(sc);
176 	printf("\n");
177 
178 	MIIBUS_MEDIAINIT(sc->mii_dev);
179 	return (0);
180 }
181 
182 static int
183 truephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
184 {
185 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
186 	int bmcr;
187 
188 	switch (cmd) {
189 	case MII_POLLSTAT:
190 		break;
191 
192 	case MII_MEDIACHG:
193 		/*
194 		 * If the interface is not up, don't do anything.
195 		 */
196 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
197 			break;
198 
199 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
200 			bmcr = PHY_READ(sc, MII_BMCR) & ~BMCR_AUTOEN;
201 			PHY_WRITE(sc, MII_BMCR, bmcr);
202 			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_PDOWN);
203 		}
204 
205 		mii_phy_setmedia(sc);
206 
207 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
208 			bmcr = PHY_READ(sc, MII_BMCR) & ~BMCR_PDOWN;
209 			PHY_WRITE(sc, MII_BMCR, bmcr);
210 
211 			if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
212 				PHY_WRITE(sc, MII_BMCR,
213 					  bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
214 			}
215 		}
216 		break;
217 
218 	case MII_TICK:
219 		if (mii_phy_tick(sc) == EJUSTRETURN)
220 			return (0);
221 		break;
222 	}
223 
224 	/* Update the media status. */
225 	truephy_status(sc);
226 
227 	/* Callback if something changed. */
228 	mii_phy_update(sc, cmd);
229 	return (0);
230 }
231 
232 static void
233 truephy_reset(struct mii_softc *sc)
234 {
235 	int i;
236 
237 	for (i = 0; i < 2; ++i) {
238 		PHY_READ(sc, MII_PHYIDR1);
239 		PHY_READ(sc, MII_PHYIDR2);
240 
241 		PHY_READ(sc, TRUEPHY_CTRL);
242 		PHY_WRITE(sc, TRUEPHY_CTRL,
243 			  TRUEPHY_CTRL_DIAG | TRUEPHY_CTRL_RSV1);
244 
245 		PHY_WRITE(sc, TRUEPHY_INDEX, TRUEPHY_INDEX_MAGIC);
246 		PHY_READ(sc, TRUEPHY_DATA);
247 
248 		PHY_WRITE(sc, TRUEPHY_CTRL, TRUEPHY_CTRL_RSV1);
249 	}
250 
251 	PHY_READ(sc, MII_BMCR);
252 	PHY_READ(sc, TRUEPHY_CTRL);
253 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN | BMCR_S1000);
254 	PHY_WRITE(sc, TRUEPHY_CTRL,
255 		  TRUEPHY_CTRL_DIAG | TRUEPHY_CTRL_RSV1 | TRUEPHY_CTRL_RSV0);
256 
257 #define N(arr)	(int)(sizeof(arr) / sizeof(arr[0]))
258 
259 	for (i = 0; i < N(truephy_dspcode); ++i) {
260 		const struct truephy_dsp *dsp = &truephy_dspcode[i];
261 
262 		PHY_WRITE(sc, TRUEPHY_INDEX, dsp->index);
263 		PHY_WRITE(sc, TRUEPHY_DATA, dsp->data);
264 
265 		PHY_WRITE(sc, TRUEPHY_INDEX, dsp->index);
266 		PHY_READ(sc, TRUEPHY_DATA);
267 	}
268 
269 #undef N
270 
271 	PHY_READ(sc, MII_BMCR);
272 	PHY_READ(sc, TRUEPHY_CTRL);
273 	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN |  BMCR_S1000);
274 	PHY_WRITE(sc, TRUEPHY_CTRL, TRUEPHY_CTRL_RSV1);
275 
276 	mii_phy_reset(sc);
277 
278 	if (TRUEPHY_FRAMELEN(sc->mii_pdata->mii_ifp->if_mtu) > 2048) {
279 		int conf;
280 
281 		conf = PHY_READ(sc, TRUEPHY_CONF);
282 		conf &= ~TRUEPHY_CONF_TXFIFO_MASK;
283 		conf |= TRUEPHY_CONF_TXFIFO_24;
284 		PHY_WRITE(sc, TRUEPHY_CONF, conf);
285 	}
286 }
287 
288 static void
289 truephy_status(struct mii_softc *sc)
290 {
291 	struct mii_data *mii = sc->mii_pdata;
292 	int bmsr, bmcr, sr;
293 
294 	mii->mii_media_status = IFM_AVALID;
295 	mii->mii_media_active = IFM_ETHER;
296 
297 	sr = PHY_READ(sc, TRUEPHY_SR);
298 	bmcr = PHY_READ(sc, MII_BMCR);
299 
300 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
301 	if (bmsr & BMSR_LINK)
302 		mii->mii_media_status |= IFM_ACTIVE;
303 
304 	if (bmcr & BMCR_AUTOEN) {
305 		if ((bmsr & BMSR_ACOMP) == 0) {
306 			mii->mii_media_active |= IFM_NONE;
307 			return;
308 		}
309 	}
310 
311 	switch (sr & TRUEPHY_SR_SPD_MASK) {
312 	case TRUEPHY_SR_SPD_1000T:
313 		mii->mii_media_active |= IFM_1000_T;
314 		break;
315 	case TRUEPHY_SR_SPD_100TX:
316 		mii->mii_media_active |= IFM_100_TX;
317 		break;
318 	case TRUEPHY_SR_SPD_10T:
319 		mii->mii_media_active |= IFM_10_T;
320 		break;
321 	default:
322 		/* XXX will this ever happen? */
323 		printf("invalid media SR %#x\n", sr);
324 		mii->mii_media_active |= IFM_NONE;
325 		return;
326 	}
327 
328 	if (sr & TRUEPHY_SR_FDX)
329 		mii->mii_media_active |= IFM_FDX;
330 	else
331 		mii->mii_media_active |= IFM_HDX;
332 }
333