1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * Copyright (c) 2006 Bernd Walter. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * driver for RealTek 8305 pseudo PHYs 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/socket.h> 48 #include <sys/bus.h> 49 #include <sys/taskqueue.h> /* XXXGL: if_rlreg.h contamination */ 50 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <machine/bus.h> 60 #include <dev/rl/if_rlreg.h> 61 62 #include "miibus_if.h" 63 64 //#define RL_DEBUG 65 #define RL_VLAN 66 67 static int rlswitch_probe(device_t); 68 static int rlswitch_attach(device_t); 69 70 static device_method_t rlswitch_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, rlswitch_probe), 73 DEVMETHOD(device_attach, rlswitch_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 DEVMETHOD_END 77 }; 78 79 static devclass_t rlswitch_devclass; 80 81 static driver_t rlswitch_driver = { 82 "rlswitch", 83 rlswitch_methods, 84 sizeof(struct mii_softc) 85 }; 86 87 DRIVER_MODULE(rlswitch, miibus, rlswitch_driver, rlswitch_devclass, 0, 0); 88 89 static int rlswitch_service(struct mii_softc *, struct mii_data *, int); 90 static void rlswitch_status(struct mii_softc *); 91 92 #ifdef RL_DEBUG 93 static void rlswitch_phydump(device_t dev); 94 #endif 95 96 static const struct mii_phydesc rlswitches[] = { 97 MII_PHY_DESC(REALTEK, RTL8305SC), 98 MII_PHY_END 99 }; 100 101 static const struct mii_phy_funcs rlswitch_funcs = { 102 rlswitch_service, 103 rlswitch_status, 104 mii_phy_reset 105 }; 106 107 static int 108 rlswitch_probe(device_t dev) 109 { 110 int rv; 111 112 rv = mii_phy_dev_probe(dev, rlswitches, BUS_PROBE_DEFAULT); 113 if (rv <= 0) 114 return (rv); 115 116 return (ENXIO); 117 } 118 119 static int 120 rlswitch_attach(device_t dev) 121 { 122 struct mii_softc *sc; 123 124 sc = device_get_softc(dev); 125 126 /* 127 * We handle all pseudo PHYs in a single instance. 128 */ 129 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 130 &rlswitch_funcs, 0); 131 132 sc->mii_capabilities = BMSR_100TXFDX & sc->mii_capmask; 133 device_printf(dev, " "); 134 mii_phy_add_media(sc); 135 printf("\n"); 136 #ifdef RL_DEBUG 137 rlswitch_phydump(dev); 138 #endif 139 140 #ifdef RL_VLAN 141 int val; 142 143 /* Global Control 0 */ 144 val = 0; 145 val |= 0 << 10; /* enable 802.1q VLAN Tag support */ 146 val |= 0 << 9; /* enable VLAN ingress filtering */ 147 val |= 1 << 8; /* disable VLAN tag admit control */ 148 val |= 1 << 6; /* internal use */ 149 val |= 1 << 5; /* internal use */ 150 val |= 1 << 4; /* internal use */ 151 val |= 1 << 3; /* internal use */ 152 val |= 1 << 1; /* reserved */ 153 MIIBUS_WRITEREG(sc->mii_dev, 0, 16, val); 154 155 /* Global Control 2 */ 156 val = 0; 157 val |= 1 << 15; /* reserved */ 158 val |= 0 << 14; /* enable 1552 Bytes support */ 159 val |= 1 << 13; /* enable broadcast input drop */ 160 val |= 1 << 12; /* forward reserved control frames */ 161 val |= 1 << 11; /* disable forwarding unicast frames to other VLAN's */ 162 val |= 1 << 10; /* disable forwarding ARP broadcasts to other VLAN's */ 163 val |= 1 << 9; /* enable 48 pass 1 */ 164 val |= 0 << 8; /* enable VLAN */ 165 val |= 1 << 7; /* reserved */ 166 val |= 1 << 6; /* enable defer */ 167 val |= 1 << 5; /* 43ms LED blink time */ 168 val |= 3 << 3; /* 16:1 queue weight */ 169 val |= 1 << 2; /* disable broadcast storm control */ 170 val |= 1 << 1; /* enable power-on LED blinking */ 171 val |= 1 << 0; /* reserved */ 172 MIIBUS_WRITEREG(sc->mii_dev, 0, 18, val); 173 174 /* Port 0 Control Register 0 */ 175 val = 0; 176 val |= 1 << 15; /* reserved */ 177 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 178 val |= 1 << 10; /* disable 802.1p priority classification */ 179 val |= 1 << 9; /* disable diffserv priority classification */ 180 val |= 1 << 6; /* internal use */ 181 val |= 3 << 4; /* internal use */ 182 val |= 1 << 3; /* internal use */ 183 val |= 1 << 2; /* internal use */ 184 val |= 1 << 0; /* remove VLAN tags on output */ 185 MIIBUS_WRITEREG(sc->mii_dev, 0, 22, val); 186 187 /* Port 1 Control Register 0 */ 188 val = 0; 189 val |= 1 << 15; /* reserved */ 190 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 191 val |= 1 << 10; /* disable 802.1p priority classification */ 192 val |= 1 << 9; /* disable diffserv priority classification */ 193 val |= 1 << 6; /* internal use */ 194 val |= 3 << 4; /* internal use */ 195 val |= 1 << 3; /* internal use */ 196 val |= 1 << 2; /* internal use */ 197 val |= 1 << 0; /* remove VLAN tags on output */ 198 MIIBUS_WRITEREG(sc->mii_dev, 1, 22, val); 199 200 /* Port 2 Control Register 0 */ 201 val = 0; 202 val |= 1 << 15; /* reserved */ 203 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 204 val |= 1 << 10; /* disable 802.1p priority classification */ 205 val |= 1 << 9; /* disable diffserv priority classification */ 206 val |= 1 << 6; /* internal use */ 207 val |= 3 << 4; /* internal use */ 208 val |= 1 << 3; /* internal use */ 209 val |= 1 << 2; /* internal use */ 210 val |= 1 << 0; /* remove VLAN tags on output */ 211 MIIBUS_WRITEREG(sc->mii_dev, 2, 22, val); 212 213 /* Port 3 Control Register 0 */ 214 val = 0; 215 val |= 1 << 15; /* reserved */ 216 val |= 1 << 11; /* drop received packets with wrong VLAN tag */ 217 val |= 1 << 10; /* disable 802.1p priority classification */ 218 val |= 1 << 9; /* disable diffserv priority classification */ 219 val |= 1 << 6; /* internal use */ 220 val |= 3 << 4; /* internal use */ 221 val |= 1 << 3; /* internal use */ 222 val |= 1 << 2; /* internal use */ 223 val |= 1 << 0; /* remove VLAN tags on output */ 224 MIIBUS_WRITEREG(sc->mii_dev, 3, 22, val); 225 226 /* Port 4 (system port) Control Register 0 */ 227 val = 0; 228 val |= 1 << 15; /* reserved */ 229 val |= 0 << 11; /* don't drop received packets with wrong VLAN tag */ 230 val |= 1 << 10; /* disable 802.1p priority classification */ 231 val |= 1 << 9; /* disable diffserv priority classification */ 232 val |= 1 << 6; /* internal use */ 233 val |= 3 << 4; /* internal use */ 234 val |= 1 << 3; /* internal use */ 235 val |= 1 << 2; /* internal use */ 236 val |= 2 << 0; /* add VLAN tags for untagged packets on output */ 237 MIIBUS_WRITEREG(sc->mii_dev, 4, 22, val); 238 239 /* Port 0 Control Register 1 and VLAN A */ 240 val = 0; 241 val |= 0x0 << 12; /* Port 0 VLAN Index */ 242 val |= 1 << 11; /* internal use */ 243 val |= 1 << 10; /* internal use */ 244 val |= 1 << 9; /* internal use */ 245 val |= 1 << 7; /* internal use */ 246 val |= 1 << 6; /* internal use */ 247 val |= 0x11 << 0; /* VLAN A membership */ 248 MIIBUS_WRITEREG(sc->mii_dev, 0, 24, val); 249 250 /* Port 0 Control Register 2 and VLAN A */ 251 val = 0; 252 val |= 1 << 15; /* internal use */ 253 val |= 1 << 14; /* internal use */ 254 val |= 1 << 13; /* internal use */ 255 val |= 1 << 12; /* internal use */ 256 val |= 0x100 << 0; /* VLAN A ID */ 257 MIIBUS_WRITEREG(sc->mii_dev, 0, 25, val); 258 259 /* Port 1 Control Register 1 and VLAN B */ 260 val = 0; 261 val |= 0x1 << 12; /* Port 1 VLAN Index */ 262 val |= 1 << 11; /* internal use */ 263 val |= 1 << 10; /* internal use */ 264 val |= 1 << 9; /* internal use */ 265 val |= 1 << 7; /* internal use */ 266 val |= 1 << 6; /* internal use */ 267 val |= 0x12 << 0; /* VLAN B membership */ 268 MIIBUS_WRITEREG(sc->mii_dev, 1, 24, val); 269 270 /* Port 1 Control Register 2 and VLAN B */ 271 val = 0; 272 val |= 1 << 15; /* internal use */ 273 val |= 1 << 14; /* internal use */ 274 val |= 1 << 13; /* internal use */ 275 val |= 1 << 12; /* internal use */ 276 val |= 0x101 << 0; /* VLAN B ID */ 277 MIIBUS_WRITEREG(sc->mii_dev, 1, 25, val); 278 279 /* Port 2 Control Register 1 and VLAN C */ 280 val = 0; 281 val |= 0x2 << 12; /* Port 2 VLAN Index */ 282 val |= 1 << 11; /* internal use */ 283 val |= 1 << 10; /* internal use */ 284 val |= 1 << 9; /* internal use */ 285 val |= 1 << 7; /* internal use */ 286 val |= 1 << 6; /* internal use */ 287 val |= 0x14 << 0; /* VLAN C membership */ 288 MIIBUS_WRITEREG(sc->mii_dev, 2, 24, val); 289 290 /* Port 2 Control Register 2 and VLAN C */ 291 val = 0; 292 val |= 1 << 15; /* internal use */ 293 val |= 1 << 14; /* internal use */ 294 val |= 1 << 13; /* internal use */ 295 val |= 1 << 12; /* internal use */ 296 val |= 0x102 << 0; /* VLAN C ID */ 297 MIIBUS_WRITEREG(sc->mii_dev, 2, 25, val); 298 299 /* Port 3 Control Register 1 and VLAN D */ 300 val = 0; 301 val |= 0x3 << 12; /* Port 3 VLAN Index */ 302 val |= 1 << 11; /* internal use */ 303 val |= 1 << 10; /* internal use */ 304 val |= 1 << 9; /* internal use */ 305 val |= 1 << 7; /* internal use */ 306 val |= 1 << 6; /* internal use */ 307 val |= 0x18 << 0; /* VLAN D membership */ 308 MIIBUS_WRITEREG(sc->mii_dev, 3, 24, val); 309 310 /* Port 3 Control Register 2 and VLAN D */ 311 val = 0; 312 val |= 1 << 15; /* internal use */ 313 val |= 1 << 14; /* internal use */ 314 val |= 1 << 13; /* internal use */ 315 val |= 1 << 12; /* internal use */ 316 val |= 0x103 << 0; /* VLAN D ID */ 317 MIIBUS_WRITEREG(sc->mii_dev, 3, 25, val); 318 319 /* Port 4 Control Register 1 and VLAN E */ 320 val = 0; 321 val |= 0x0 << 12; /* Port 4 VLAN Index */ 322 val |= 1 << 11; /* internal use */ 323 val |= 1 << 10; /* internal use */ 324 val |= 1 << 9; /* internal use */ 325 val |= 1 << 7; /* internal use */ 326 val |= 1 << 6; /* internal use */ 327 val |= 0 << 0; /* VLAN E membership */ 328 MIIBUS_WRITEREG(sc->mii_dev, 4, 24, val); 329 330 /* Port 4 Control Register 2 and VLAN E */ 331 val = 0; 332 val |= 1 << 15; /* internal use */ 333 val |= 1 << 14; /* internal use */ 334 val |= 1 << 13; /* internal use */ 335 val |= 1 << 12; /* internal use */ 336 val |= 0x104 << 0; /* VLAN E ID */ 337 MIIBUS_WRITEREG(sc->mii_dev, 4, 25, val); 338 #endif 339 340 #ifdef RL_DEBUG 341 rlswitch_phydump(dev); 342 #endif 343 MIIBUS_MEDIAINIT(sc->mii_dev); 344 return (0); 345 } 346 347 static int 348 rlswitch_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 349 { 350 351 switch (cmd) { 352 case MII_POLLSTAT: 353 break; 354 355 case MII_MEDIACHG: 356 break; 357 358 case MII_TICK: 359 break; 360 } 361 362 /* Update the media status. */ 363 PHY_STATUS(sc); 364 365 /* Callback if something changed. */ 366 // mii_phy_update(sc, cmd); 367 return (0); 368 } 369 370 static void 371 rlswitch_status(struct mii_softc *phy) 372 { 373 struct mii_data *mii = phy->mii_pdata; 374 375 mii->mii_media_status = IFM_AVALID; 376 mii->mii_media_active = IFM_ETHER; 377 mii->mii_media_status |= IFM_ACTIVE; 378 mii->mii_media_active |= 379 IFM_100_TX | IFM_FDX | mii_phy_flowstatus(phy); 380 } 381 382 #ifdef RL_DEBUG 383 static void 384 rlswitch_phydump(device_t dev) { 385 int phy, reg, val; 386 struct mii_softc *sc; 387 388 sc = device_get_softc(dev); 389 device_printf(dev, "rlswitchphydump\n"); 390 for (phy = 0; phy <= 5; phy++) { 391 printf("PHY%i:", phy); 392 for (reg = 0; reg <= 31; reg++) { 393 val = MIIBUS_READREG(sc->mii_dev, phy, reg); 394 printf(" 0x%x", val); 395 } 396 printf("\n"); 397 } 398 } 399 #endif 400