1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/taskqueue.h> 46 #include <sys/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include "miibus_if.h" 60 61 #include <machine/bus.h> 62 #include <dev/rl/if_rlreg.h> 63 64 static int rgephy_probe(device_t); 65 static int rgephy_attach(device_t); 66 67 static device_method_t rgephy_methods[] = { 68 /* device interface */ 69 DEVMETHOD(device_probe, rgephy_probe), 70 DEVMETHOD(device_attach, rgephy_attach), 71 DEVMETHOD(device_detach, mii_phy_detach), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 DEVMETHOD_END 74 }; 75 76 static devclass_t rgephy_devclass; 77 78 static driver_t rgephy_driver = { 79 "rgephy", 80 rgephy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 85 86 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 87 static void rgephy_status(struct mii_softc *); 88 static int rgephy_mii_phy_auto(struct mii_softc *, int); 89 static void rgephy_reset(struct mii_softc *); 90 static void rgephy_loop(struct mii_softc *); 91 static void rgephy_load_dspcode(struct mii_softc *); 92 93 static const struct mii_phydesc rgephys[] = { 94 MII_PHY_DESC(REALTEK, RTL8169S), 95 MII_PHY_DESC(REALTEK, RTL8251), 96 MII_PHY_END 97 }; 98 99 static const struct mii_phy_funcs rgephy_funcs = { 100 rgephy_service, 101 rgephy_status, 102 rgephy_reset 103 }; 104 105 static int 106 rgephy_probe(device_t dev) 107 { 108 109 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 110 } 111 112 static int 113 rgephy_attach(device_t dev) 114 { 115 struct mii_softc *sc; 116 u_int flags; 117 118 sc = device_get_softc(dev); 119 flags = 0; 120 if (mii_dev_mac_match(dev, "re")) 121 flags |= MIIF_PHYPRIV0; 122 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 123 124 /* RTL8169S do not report auto-sense; add manually. */ 125 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 126 sc->mii_capmask; 127 if (sc->mii_capabilities & BMSR_EXTSTAT) 128 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 129 device_printf(dev, " "); 130 mii_phy_add_media(sc); 131 printf("\n"); 132 /* 133 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 134 * manual configuration, which is used to work around issues with 135 * certain setups by default, should not be triggered as it may in 136 * turn cause harm in some edge cases. 137 */ 138 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 139 140 PHY_RESET(sc); 141 142 MIIBUS_MEDIAINIT(sc->mii_dev); 143 return (0); 144 } 145 146 static int 147 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 148 { 149 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 150 int reg, speed, gig, anar; 151 152 switch (cmd) { 153 case MII_POLLSTAT: 154 break; 155 156 case MII_MEDIACHG: 157 PHY_RESET(sc); /* XXX hardware bug work-around */ 158 159 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 160 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 161 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 162 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 163 164 switch (IFM_SUBTYPE(ife->ifm_media)) { 165 case IFM_AUTO: 166 #ifdef foo 167 /* 168 * If we're already in auto mode, just return. 169 */ 170 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 171 return (0); 172 #endif 173 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 174 break; 175 case IFM_1000_T: 176 speed = RGEPHY_S1000; 177 goto setit; 178 case IFM_100_TX: 179 speed = RGEPHY_S100; 180 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 181 goto setit; 182 case IFM_10_T: 183 speed = RGEPHY_S10; 184 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 185 setit: 186 if ((ife->ifm_media & IFM_FLOW) != 0 && 187 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 188 return (EINVAL); 189 190 if ((ife->ifm_media & IFM_FDX) != 0) { 191 speed |= RGEPHY_BMCR_FDX; 192 gig = RGEPHY_1000CTL_AFD; 193 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 194 if ((ife->ifm_media & IFM_FLOW) != 0 || 195 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 196 anar |= 197 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 198 } else { 199 gig = RGEPHY_1000CTL_AHD; 200 anar &= 201 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 202 } 203 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 204 gig |= RGEPHY_1000CTL_MSE; 205 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 206 gig |= RGEPHY_1000CTL_MSC; 207 } else { 208 gig = 0; 209 anar &= ~RGEPHY_ANAR_ASP; 210 } 211 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 212 speed |= 213 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 214 rgephy_loop(sc); 215 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 216 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 217 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 218 break; 219 case IFM_NONE: 220 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 221 break; 222 default: 223 return (EINVAL); 224 } 225 break; 226 227 case MII_TICK: 228 /* 229 * Only used for autonegotiation. 230 */ 231 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 232 sc->mii_ticks = 0; 233 break; 234 } 235 236 /* 237 * Check to see if we have link. If we do, we don't 238 * need to restart the autonegotiation process. 239 */ 240 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 241 sc->mii_mpd_rev >= 2) { 242 /* RTL8211B(L) */ 243 reg = PHY_READ(sc, RGEPHY_MII_SSR); 244 if (reg & RGEPHY_SSR_LINK) { 245 sc->mii_ticks = 0; 246 break; 247 } 248 } else { 249 reg = PHY_READ(sc, RL_GMEDIASTAT); 250 if (reg & RL_GMEDIASTAT_LINK) { 251 sc->mii_ticks = 0; 252 break; 253 } 254 } 255 256 /* Announce link loss right after it happens. */ 257 if (sc->mii_ticks++ == 0) 258 break; 259 260 /* Only retry autonegotiation every mii_anegticks seconds. */ 261 if (sc->mii_ticks <= sc->mii_anegticks) 262 return (0); 263 264 sc->mii_ticks = 0; 265 rgephy_mii_phy_auto(sc, ife->ifm_media); 266 break; 267 } 268 269 /* Update the media status. */ 270 PHY_STATUS(sc); 271 272 /* 273 * Callback if something changed. Note that we need to poke 274 * the DSP on the RealTek PHYs if the media changes. 275 * 276 */ 277 if (sc->mii_media_active != mii->mii_media_active || 278 sc->mii_media_status != mii->mii_media_status || 279 cmd == MII_MEDIACHG) { 280 rgephy_load_dspcode(sc); 281 } 282 mii_phy_update(sc, cmd); 283 return (0); 284 } 285 286 static void 287 rgephy_status(struct mii_softc *sc) 288 { 289 struct mii_data *mii = sc->mii_pdata; 290 int bmsr, bmcr; 291 uint16_t ssr; 292 293 mii->mii_media_status = IFM_AVALID; 294 mii->mii_media_active = IFM_ETHER; 295 296 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 297 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 298 if (ssr & RGEPHY_SSR_LINK) 299 mii->mii_media_status |= IFM_ACTIVE; 300 } else { 301 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 302 if (bmsr & RL_GMEDIASTAT_LINK) 303 mii->mii_media_status |= IFM_ACTIVE; 304 } 305 306 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 307 308 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 309 if (bmcr & RGEPHY_BMCR_ISO) { 310 mii->mii_media_active |= IFM_NONE; 311 mii->mii_media_status = 0; 312 return; 313 } 314 315 if (bmcr & RGEPHY_BMCR_LOOP) 316 mii->mii_media_active |= IFM_LOOP; 317 318 if (bmcr & RGEPHY_BMCR_AUTOEN) { 319 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 320 /* Erg, still trying, I guess... */ 321 mii->mii_media_active |= IFM_NONE; 322 return; 323 } 324 } 325 326 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 327 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 328 switch (ssr & RGEPHY_SSR_SPD_MASK) { 329 case RGEPHY_SSR_S1000: 330 mii->mii_media_active |= IFM_1000_T; 331 break; 332 case RGEPHY_SSR_S100: 333 mii->mii_media_active |= IFM_100_TX; 334 break; 335 case RGEPHY_SSR_S10: 336 mii->mii_media_active |= IFM_10_T; 337 break; 338 default: 339 mii->mii_media_active |= IFM_NONE; 340 break; 341 } 342 if (ssr & RGEPHY_SSR_FDX) 343 mii->mii_media_active |= IFM_FDX; 344 else 345 mii->mii_media_active |= IFM_HDX; 346 } else { 347 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 348 if (bmsr & RL_GMEDIASTAT_1000MBPS) 349 mii->mii_media_active |= IFM_1000_T; 350 else if (bmsr & RL_GMEDIASTAT_100MBPS) 351 mii->mii_media_active |= IFM_100_TX; 352 else if (bmsr & RL_GMEDIASTAT_10MBPS) 353 mii->mii_media_active |= IFM_10_T; 354 else 355 mii->mii_media_active |= IFM_NONE; 356 if (bmsr & RL_GMEDIASTAT_FDX) 357 mii->mii_media_active |= IFM_FDX; 358 else 359 mii->mii_media_active |= IFM_HDX; 360 } 361 362 if ((mii->mii_media_active & IFM_FDX) != 0) 363 mii->mii_media_active |= mii_phy_flowstatus(sc); 364 365 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 366 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 367 mii->mii_media_active |= IFM_ETH_MASTER; 368 } 369 370 static int 371 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 372 { 373 int anar; 374 375 rgephy_loop(sc); 376 PHY_RESET(sc); 377 378 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 379 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 380 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 381 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 382 DELAY(1000); 383 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 384 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 385 DELAY(1000); 386 PHY_WRITE(sc, RGEPHY_MII_BMCR, 387 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 388 DELAY(100); 389 390 return (EJUSTRETURN); 391 } 392 393 static void 394 rgephy_loop(struct mii_softc *sc) 395 { 396 int i; 397 398 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 399 sc->mii_mpd_rev < 2) { 400 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 401 DELAY(1000); 402 } 403 404 for (i = 0; i < 15000; i++) { 405 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 406 #if 0 407 device_printf(sc->mii_dev, "looped %d\n", i); 408 #endif 409 break; 410 } 411 DELAY(10); 412 } 413 } 414 415 #define PHY_SETBIT(x, y, z) \ 416 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 417 #define PHY_CLRBIT(x, y, z) \ 418 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 419 420 /* 421 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 422 * existing revisions of the 8169S/8110S chips need to be tuned in 423 * order to reliably negotiate a 1000Mbps link. This is only needed 424 * for rev 0 and rev 1 of the PHY. Later versions work without 425 * any fixups. 426 */ 427 static void 428 rgephy_load_dspcode(struct mii_softc *sc) 429 { 430 int val; 431 432 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 433 sc->mii_mpd_rev >= 2) 434 return; 435 436 PHY_WRITE(sc, 31, 0x0001); 437 PHY_WRITE(sc, 21, 0x1000); 438 PHY_WRITE(sc, 24, 0x65C7); 439 PHY_CLRBIT(sc, 4, 0x0800); 440 val = PHY_READ(sc, 4) & 0xFFF; 441 PHY_WRITE(sc, 4, val); 442 PHY_WRITE(sc, 3, 0x00A1); 443 PHY_WRITE(sc, 2, 0x0008); 444 PHY_WRITE(sc, 1, 0x1020); 445 PHY_WRITE(sc, 0, 0x1000); 446 PHY_SETBIT(sc, 4, 0x0800); 447 PHY_CLRBIT(sc, 4, 0x0800); 448 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 449 PHY_WRITE(sc, 4, val); 450 PHY_WRITE(sc, 3, 0xFF41); 451 PHY_WRITE(sc, 2, 0xDE60); 452 PHY_WRITE(sc, 1, 0x0140); 453 PHY_WRITE(sc, 0, 0x0077); 454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 455 PHY_WRITE(sc, 4, val); 456 PHY_WRITE(sc, 3, 0xDF01); 457 PHY_WRITE(sc, 2, 0xDF20); 458 PHY_WRITE(sc, 1, 0xFF95); 459 PHY_WRITE(sc, 0, 0xFA00); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xFF41); 463 PHY_WRITE(sc, 2, 0xDE20); 464 PHY_WRITE(sc, 1, 0x0140); 465 PHY_WRITE(sc, 0, 0x00BB); 466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 467 PHY_WRITE(sc, 4, val); 468 PHY_WRITE(sc, 3, 0xDF01); 469 PHY_WRITE(sc, 2, 0xDF20); 470 PHY_WRITE(sc, 1, 0xFF95); 471 PHY_WRITE(sc, 0, 0xBF00); 472 PHY_SETBIT(sc, 4, 0x0800); 473 PHY_CLRBIT(sc, 4, 0x0800); 474 PHY_WRITE(sc, 31, 0x0000); 475 476 DELAY(40); 477 } 478 479 static void 480 rgephy_reset(struct mii_softc *sc) 481 { 482 uint16_t pcr, ssr; 483 484 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { 485 /* RTL8211C(L) */ 486 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 487 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 488 ssr &= ~RGEPHY_SSR_ALDPS; 489 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 490 } 491 } 492 493 if (sc->mii_mpd_rev >= 2) { 494 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 495 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 496 pcr &= ~RGEPHY_PCR_MDI_MASK; 497 pcr |= RGEPHY_PCR_MDIX_AUTO; 498 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 499 } 500 } 501 502 mii_phy_reset(sc); 503 DELAY(1000); 504 rgephy_load_dspcode(sc); 505 } 506