1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/rgephyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 #include <pci/if_rlreg.h> 61 62 static int rgephy_probe(device_t); 63 static int rgephy_attach(device_t); 64 65 static device_method_t rgephy_methods[] = { 66 /* device interface */ 67 DEVMETHOD(device_probe, rgephy_probe), 68 DEVMETHOD(device_attach, rgephy_attach), 69 DEVMETHOD(device_detach, mii_phy_detach), 70 DEVMETHOD(device_shutdown, bus_generic_shutdown), 71 { 0, 0 } 72 }; 73 74 static devclass_t rgephy_devclass; 75 76 static driver_t rgephy_driver = { 77 "rgephy", 78 rgephy_methods, 79 sizeof(struct mii_softc) 80 }; 81 82 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 83 84 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 85 static void rgephy_status(struct mii_softc *); 86 static int rgephy_mii_phy_auto(struct mii_softc *); 87 static void rgephy_reset(struct mii_softc *); 88 static void rgephy_loop(struct mii_softc *); 89 static void rgephy_load_dspcode(struct mii_softc *); 90 91 static const struct mii_phydesc rgephys[] = { 92 MII_PHY_DESC(xxREALTEK, RTL8169S), 93 MII_PHY_END 94 }; 95 96 static int 97 rgephy_probe(device_t dev) 98 { 99 100 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 101 } 102 103 static int 104 rgephy_attach(device_t dev) 105 { 106 struct mii_softc *sc; 107 struct mii_attach_args *ma; 108 struct mii_data *mii; 109 const char *sep = ""; 110 111 sc = device_get_softc(dev); 112 ma = device_get_ivars(dev); 113 sc->mii_dev = device_get_parent(dev); 114 mii = device_get_softc(sc->mii_dev); 115 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 116 117 sc->mii_inst = mii->mii_instance; 118 sc->mii_phy = ma->mii_phyno; 119 sc->mii_service = rgephy_service; 120 sc->mii_pdata = mii; 121 122 mii->mii_instance++; 123 124 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 125 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 126 127 #if 0 128 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 129 BMCR_LOOP|BMCR_S100); 130 #endif 131 132 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 133 sc->mii_capabilities &= ~BMSR_ANEG; 134 if (sc->mii_capabilities & BMSR_EXTSTAT) 135 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 136 137 device_printf(dev, " "); 138 mii_phy_add_media(sc); 139 /* RTL8169S do not report auto-sense; add manually. */ 140 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 141 sep = ", "; 142 PRINT("auto"); 143 printf("\n"); 144 #undef ADD 145 #undef PRINT 146 147 rgephy_reset(sc); 148 MIIBUS_MEDIAINIT(sc->mii_dev); 149 return (0); 150 } 151 152 static int 153 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 154 { 155 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 156 int reg, speed, gig, anar; 157 158 switch (cmd) { 159 case MII_POLLSTAT: 160 /* 161 * If we're not polling our PHY instance, just return. 162 */ 163 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 164 return (0); 165 break; 166 167 case MII_MEDIACHG: 168 /* 169 * If the media indicates a different PHY instance, 170 * isolate ourselves. 171 */ 172 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 173 reg = PHY_READ(sc, MII_BMCR); 174 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 175 return (0); 176 } 177 178 /* 179 * If the interface is not up, don't do anything. 180 */ 181 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 182 break; 183 184 rgephy_reset(sc); /* XXX hardware bug work-around */ 185 186 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 187 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 188 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 189 190 switch (IFM_SUBTYPE(ife->ifm_media)) { 191 case IFM_AUTO: 192 #ifdef foo 193 /* 194 * If we're already in auto mode, just return. 195 */ 196 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 197 return (0); 198 #endif 199 (void) rgephy_mii_phy_auto(sc); 200 break; 201 case IFM_1000_T: 202 speed = RGEPHY_S1000; 203 goto setit; 204 case IFM_100_TX: 205 speed = RGEPHY_S100; 206 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 207 goto setit; 208 case IFM_10_T: 209 speed = RGEPHY_S10; 210 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 211 setit: 212 rgephy_loop(sc); 213 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 214 speed |= RGEPHY_BMCR_FDX; 215 gig = RGEPHY_1000CTL_AFD; 216 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 217 } else { 218 gig = RGEPHY_1000CTL_AHD; 219 anar &= 220 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 221 } 222 223 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 224 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 225 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 226 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 227 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 228 break; 229 } 230 231 /* 232 * When setting the link manually, one side must 233 * be the master and the other the slave. However 234 * ifmedia doesn't give us a good way to specify 235 * this, so we fake it by using one of the LINK 236 * flags. If LINK0 is set, we program the PHY to 237 * be a master, otherwise it's a slave. 238 */ 239 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 240 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 241 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 242 } else { 243 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 244 gig|RGEPHY_1000CTL_MSE); 245 } 246 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 247 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 248 break; 249 case IFM_NONE: 250 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 251 break; 252 case IFM_100_T4: 253 default: 254 return (EINVAL); 255 } 256 break; 257 258 case MII_TICK: 259 /* 260 * If we're not currently selected, just return. 261 */ 262 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 263 return (0); 264 265 /* 266 * Is the interface even up? 267 */ 268 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 269 return (0); 270 271 /* 272 * Only used for autonegotiation. 273 */ 274 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 275 break; 276 277 /* 278 * Check to see if we have link. If we do, we don't 279 * need to restart the autonegotiation process. Read 280 * the BMSR twice in case it's latched. 281 */ 282 reg = PHY_READ(sc, RL_GMEDIASTAT); 283 if (reg & RL_GMEDIASTAT_LINK) 284 break; 285 286 /* 287 * Only retry autonegotiation every 5 seconds. 288 */ 289 if (++sc->mii_ticks <= MII_ANEGTICKS) 290 break; 291 292 sc->mii_ticks = 0; 293 rgephy_mii_phy_auto(sc); 294 return (0); 295 } 296 297 /* Update the media status. */ 298 rgephy_status(sc); 299 300 /* 301 * Callback if something changed. Note that we need to poke 302 * the DSP on the RealTek PHYs if the media changes. 303 * 304 */ 305 if (sc->mii_media_active != mii->mii_media_active || 306 sc->mii_media_status != mii->mii_media_status || 307 cmd == MII_MEDIACHG) { 308 rgephy_load_dspcode(sc); 309 } 310 mii_phy_update(sc, cmd); 311 return (0); 312 } 313 314 static void 315 rgephy_status(struct mii_softc *sc) 316 { 317 struct mii_data *mii = sc->mii_pdata; 318 int bmsr, bmcr; 319 320 mii->mii_media_status = IFM_AVALID; 321 mii->mii_media_active = IFM_ETHER; 322 323 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 324 325 if (bmsr & RL_GMEDIASTAT_LINK) 326 mii->mii_media_status |= IFM_ACTIVE; 327 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 328 329 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 330 331 if (bmcr & RGEPHY_BMCR_LOOP) 332 mii->mii_media_active |= IFM_LOOP; 333 334 if (bmcr & RGEPHY_BMCR_AUTOEN) { 335 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 336 /* Erg, still trying, I guess... */ 337 mii->mii_media_active |= IFM_NONE; 338 return; 339 } 340 } 341 342 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 343 if (bmsr & RL_GMEDIASTAT_1000MBPS) 344 mii->mii_media_active |= IFM_1000_T; 345 else if (bmsr & RL_GMEDIASTAT_100MBPS) 346 mii->mii_media_active |= IFM_100_TX; 347 else if (bmsr & RL_GMEDIASTAT_10MBPS) 348 mii->mii_media_active |= IFM_10_T; 349 else 350 mii->mii_media_active |= IFM_NONE; 351 if (bmsr & RL_GMEDIASTAT_FDX) 352 mii->mii_media_active |= IFM_FDX; 353 } 354 355 static int 356 rgephy_mii_phy_auto(struct mii_softc *mii) 357 { 358 359 rgephy_loop(mii); 360 rgephy_reset(mii); 361 362 PHY_WRITE(mii, RGEPHY_MII_ANAR, 363 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 364 DELAY(1000); 365 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 366 RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD); 367 DELAY(1000); 368 PHY_WRITE(mii, RGEPHY_MII_BMCR, 369 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 370 DELAY(100); 371 372 return (EJUSTRETURN); 373 } 374 375 static void 376 rgephy_loop(struct mii_softc *sc) 377 { 378 int i; 379 380 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 381 DELAY(1000); 382 383 for (i = 0; i < 15000; i++) { 384 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 385 #if 0 386 device_printf(sc->mii_dev, "looped %d\n", i); 387 #endif 388 break; 389 } 390 DELAY(10); 391 } 392 } 393 394 #define PHY_SETBIT(x, y, z) \ 395 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 396 #define PHY_CLRBIT(x, y, z) \ 397 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 398 399 /* 400 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 401 * existing revisions of the 8169S/8110S chips need to be tuned in 402 * order to reliably negotiate a 1000Mbps link. This is only needed 403 * for rev 0 and rev 1 of the PHY. Later versions work without 404 * any fixups. 405 */ 406 static void 407 rgephy_load_dspcode(struct mii_softc *sc) 408 { 409 int val; 410 uint16_t id2; 411 412 id2 = PHY_READ(sc, MII_PHYIDR2); 413 414 if (MII_REV(id2) > 1) 415 return; 416 417 PHY_WRITE(sc, 31, 0x0001); 418 PHY_WRITE(sc, 21, 0x1000); 419 PHY_WRITE(sc, 24, 0x65C7); 420 PHY_CLRBIT(sc, 4, 0x0800); 421 val = PHY_READ(sc, 4) & 0xFFF; 422 PHY_WRITE(sc, 4, val); 423 PHY_WRITE(sc, 3, 0x00A1); 424 PHY_WRITE(sc, 2, 0x0008); 425 PHY_WRITE(sc, 1, 0x1020); 426 PHY_WRITE(sc, 0, 0x1000); 427 PHY_SETBIT(sc, 4, 0x0800); 428 PHY_CLRBIT(sc, 4, 0x0800); 429 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 430 PHY_WRITE(sc, 4, val); 431 PHY_WRITE(sc, 3, 0xFF41); 432 PHY_WRITE(sc, 2, 0xDE60); 433 PHY_WRITE(sc, 1, 0x0140); 434 PHY_WRITE(sc, 0, 0x0077); 435 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 436 PHY_WRITE(sc, 4, val); 437 PHY_WRITE(sc, 3, 0xDF01); 438 PHY_WRITE(sc, 2, 0xDF20); 439 PHY_WRITE(sc, 1, 0xFF95); 440 PHY_WRITE(sc, 0, 0xFA00); 441 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 442 PHY_WRITE(sc, 4, val); 443 PHY_WRITE(sc, 3, 0xFF41); 444 PHY_WRITE(sc, 2, 0xDE20); 445 PHY_WRITE(sc, 1, 0x0140); 446 PHY_WRITE(sc, 0, 0x00BB); 447 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 448 PHY_WRITE(sc, 4, val); 449 PHY_WRITE(sc, 3, 0xDF01); 450 PHY_WRITE(sc, 2, 0xDF20); 451 PHY_WRITE(sc, 1, 0xFF95); 452 PHY_WRITE(sc, 0, 0xBF00); 453 PHY_SETBIT(sc, 4, 0x0800); 454 PHY_CLRBIT(sc, 4, 0x0800); 455 PHY_WRITE(sc, 31, 0x0000); 456 457 DELAY(40); 458 } 459 460 static void 461 rgephy_reset(struct mii_softc *sc) 462 { 463 464 mii_phy_reset(sc); 465 DELAY(1000); 466 rgephy_load_dspcode(sc); 467 } 468