1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/rgephyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 #include <pci/if_rlreg.h> 61 62 static int rgephy_probe(device_t); 63 static int rgephy_attach(device_t); 64 65 static device_method_t rgephy_methods[] = { 66 /* device interface */ 67 DEVMETHOD(device_probe, rgephy_probe), 68 DEVMETHOD(device_attach, rgephy_attach), 69 DEVMETHOD(device_detach, mii_phy_detach), 70 DEVMETHOD(device_shutdown, bus_generic_shutdown), 71 DEVMETHOD_END 72 }; 73 74 static devclass_t rgephy_devclass; 75 76 static driver_t rgephy_driver = { 77 "rgephy", 78 rgephy_methods, 79 sizeof(struct mii_softc) 80 }; 81 82 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 83 84 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 85 static void rgephy_status(struct mii_softc *); 86 static int rgephy_mii_phy_auto(struct mii_softc *, int); 87 static void rgephy_reset(struct mii_softc *); 88 static void rgephy_loop(struct mii_softc *); 89 static void rgephy_load_dspcode(struct mii_softc *); 90 91 static const struct mii_phydesc rgephys[] = { 92 MII_PHY_DESC(REALTEK, RTL8169S), 93 MII_PHY_END 94 }; 95 96 static const struct mii_phy_funcs rgephy_funcs = { 97 rgephy_service, 98 rgephy_status, 99 rgephy_reset 100 }; 101 102 static int 103 rgephy_probe(device_t dev) 104 { 105 106 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct mii_softc *sc; 113 struct mii_attach_args *ma; 114 u_int flags; 115 116 sc = device_get_softc(dev); 117 ma = device_get_ivars(dev); 118 flags = 0; 119 if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0) 120 flags |= MIIF_PHYPRIV0; 121 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 122 123 /* RTL8169S do not report auto-sense; add manually. */ 124 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 125 sc->mii_capmask; 126 if (sc->mii_capabilities & BMSR_EXTSTAT) 127 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 128 device_printf(dev, " "); 129 mii_phy_add_media(sc); 130 printf("\n"); 131 /* 132 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 133 * manual configuration, which is used to work around issues with 134 * certain setups by default, should not be triggered as it may in 135 * turn cause harm in some edge cases. 136 */ 137 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 138 139 PHY_RESET(sc); 140 141 MIIBUS_MEDIAINIT(sc->mii_dev); 142 return (0); 143 } 144 145 static int 146 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 147 { 148 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 149 int reg, speed, gig, anar; 150 151 switch (cmd) { 152 case MII_POLLSTAT: 153 break; 154 155 case MII_MEDIACHG: 156 /* 157 * If the interface is not up, don't do anything. 158 */ 159 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 160 break; 161 162 PHY_RESET(sc); /* XXX hardware bug work-around */ 163 164 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 165 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 166 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 167 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 168 169 switch (IFM_SUBTYPE(ife->ifm_media)) { 170 case IFM_AUTO: 171 #ifdef foo 172 /* 173 * If we're already in auto mode, just return. 174 */ 175 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 176 return (0); 177 #endif 178 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 179 break; 180 case IFM_1000_T: 181 speed = RGEPHY_S1000; 182 goto setit; 183 case IFM_100_TX: 184 speed = RGEPHY_S100; 185 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 186 goto setit; 187 case IFM_10_T: 188 speed = RGEPHY_S10; 189 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 190 setit: 191 if ((ife->ifm_media & IFM_FLOW) != 0 && 192 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 193 return (EINVAL); 194 195 if ((ife->ifm_media & IFM_FDX) != 0) { 196 speed |= RGEPHY_BMCR_FDX; 197 gig = RGEPHY_1000CTL_AFD; 198 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 199 if ((ife->ifm_media & IFM_FLOW) != 0 || 200 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 201 anar |= 202 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 203 } else { 204 gig = RGEPHY_1000CTL_AHD; 205 anar &= 206 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 207 } 208 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 209 gig |= RGEPHY_1000CTL_MSE; 210 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 211 gig |= RGEPHY_1000CTL_MSC; 212 } else { 213 gig = 0; 214 anar &= ~RGEPHY_ANAR_ASP; 215 } 216 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 217 speed |= 218 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 219 rgephy_loop(sc); 220 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 221 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 222 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 223 break; 224 case IFM_NONE: 225 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 226 break; 227 default: 228 return (EINVAL); 229 } 230 break; 231 232 case MII_TICK: 233 /* 234 * Is the interface even up? 235 */ 236 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 237 return (0); 238 239 /* 240 * Only used for autonegotiation. 241 */ 242 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 243 sc->mii_ticks = 0; 244 break; 245 } 246 247 /* 248 * Check to see if we have link. If we do, we don't 249 * need to restart the autonegotiation process. 250 */ 251 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 252 sc->mii_mpd_rev >= 2) { 253 /* RTL8211B(L) */ 254 reg = PHY_READ(sc, RGEPHY_MII_SSR); 255 if (reg & RGEPHY_SSR_LINK) { 256 sc->mii_ticks = 0; 257 break; 258 } 259 } else { 260 reg = PHY_READ(sc, RL_GMEDIASTAT); 261 if (reg & RL_GMEDIASTAT_LINK) { 262 sc->mii_ticks = 0; 263 break; 264 } 265 } 266 267 /* Announce link loss right after it happens. */ 268 if (sc->mii_ticks++ == 0) 269 break; 270 271 /* Only retry autonegotiation every mii_anegticks seconds. */ 272 if (sc->mii_ticks <= sc->mii_anegticks) 273 return (0); 274 275 sc->mii_ticks = 0; 276 rgephy_mii_phy_auto(sc, ife->ifm_media); 277 break; 278 } 279 280 /* Update the media status. */ 281 PHY_STATUS(sc); 282 283 /* 284 * Callback if something changed. Note that we need to poke 285 * the DSP on the RealTek PHYs if the media changes. 286 * 287 */ 288 if (sc->mii_media_active != mii->mii_media_active || 289 sc->mii_media_status != mii->mii_media_status || 290 cmd == MII_MEDIACHG) { 291 rgephy_load_dspcode(sc); 292 } 293 mii_phy_update(sc, cmd); 294 return (0); 295 } 296 297 static void 298 rgephy_status(struct mii_softc *sc) 299 { 300 struct mii_data *mii = sc->mii_pdata; 301 int bmsr, bmcr; 302 uint16_t ssr; 303 304 mii->mii_media_status = IFM_AVALID; 305 mii->mii_media_active = IFM_ETHER; 306 307 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 308 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 309 if (ssr & RGEPHY_SSR_LINK) 310 mii->mii_media_status |= IFM_ACTIVE; 311 } else { 312 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 313 if (bmsr & RL_GMEDIASTAT_LINK) 314 mii->mii_media_status |= IFM_ACTIVE; 315 } 316 317 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 318 319 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 320 if (bmcr & RGEPHY_BMCR_ISO) { 321 mii->mii_media_active |= IFM_NONE; 322 mii->mii_media_status = 0; 323 return; 324 } 325 326 if (bmcr & RGEPHY_BMCR_LOOP) 327 mii->mii_media_active |= IFM_LOOP; 328 329 if (bmcr & RGEPHY_BMCR_AUTOEN) { 330 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 331 /* Erg, still trying, I guess... */ 332 mii->mii_media_active |= IFM_NONE; 333 return; 334 } 335 } 336 337 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 338 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 339 switch (ssr & RGEPHY_SSR_SPD_MASK) { 340 case RGEPHY_SSR_S1000: 341 mii->mii_media_active |= IFM_1000_T; 342 break; 343 case RGEPHY_SSR_S100: 344 mii->mii_media_active |= IFM_100_TX; 345 break; 346 case RGEPHY_SSR_S10: 347 mii->mii_media_active |= IFM_10_T; 348 break; 349 default: 350 mii->mii_media_active |= IFM_NONE; 351 break; 352 } 353 if (ssr & RGEPHY_SSR_FDX) 354 mii->mii_media_active |= IFM_FDX; 355 else 356 mii->mii_media_active |= IFM_HDX; 357 } else { 358 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 359 if (bmsr & RL_GMEDIASTAT_1000MBPS) 360 mii->mii_media_active |= IFM_1000_T; 361 else if (bmsr & RL_GMEDIASTAT_100MBPS) 362 mii->mii_media_active |= IFM_100_TX; 363 else if (bmsr & RL_GMEDIASTAT_10MBPS) 364 mii->mii_media_active |= IFM_10_T; 365 else 366 mii->mii_media_active |= IFM_NONE; 367 if (bmsr & RL_GMEDIASTAT_FDX) 368 mii->mii_media_active |= IFM_FDX; 369 else 370 mii->mii_media_active |= IFM_HDX; 371 } 372 373 if ((mii->mii_media_active & IFM_FDX) != 0) 374 mii->mii_media_active |= mii_phy_flowstatus(sc); 375 376 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 377 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 378 mii->mii_media_active |= IFM_ETH_MASTER; 379 } 380 381 static int 382 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 383 { 384 int anar; 385 386 rgephy_loop(sc); 387 PHY_RESET(sc); 388 389 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 390 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 391 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 392 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 393 DELAY(1000); 394 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 395 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 396 DELAY(1000); 397 PHY_WRITE(sc, RGEPHY_MII_BMCR, 398 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 399 DELAY(100); 400 401 return (EJUSTRETURN); 402 } 403 404 static void 405 rgephy_loop(struct mii_softc *sc) 406 { 407 int i; 408 409 if (sc->mii_mpd_rev < 2) { 410 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 411 DELAY(1000); 412 } 413 414 for (i = 0; i < 15000; i++) { 415 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 416 #if 0 417 device_printf(sc->mii_dev, "looped %d\n", i); 418 #endif 419 break; 420 } 421 DELAY(10); 422 } 423 } 424 425 #define PHY_SETBIT(x, y, z) \ 426 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 427 #define PHY_CLRBIT(x, y, z) \ 428 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 429 430 /* 431 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 432 * existing revisions of the 8169S/8110S chips need to be tuned in 433 * order to reliably negotiate a 1000Mbps link. This is only needed 434 * for rev 0 and rev 1 of the PHY. Later versions work without 435 * any fixups. 436 */ 437 static void 438 rgephy_load_dspcode(struct mii_softc *sc) 439 { 440 int val; 441 442 if (sc->mii_mpd_rev >= 2) 443 return; 444 445 PHY_WRITE(sc, 31, 0x0001); 446 PHY_WRITE(sc, 21, 0x1000); 447 PHY_WRITE(sc, 24, 0x65C7); 448 PHY_CLRBIT(sc, 4, 0x0800); 449 val = PHY_READ(sc, 4) & 0xFFF; 450 PHY_WRITE(sc, 4, val); 451 PHY_WRITE(sc, 3, 0x00A1); 452 PHY_WRITE(sc, 2, 0x0008); 453 PHY_WRITE(sc, 1, 0x1020); 454 PHY_WRITE(sc, 0, 0x1000); 455 PHY_SETBIT(sc, 4, 0x0800); 456 PHY_CLRBIT(sc, 4, 0x0800); 457 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 458 PHY_WRITE(sc, 4, val); 459 PHY_WRITE(sc, 3, 0xFF41); 460 PHY_WRITE(sc, 2, 0xDE60); 461 PHY_WRITE(sc, 1, 0x0140); 462 PHY_WRITE(sc, 0, 0x0077); 463 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 464 PHY_WRITE(sc, 4, val); 465 PHY_WRITE(sc, 3, 0xDF01); 466 PHY_WRITE(sc, 2, 0xDF20); 467 PHY_WRITE(sc, 1, 0xFF95); 468 PHY_WRITE(sc, 0, 0xFA00); 469 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 470 PHY_WRITE(sc, 4, val); 471 PHY_WRITE(sc, 3, 0xFF41); 472 PHY_WRITE(sc, 2, 0xDE20); 473 PHY_WRITE(sc, 1, 0x0140); 474 PHY_WRITE(sc, 0, 0x00BB); 475 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 476 PHY_WRITE(sc, 4, val); 477 PHY_WRITE(sc, 3, 0xDF01); 478 PHY_WRITE(sc, 2, 0xDF20); 479 PHY_WRITE(sc, 1, 0xFF95); 480 PHY_WRITE(sc, 0, 0xBF00); 481 PHY_SETBIT(sc, 4, 0x0800); 482 PHY_CLRBIT(sc, 4, 0x0800); 483 PHY_WRITE(sc, 31, 0x0000); 484 485 DELAY(40); 486 } 487 488 static void 489 rgephy_reset(struct mii_softc *sc) 490 { 491 uint16_t pcr, ssr; 492 493 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { 494 /* RTL8211C(L) */ 495 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 496 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 497 ssr &= ~RGEPHY_SSR_ALDPS; 498 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 499 } 500 } 501 502 if (sc->mii_mpd_rev >= 2) { 503 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 504 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 505 pcr &= ~RGEPHY_PCR_MDI_MASK; 506 pcr |= RGEPHY_PCR_MDIX_AUTO; 507 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 508 } 509 } 510 511 mii_phy_reset(sc); 512 DELAY(1000); 513 rgephy_load_dspcode(sc); 514 } 515