1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include "miibus_if.h" 59 60 #include <machine/bus.h> 61 #include <pci/if_rlreg.h> 62 63 static int rgephy_probe(device_t); 64 static int rgephy_attach(device_t); 65 66 static device_method_t rgephy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, rgephy_probe), 69 DEVMETHOD(device_attach, rgephy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t rgephy_devclass; 76 77 static driver_t rgephy_driver = { 78 "rgephy", 79 rgephy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 84 85 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 86 static void rgephy_status(struct mii_softc *); 87 static int rgephy_mii_phy_auto(struct mii_softc *); 88 static void rgephy_reset(struct mii_softc *); 89 static void rgephy_loop(struct mii_softc *); 90 static void rgephy_load_dspcode(struct mii_softc *); 91 static int rgephy_mii_model; 92 93 static int 94 rgephy_probe(device_t dev) 95 { 96 struct mii_attach_args *ma; 97 98 ma = device_get_ivars(dev); 99 100 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK && 101 MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) { 102 device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S); 103 return(BUS_PROBE_DEFAULT); 104 } 105 106 return(ENXIO); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct mii_softc *sc; 113 struct mii_attach_args *ma; 114 struct mii_data *mii; 115 const char *sep = ""; 116 117 sc = device_get_softc(dev); 118 ma = device_get_ivars(dev); 119 sc->mii_dev = device_get_parent(dev); 120 mii = device_get_softc(sc->mii_dev); 121 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 122 123 sc->mii_inst = mii->mii_instance; 124 sc->mii_phy = ma->mii_phyno; 125 sc->mii_service = rgephy_service; 126 sc->mii_pdata = mii; 127 128 sc->mii_flags |= MIIF_NOISOLATE; 129 mii->mii_instance++; 130 131 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 132 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 133 134 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 135 BMCR_ISO); 136 #if 0 137 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 138 BMCR_LOOP|BMCR_S100); 139 #endif 140 141 rgephy_mii_model = MII_MODEL(ma->mii_id2); 142 143 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 144 sc->mii_capabilities &= ~BMSR_ANEG; 145 146 device_printf(dev, " "); 147 mii_add_media(sc); 148 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 149 RGEPHY_BMCR_FDX); 150 PRINT(", 1000baseTX"); 151 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 152 PRINT("1000baseTX-FDX"); 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 154 PRINT("auto"); 155 156 printf("\n"); 157 #undef ADD 158 #undef PRINT 159 160 rgephy_reset(sc); 161 MIIBUS_MEDIAINIT(sc->mii_dev); 162 return(0); 163 } 164 165 static int 166 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 167 { 168 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 169 int reg, speed, gig; 170 171 switch (cmd) { 172 case MII_POLLSTAT: 173 /* 174 * If we're not polling our PHY instance, just return. 175 */ 176 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 177 return (0); 178 break; 179 180 case MII_MEDIACHG: 181 /* 182 * If the media indicates a different PHY instance, 183 * isolate ourselves. 184 */ 185 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 186 reg = PHY_READ(sc, MII_BMCR); 187 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 188 return (0); 189 } 190 191 /* 192 * If the interface is not up, don't do anything. 193 */ 194 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 195 break; 196 197 rgephy_reset(sc); /* XXX hardware bug work-around */ 198 199 switch (IFM_SUBTYPE(ife->ifm_media)) { 200 case IFM_AUTO: 201 #ifdef foo 202 /* 203 * If we're already in auto mode, just return. 204 */ 205 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 206 return (0); 207 #endif 208 (void) rgephy_mii_phy_auto(sc); 209 break; 210 case IFM_1000_T: 211 speed = RGEPHY_S1000; 212 goto setit; 213 case IFM_100_TX: 214 speed = RGEPHY_S100; 215 goto setit; 216 case IFM_10_T: 217 speed = RGEPHY_S10; 218 setit: 219 rgephy_loop(sc); 220 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 221 speed |= RGEPHY_BMCR_FDX; 222 gig = RGEPHY_1000CTL_AFD; 223 } else { 224 gig = RGEPHY_1000CTL_AHD; 225 } 226 227 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 228 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 229 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 230 231 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 232 break; 233 234 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 235 PHY_WRITE(sc, RGEPHY_MII_BMCR, 236 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 237 238 /* 239 * When settning the link manually, one side must 240 * be the master and the other the slave. However 241 * ifmedia doesn't give us a good way to specify 242 * this, so we fake it by using one of the LINK 243 * flags. If LINK0 is set, we program the PHY to 244 * be a master, otherwise it's a slave. 245 */ 246 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 247 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 248 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 249 } else { 250 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 251 gig|RGEPHY_1000CTL_MSE); 252 } 253 break; 254 #ifdef foo 255 case IFM_NONE: 256 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 257 break; 258 #endif 259 case IFM_100_T4: 260 default: 261 return (EINVAL); 262 } 263 break; 264 265 case MII_TICK: 266 /* 267 * If we're not currently selected, just return. 268 */ 269 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 270 return (0); 271 272 /* 273 * Is the interface even up? 274 */ 275 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 276 return (0); 277 278 /* 279 * Only used for autonegotiation. 280 */ 281 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 282 break; 283 284 /* 285 * Check to see if we have link. If we do, we don't 286 * need to restart the autonegotiation process. Read 287 * the BMSR twice in case it's latched. 288 */ 289 reg = PHY_READ(sc, RL_GMEDIASTAT); 290 if (reg & RL_GMEDIASTAT_LINK) 291 break; 292 293 /* 294 * Only retry autonegotiation every 5 seconds. 295 */ 296 if (++sc->mii_ticks <= 5/*10*/) 297 break; 298 299 sc->mii_ticks = 0; 300 rgephy_mii_phy_auto(sc); 301 return (0); 302 } 303 304 /* Update the media status. */ 305 rgephy_status(sc); 306 307 /* 308 * Callback if something changed. Note that we need to poke 309 * the DSP on the RealTek PHYs if the media changes. 310 * 311 */ 312 if (sc->mii_media_active != mii->mii_media_active || 313 sc->mii_media_status != mii->mii_media_status || 314 cmd == MII_MEDIACHG) { 315 rgephy_load_dspcode(sc); 316 } 317 mii_phy_update(sc, cmd); 318 return (0); 319 } 320 321 static void 322 rgephy_status(struct mii_softc *sc) 323 { 324 struct mii_data *mii = sc->mii_pdata; 325 int bmsr, bmcr; 326 327 mii->mii_media_status = IFM_AVALID; 328 mii->mii_media_active = IFM_ETHER; 329 330 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 331 332 if (bmsr & RL_GMEDIASTAT_LINK) 333 mii->mii_media_status |= IFM_ACTIVE; 334 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 335 336 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 337 338 if (bmcr & RGEPHY_BMCR_LOOP) 339 mii->mii_media_active |= IFM_LOOP; 340 341 if (bmcr & RGEPHY_BMCR_AUTOEN) { 342 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 343 /* Erg, still trying, I guess... */ 344 mii->mii_media_active |= IFM_NONE; 345 return; 346 } 347 } 348 349 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 350 if (bmsr & RL_GMEDIASTAT_1000MBPS) 351 mii->mii_media_active |= IFM_1000_T; 352 else if (bmsr & RL_GMEDIASTAT_100MBPS) 353 mii->mii_media_active |= IFM_100_TX; 354 else if (bmsr & RL_GMEDIASTAT_10MBPS) 355 mii->mii_media_active |= IFM_10_T; 356 else 357 mii->mii_media_active |= IFM_NONE; 358 if (bmsr & RL_GMEDIASTAT_FDX) 359 mii->mii_media_active |= IFM_FDX; 360 361 return; 362 } 363 364 365 static int 366 rgephy_mii_phy_auto(struct mii_softc *mii) 367 { 368 rgephy_loop(mii); 369 rgephy_reset(mii); 370 371 PHY_WRITE(mii, RGEPHY_MII_ANAR, 372 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 373 DELAY(1000); 374 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 375 RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD); 376 DELAY(1000); 377 PHY_WRITE(mii, RGEPHY_MII_BMCR, 378 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 379 DELAY(100); 380 381 return (EJUSTRETURN); 382 } 383 384 static void 385 rgephy_loop(struct mii_softc *sc) 386 { 387 u_int32_t bmsr; 388 int i; 389 390 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 391 DELAY(1000); 392 393 for (i = 0; i < 15000; i++) { 394 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 395 if (!(bmsr & RGEPHY_BMSR_LINK)) { 396 #if 0 397 device_printf(sc->mii_dev, "looped %d\n", i); 398 #endif 399 break; 400 } 401 DELAY(10); 402 } 403 } 404 405 #define PHY_SETBIT(x, y, z) \ 406 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 407 #define PHY_CLRBIT(x, y, z) \ 408 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 409 410 /* 411 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 412 * existing revisions of the 8169S/8110S chips need to be tuned in 413 * order to reliably negotiate a 1000Mbps link. This is only needed 414 * for rev 0 and rev 1 of the PHY. Later versions work without 415 * any fixups. 416 */ 417 static void 418 rgephy_load_dspcode(struct mii_softc *sc) 419 { 420 int val; 421 uint16_t id2; 422 423 id2 = PHY_READ(sc, MII_PHYIDR2); 424 425 if (MII_REV(id2) > 1) 426 return; 427 428 PHY_WRITE(sc, 31, 0x0001); 429 PHY_WRITE(sc, 21, 0x1000); 430 PHY_WRITE(sc, 24, 0x65C7); 431 PHY_CLRBIT(sc, 4, 0x0800); 432 val = PHY_READ(sc, 4) & 0xFFF; 433 PHY_WRITE(sc, 4, val); 434 PHY_WRITE(sc, 3, 0x00A1); 435 PHY_WRITE(sc, 2, 0x0008); 436 PHY_WRITE(sc, 1, 0x1020); 437 PHY_WRITE(sc, 0, 0x1000); 438 PHY_SETBIT(sc, 4, 0x0800); 439 PHY_CLRBIT(sc, 4, 0x0800); 440 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 441 PHY_WRITE(sc, 4, val); 442 PHY_WRITE(sc, 3, 0xFF41); 443 PHY_WRITE(sc, 2, 0xDE60); 444 PHY_WRITE(sc, 1, 0x0140); 445 PHY_WRITE(sc, 0, 0x0077); 446 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 447 PHY_WRITE(sc, 4, val); 448 PHY_WRITE(sc, 3, 0xDF01); 449 PHY_WRITE(sc, 2, 0xDF20); 450 PHY_WRITE(sc, 1, 0xFF95); 451 PHY_WRITE(sc, 0, 0xFA00); 452 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 453 PHY_WRITE(sc, 4, val); 454 PHY_WRITE(sc, 3, 0xFF41); 455 PHY_WRITE(sc, 2, 0xDE20); 456 PHY_WRITE(sc, 1, 0x0140); 457 PHY_WRITE(sc, 0, 0x00BB); 458 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 459 PHY_WRITE(sc, 4, val); 460 PHY_WRITE(sc, 3, 0xDF01); 461 PHY_WRITE(sc, 2, 0xDF20); 462 PHY_WRITE(sc, 1, 0xFF95); 463 PHY_WRITE(sc, 0, 0xBF00); 464 PHY_SETBIT(sc, 4, 0x0800); 465 PHY_CLRBIT(sc, 4, 0x0800); 466 PHY_WRITE(sc, 31, 0x0000); 467 468 DELAY(40); 469 } 470 471 static void 472 rgephy_reset(struct mii_softc *sc) 473 { 474 mii_phy_reset(sc); 475 DELAY(1000); 476 rgephy_load_dspcode(sc); 477 478 return; 479 } 480