1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/taskqueue.h> 46 #include <sys/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include "miibus_if.h" 60 61 #include <machine/bus.h> 62 #include <pci/if_rlreg.h> 63 64 static int rgephy_probe(device_t); 65 static int rgephy_attach(device_t); 66 67 static device_method_t rgephy_methods[] = { 68 /* device interface */ 69 DEVMETHOD(device_probe, rgephy_probe), 70 DEVMETHOD(device_attach, rgephy_attach), 71 DEVMETHOD(device_detach, mii_phy_detach), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 DEVMETHOD_END 74 }; 75 76 static devclass_t rgephy_devclass; 77 78 static driver_t rgephy_driver = { 79 "rgephy", 80 rgephy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 85 86 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 87 static void rgephy_status(struct mii_softc *); 88 static int rgephy_mii_phy_auto(struct mii_softc *, int); 89 static void rgephy_reset(struct mii_softc *); 90 static void rgephy_loop(struct mii_softc *); 91 static void rgephy_load_dspcode(struct mii_softc *); 92 93 static const struct mii_phydesc rgephys[] = { 94 MII_PHY_DESC(REALTEK, RTL8169S), 95 MII_PHY_DESC(REALTEK, RTL8251), 96 MII_PHY_END 97 }; 98 99 static const struct mii_phy_funcs rgephy_funcs = { 100 rgephy_service, 101 rgephy_status, 102 rgephy_reset 103 }; 104 105 static int 106 rgephy_probe(device_t dev) 107 { 108 109 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 110 } 111 112 static int 113 rgephy_attach(device_t dev) 114 { 115 struct mii_softc *sc; 116 struct mii_attach_args *ma; 117 u_int flags; 118 119 sc = device_get_softc(dev); 120 ma = device_get_ivars(dev); 121 flags = 0; 122 if (strcmp(if_getdname(ma->mii_data->mii_ifp), "re") == 0) 123 flags |= MIIF_PHYPRIV0; 124 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 125 126 /* RTL8169S do not report auto-sense; add manually. */ 127 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 128 sc->mii_capmask; 129 if (sc->mii_capabilities & BMSR_EXTSTAT) 130 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 131 device_printf(dev, " "); 132 mii_phy_add_media(sc); 133 printf("\n"); 134 /* 135 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 136 * manual configuration, which is used to work around issues with 137 * certain setups by default, should not be triggered as it may in 138 * turn cause harm in some edge cases. 139 */ 140 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 141 142 PHY_RESET(sc); 143 144 MIIBUS_MEDIAINIT(sc->mii_dev); 145 return (0); 146 } 147 148 static int 149 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 150 { 151 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 152 int reg, speed, gig, anar; 153 154 switch (cmd) { 155 case MII_POLLSTAT: 156 break; 157 158 case MII_MEDIACHG: 159 PHY_RESET(sc); /* XXX hardware bug work-around */ 160 161 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 162 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 163 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 164 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 165 166 switch (IFM_SUBTYPE(ife->ifm_media)) { 167 case IFM_AUTO: 168 #ifdef foo 169 /* 170 * If we're already in auto mode, just return. 171 */ 172 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 173 return (0); 174 #endif 175 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 176 break; 177 case IFM_1000_T: 178 speed = RGEPHY_S1000; 179 goto setit; 180 case IFM_100_TX: 181 speed = RGEPHY_S100; 182 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 183 goto setit; 184 case IFM_10_T: 185 speed = RGEPHY_S10; 186 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 187 setit: 188 if ((ife->ifm_media & IFM_FLOW) != 0 && 189 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 190 return (EINVAL); 191 192 if ((ife->ifm_media & IFM_FDX) != 0) { 193 speed |= RGEPHY_BMCR_FDX; 194 gig = RGEPHY_1000CTL_AFD; 195 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 196 if ((ife->ifm_media & IFM_FLOW) != 0 || 197 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 198 anar |= 199 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 200 } else { 201 gig = RGEPHY_1000CTL_AHD; 202 anar &= 203 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 204 } 205 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 206 gig |= RGEPHY_1000CTL_MSE; 207 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 208 gig |= RGEPHY_1000CTL_MSC; 209 } else { 210 gig = 0; 211 anar &= ~RGEPHY_ANAR_ASP; 212 } 213 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 214 speed |= 215 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 216 rgephy_loop(sc); 217 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 218 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 219 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 220 break; 221 case IFM_NONE: 222 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 223 break; 224 default: 225 return (EINVAL); 226 } 227 break; 228 229 case MII_TICK: 230 /* 231 * Only used for autonegotiation. 232 */ 233 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 234 sc->mii_ticks = 0; 235 break; 236 } 237 238 /* 239 * Check to see if we have link. If we do, we don't 240 * need to restart the autonegotiation process. 241 */ 242 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 243 sc->mii_mpd_rev >= 2) { 244 /* RTL8211B(L) */ 245 reg = PHY_READ(sc, RGEPHY_MII_SSR); 246 if (reg & RGEPHY_SSR_LINK) { 247 sc->mii_ticks = 0; 248 break; 249 } 250 } else { 251 reg = PHY_READ(sc, RL_GMEDIASTAT); 252 if (reg & RL_GMEDIASTAT_LINK) { 253 sc->mii_ticks = 0; 254 break; 255 } 256 } 257 258 /* Announce link loss right after it happens. */ 259 if (sc->mii_ticks++ == 0) 260 break; 261 262 /* Only retry autonegotiation every mii_anegticks seconds. */ 263 if (sc->mii_ticks <= sc->mii_anegticks) 264 return (0); 265 266 sc->mii_ticks = 0; 267 rgephy_mii_phy_auto(sc, ife->ifm_media); 268 break; 269 } 270 271 /* Update the media status. */ 272 PHY_STATUS(sc); 273 274 /* 275 * Callback if something changed. Note that we need to poke 276 * the DSP on the RealTek PHYs if the media changes. 277 * 278 */ 279 if (sc->mii_media_active != mii->mii_media_active || 280 sc->mii_media_status != mii->mii_media_status || 281 cmd == MII_MEDIACHG) { 282 rgephy_load_dspcode(sc); 283 } 284 mii_phy_update(sc, cmd); 285 return (0); 286 } 287 288 static void 289 rgephy_status(struct mii_softc *sc) 290 { 291 struct mii_data *mii = sc->mii_pdata; 292 int bmsr, bmcr; 293 uint16_t ssr; 294 295 mii->mii_media_status = IFM_AVALID; 296 mii->mii_media_active = IFM_ETHER; 297 298 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 299 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 300 if (ssr & RGEPHY_SSR_LINK) 301 mii->mii_media_status |= IFM_ACTIVE; 302 } else { 303 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 304 if (bmsr & RL_GMEDIASTAT_LINK) 305 mii->mii_media_status |= IFM_ACTIVE; 306 } 307 308 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 309 310 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 311 if (bmcr & RGEPHY_BMCR_ISO) { 312 mii->mii_media_active |= IFM_NONE; 313 mii->mii_media_status = 0; 314 return; 315 } 316 317 if (bmcr & RGEPHY_BMCR_LOOP) 318 mii->mii_media_active |= IFM_LOOP; 319 320 if (bmcr & RGEPHY_BMCR_AUTOEN) { 321 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 322 /* Erg, still trying, I guess... */ 323 mii->mii_media_active |= IFM_NONE; 324 return; 325 } 326 } 327 328 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 329 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 330 switch (ssr & RGEPHY_SSR_SPD_MASK) { 331 case RGEPHY_SSR_S1000: 332 mii->mii_media_active |= IFM_1000_T; 333 break; 334 case RGEPHY_SSR_S100: 335 mii->mii_media_active |= IFM_100_TX; 336 break; 337 case RGEPHY_SSR_S10: 338 mii->mii_media_active |= IFM_10_T; 339 break; 340 default: 341 mii->mii_media_active |= IFM_NONE; 342 break; 343 } 344 if (ssr & RGEPHY_SSR_FDX) 345 mii->mii_media_active |= IFM_FDX; 346 else 347 mii->mii_media_active |= IFM_HDX; 348 } else { 349 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 350 if (bmsr & RL_GMEDIASTAT_1000MBPS) 351 mii->mii_media_active |= IFM_1000_T; 352 else if (bmsr & RL_GMEDIASTAT_100MBPS) 353 mii->mii_media_active |= IFM_100_TX; 354 else if (bmsr & RL_GMEDIASTAT_10MBPS) 355 mii->mii_media_active |= IFM_10_T; 356 else 357 mii->mii_media_active |= IFM_NONE; 358 if (bmsr & RL_GMEDIASTAT_FDX) 359 mii->mii_media_active |= IFM_FDX; 360 else 361 mii->mii_media_active |= IFM_HDX; 362 } 363 364 if ((mii->mii_media_active & IFM_FDX) != 0) 365 mii->mii_media_active |= mii_phy_flowstatus(sc); 366 367 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 368 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 369 mii->mii_media_active |= IFM_ETH_MASTER; 370 } 371 372 static int 373 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 374 { 375 int anar; 376 377 rgephy_loop(sc); 378 PHY_RESET(sc); 379 380 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 381 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 382 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 383 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 384 DELAY(1000); 385 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 386 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 387 DELAY(1000); 388 PHY_WRITE(sc, RGEPHY_MII_BMCR, 389 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 390 DELAY(100); 391 392 return (EJUSTRETURN); 393 } 394 395 static void 396 rgephy_loop(struct mii_softc *sc) 397 { 398 int i; 399 400 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 401 sc->mii_mpd_rev < 2) { 402 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 403 DELAY(1000); 404 } 405 406 for (i = 0; i < 15000; i++) { 407 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 408 #if 0 409 device_printf(sc->mii_dev, "looped %d\n", i); 410 #endif 411 break; 412 } 413 DELAY(10); 414 } 415 } 416 417 #define PHY_SETBIT(x, y, z) \ 418 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 419 #define PHY_CLRBIT(x, y, z) \ 420 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 421 422 /* 423 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 424 * existing revisions of the 8169S/8110S chips need to be tuned in 425 * order to reliably negotiate a 1000Mbps link. This is only needed 426 * for rev 0 and rev 1 of the PHY. Later versions work without 427 * any fixups. 428 */ 429 static void 430 rgephy_load_dspcode(struct mii_softc *sc) 431 { 432 int val; 433 434 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 435 sc->mii_mpd_rev >= 2) 436 return; 437 438 PHY_WRITE(sc, 31, 0x0001); 439 PHY_WRITE(sc, 21, 0x1000); 440 PHY_WRITE(sc, 24, 0x65C7); 441 PHY_CLRBIT(sc, 4, 0x0800); 442 val = PHY_READ(sc, 4) & 0xFFF; 443 PHY_WRITE(sc, 4, val); 444 PHY_WRITE(sc, 3, 0x00A1); 445 PHY_WRITE(sc, 2, 0x0008); 446 PHY_WRITE(sc, 1, 0x1020); 447 PHY_WRITE(sc, 0, 0x1000); 448 PHY_SETBIT(sc, 4, 0x0800); 449 PHY_CLRBIT(sc, 4, 0x0800); 450 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 451 PHY_WRITE(sc, 4, val); 452 PHY_WRITE(sc, 3, 0xFF41); 453 PHY_WRITE(sc, 2, 0xDE60); 454 PHY_WRITE(sc, 1, 0x0140); 455 PHY_WRITE(sc, 0, 0x0077); 456 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 457 PHY_WRITE(sc, 4, val); 458 PHY_WRITE(sc, 3, 0xDF01); 459 PHY_WRITE(sc, 2, 0xDF20); 460 PHY_WRITE(sc, 1, 0xFF95); 461 PHY_WRITE(sc, 0, 0xFA00); 462 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 463 PHY_WRITE(sc, 4, val); 464 PHY_WRITE(sc, 3, 0xFF41); 465 PHY_WRITE(sc, 2, 0xDE20); 466 PHY_WRITE(sc, 1, 0x0140); 467 PHY_WRITE(sc, 0, 0x00BB); 468 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 469 PHY_WRITE(sc, 4, val); 470 PHY_WRITE(sc, 3, 0xDF01); 471 PHY_WRITE(sc, 2, 0xDF20); 472 PHY_WRITE(sc, 1, 0xFF95); 473 PHY_WRITE(sc, 0, 0xBF00); 474 PHY_SETBIT(sc, 4, 0x0800); 475 PHY_CLRBIT(sc, 4, 0x0800); 476 PHY_WRITE(sc, 31, 0x0000); 477 478 DELAY(40); 479 } 480 481 static void 482 rgephy_reset(struct mii_softc *sc) 483 { 484 uint16_t pcr, ssr; 485 486 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { 487 /* RTL8211C(L) */ 488 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 489 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 490 ssr &= ~RGEPHY_SSR_ALDPS; 491 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 492 } 493 } 494 495 if (sc->mii_mpd_rev >= 2) { 496 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 497 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 498 pcr &= ~RGEPHY_PCR_MDI_MASK; 499 pcr |= RGEPHY_PCR_MDIX_AUTO; 500 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 501 } 502 } 503 504 mii_phy_reset(sc); 505 DELAY(1000); 506 rgephy_load_dspcode(sc); 507 } 508