1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/rgephyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 #include <pci/if_rlreg.h> 61 62 static int rgephy_probe(device_t); 63 static int rgephy_attach(device_t); 64 65 static device_method_t rgephy_methods[] = { 66 /* device interface */ 67 DEVMETHOD(device_probe, rgephy_probe), 68 DEVMETHOD(device_attach, rgephy_attach), 69 DEVMETHOD(device_detach, mii_phy_detach), 70 DEVMETHOD(device_shutdown, bus_generic_shutdown), 71 DEVMETHOD_END 72 }; 73 74 static devclass_t rgephy_devclass; 75 76 static driver_t rgephy_driver = { 77 "rgephy", 78 rgephy_methods, 79 sizeof(struct mii_softc) 80 }; 81 82 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 83 84 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 85 static void rgephy_status(struct mii_softc *); 86 static int rgephy_mii_phy_auto(struct mii_softc *, int); 87 static void rgephy_reset(struct mii_softc *); 88 static void rgephy_loop(struct mii_softc *); 89 static void rgephy_load_dspcode(struct mii_softc *); 90 91 static const struct mii_phydesc rgephys[] = { 92 MII_PHY_DESC(REALTEK, RTL8169S), 93 MII_PHY_END 94 }; 95 96 static const struct mii_phy_funcs rgephy_funcs = { 97 rgephy_service, 98 rgephy_status, 99 rgephy_reset 100 }; 101 102 static int 103 rgephy_probe(device_t dev) 104 { 105 106 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct mii_softc *sc; 113 114 sc = device_get_softc(dev); 115 116 mii_phy_dev_attach(dev, 0, &rgephy_funcs, 0); 117 118 /* RTL8169S do not report auto-sense; add manually. */ 119 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 120 sc->mii_capmask; 121 if (sc->mii_capabilities & BMSR_EXTSTAT) 122 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 123 device_printf(dev, " "); 124 mii_phy_add_media(sc); 125 printf("\n"); 126 /* 127 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 128 * manual configuration, which is used to work around issues with 129 * certain setups by default, should not be triggered as it may in 130 * turn cause harm in some edge cases. 131 */ 132 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 133 134 PHY_RESET(sc); 135 136 MIIBUS_MEDIAINIT(sc->mii_dev); 137 return (0); 138 } 139 140 static int 141 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 142 { 143 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 144 int reg, speed, gig, anar; 145 146 switch (cmd) { 147 case MII_POLLSTAT: 148 break; 149 150 case MII_MEDIACHG: 151 /* 152 * If the interface is not up, don't do anything. 153 */ 154 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 155 break; 156 157 PHY_RESET(sc); /* XXX hardware bug work-around */ 158 159 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 160 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 161 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 162 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 163 164 switch (IFM_SUBTYPE(ife->ifm_media)) { 165 case IFM_AUTO: 166 #ifdef foo 167 /* 168 * If we're already in auto mode, just return. 169 */ 170 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 171 return (0); 172 #endif 173 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 174 break; 175 case IFM_1000_T: 176 speed = RGEPHY_S1000; 177 goto setit; 178 case IFM_100_TX: 179 speed = RGEPHY_S100; 180 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 181 goto setit; 182 case IFM_10_T: 183 speed = RGEPHY_S10; 184 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 185 setit: 186 if ((ife->ifm_media & IFM_FLOW) != 0 && 187 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 188 return (EINVAL); 189 190 if ((ife->ifm_media & IFM_FDX) != 0) { 191 speed |= RGEPHY_BMCR_FDX; 192 gig = RGEPHY_1000CTL_AFD; 193 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 194 if ((ife->ifm_media & IFM_FLOW) != 0 || 195 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 196 anar |= 197 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 198 } else { 199 gig = RGEPHY_1000CTL_AHD; 200 anar &= 201 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 202 } 203 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 204 gig |= RGEPHY_1000CTL_MSE; 205 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 206 gig |= RGEPHY_1000CTL_MSC; 207 } else { 208 gig = 0; 209 anar &= ~RGEPHY_ANAR_ASP; 210 } 211 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 212 speed |= 213 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 214 rgephy_loop(sc); 215 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 216 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 217 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 218 break; 219 case IFM_NONE: 220 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 221 break; 222 default: 223 return (EINVAL); 224 } 225 break; 226 227 case MII_TICK: 228 /* 229 * Is the interface even up? 230 */ 231 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 232 return (0); 233 234 /* 235 * Only used for autonegotiation. 236 */ 237 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 238 sc->mii_ticks = 0; 239 break; 240 } 241 242 /* 243 * Check to see if we have link. If we do, we don't 244 * need to restart the autonegotiation process. 245 */ 246 if (sc->mii_mpd_rev >= 2) { 247 /* RTL8211B(L) */ 248 reg = PHY_READ(sc, RGEPHY_MII_SSR); 249 if (reg & RGEPHY_SSR_LINK) { 250 sc->mii_ticks = 0; 251 break; 252 } 253 } else { 254 reg = PHY_READ(sc, RL_GMEDIASTAT); 255 if (reg & RL_GMEDIASTAT_LINK) { 256 sc->mii_ticks = 0; 257 break; 258 } 259 } 260 261 /* Announce link loss right after it happens. */ 262 if (sc->mii_ticks++ == 0) 263 break; 264 265 /* Only retry autonegotiation every mii_anegticks seconds. */ 266 if (sc->mii_ticks <= sc->mii_anegticks) 267 return (0); 268 269 sc->mii_ticks = 0; 270 rgephy_mii_phy_auto(sc, ife->ifm_media); 271 break; 272 } 273 274 /* Update the media status. */ 275 PHY_STATUS(sc); 276 277 /* 278 * Callback if something changed. Note that we need to poke 279 * the DSP on the RealTek PHYs if the media changes. 280 * 281 */ 282 if (sc->mii_media_active != mii->mii_media_active || 283 sc->mii_media_status != mii->mii_media_status || 284 cmd == MII_MEDIACHG) { 285 rgephy_load_dspcode(sc); 286 } 287 mii_phy_update(sc, cmd); 288 return (0); 289 } 290 291 static void 292 rgephy_status(struct mii_softc *sc) 293 { 294 struct mii_data *mii = sc->mii_pdata; 295 int bmsr, bmcr; 296 uint16_t ssr; 297 298 mii->mii_media_status = IFM_AVALID; 299 mii->mii_media_active = IFM_ETHER; 300 301 if (sc->mii_mpd_rev >= 2) { 302 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 303 if (ssr & RGEPHY_SSR_LINK) 304 mii->mii_media_status |= IFM_ACTIVE; 305 } else { 306 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 307 if (bmsr & RL_GMEDIASTAT_LINK) 308 mii->mii_media_status |= IFM_ACTIVE; 309 } 310 311 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 312 313 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 314 if (bmcr & RGEPHY_BMCR_ISO) { 315 mii->mii_media_active |= IFM_NONE; 316 mii->mii_media_status = 0; 317 return; 318 } 319 320 if (bmcr & RGEPHY_BMCR_LOOP) 321 mii->mii_media_active |= IFM_LOOP; 322 323 if (bmcr & RGEPHY_BMCR_AUTOEN) { 324 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 325 /* Erg, still trying, I guess... */ 326 mii->mii_media_active |= IFM_NONE; 327 return; 328 } 329 } 330 331 if (sc->mii_mpd_rev >= 2) { 332 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 333 switch (ssr & RGEPHY_SSR_SPD_MASK) { 334 case RGEPHY_SSR_S1000: 335 mii->mii_media_active |= IFM_1000_T; 336 break; 337 case RGEPHY_SSR_S100: 338 mii->mii_media_active |= IFM_100_TX; 339 break; 340 case RGEPHY_SSR_S10: 341 mii->mii_media_active |= IFM_10_T; 342 break; 343 default: 344 mii->mii_media_active |= IFM_NONE; 345 break; 346 } 347 if (ssr & RGEPHY_SSR_FDX) 348 mii->mii_media_active |= IFM_FDX; 349 else 350 mii->mii_media_active |= IFM_HDX; 351 } else { 352 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 353 if (bmsr & RL_GMEDIASTAT_1000MBPS) 354 mii->mii_media_active |= IFM_1000_T; 355 else if (bmsr & RL_GMEDIASTAT_100MBPS) 356 mii->mii_media_active |= IFM_100_TX; 357 else if (bmsr & RL_GMEDIASTAT_10MBPS) 358 mii->mii_media_active |= IFM_10_T; 359 else 360 mii->mii_media_active |= IFM_NONE; 361 if (bmsr & RL_GMEDIASTAT_FDX) 362 mii->mii_media_active |= IFM_FDX; 363 else 364 mii->mii_media_active |= IFM_HDX; 365 } 366 367 if ((mii->mii_media_active & IFM_FDX) != 0) 368 mii->mii_media_active |= mii_phy_flowstatus(sc); 369 370 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 371 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 372 mii->mii_media_active |= IFM_ETH_MASTER; 373 } 374 375 static int 376 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 377 { 378 int anar; 379 380 rgephy_loop(sc); 381 PHY_RESET(sc); 382 383 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 384 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 385 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 386 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 387 DELAY(1000); 388 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 389 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 390 DELAY(1000); 391 PHY_WRITE(sc, RGEPHY_MII_BMCR, 392 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 393 DELAY(100); 394 395 return (EJUSTRETURN); 396 } 397 398 static void 399 rgephy_loop(struct mii_softc *sc) 400 { 401 int i; 402 403 if (sc->mii_mpd_rev < 2) { 404 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 405 DELAY(1000); 406 } 407 408 for (i = 0; i < 15000; i++) { 409 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 410 #if 0 411 device_printf(sc->mii_dev, "looped %d\n", i); 412 #endif 413 break; 414 } 415 DELAY(10); 416 } 417 } 418 419 #define PHY_SETBIT(x, y, z) \ 420 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 421 #define PHY_CLRBIT(x, y, z) \ 422 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 423 424 /* 425 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 426 * existing revisions of the 8169S/8110S chips need to be tuned in 427 * order to reliably negotiate a 1000Mbps link. This is only needed 428 * for rev 0 and rev 1 of the PHY. Later versions work without 429 * any fixups. 430 */ 431 static void 432 rgephy_load_dspcode(struct mii_softc *sc) 433 { 434 int val; 435 436 if (sc->mii_mpd_rev >= 2) 437 return; 438 439 PHY_WRITE(sc, 31, 0x0001); 440 PHY_WRITE(sc, 21, 0x1000); 441 PHY_WRITE(sc, 24, 0x65C7); 442 PHY_CLRBIT(sc, 4, 0x0800); 443 val = PHY_READ(sc, 4) & 0xFFF; 444 PHY_WRITE(sc, 4, val); 445 PHY_WRITE(sc, 3, 0x00A1); 446 PHY_WRITE(sc, 2, 0x0008); 447 PHY_WRITE(sc, 1, 0x1020); 448 PHY_WRITE(sc, 0, 0x1000); 449 PHY_SETBIT(sc, 4, 0x0800); 450 PHY_CLRBIT(sc, 4, 0x0800); 451 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 452 PHY_WRITE(sc, 4, val); 453 PHY_WRITE(sc, 3, 0xFF41); 454 PHY_WRITE(sc, 2, 0xDE60); 455 PHY_WRITE(sc, 1, 0x0140); 456 PHY_WRITE(sc, 0, 0x0077); 457 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 458 PHY_WRITE(sc, 4, val); 459 PHY_WRITE(sc, 3, 0xDF01); 460 PHY_WRITE(sc, 2, 0xDF20); 461 PHY_WRITE(sc, 1, 0xFF95); 462 PHY_WRITE(sc, 0, 0xFA00); 463 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 464 PHY_WRITE(sc, 4, val); 465 PHY_WRITE(sc, 3, 0xFF41); 466 PHY_WRITE(sc, 2, 0xDE20); 467 PHY_WRITE(sc, 1, 0x0140); 468 PHY_WRITE(sc, 0, 0x00BB); 469 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 470 PHY_WRITE(sc, 4, val); 471 PHY_WRITE(sc, 3, 0xDF01); 472 PHY_WRITE(sc, 2, 0xDF20); 473 PHY_WRITE(sc, 1, 0xFF95); 474 PHY_WRITE(sc, 0, 0xBF00); 475 PHY_SETBIT(sc, 4, 0x0800); 476 PHY_CLRBIT(sc, 4, 0x0800); 477 PHY_WRITE(sc, 31, 0x0000); 478 479 DELAY(40); 480 } 481 482 static void 483 rgephy_reset(struct mii_softc *sc) 484 { 485 uint16_t ssr; 486 487 if (sc->mii_mpd_rev == 3) { 488 /* RTL8211C(L) */ 489 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 490 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 491 ssr &= ~RGEPHY_SSR_ALDPS; 492 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 493 } 494 } 495 496 mii_phy_reset(sc); 497 DELAY(1000); 498 rgephy_load_dspcode(sc); 499 } 500