1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include "miibus_if.h" 59 60 #include <machine/bus.h> 61 #include <pci/if_rlreg.h> 62 63 static int rgephy_probe(device_t); 64 static int rgephy_attach(device_t); 65 66 static device_method_t rgephy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, rgephy_probe), 69 DEVMETHOD(device_attach, rgephy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t rgephy_devclass; 76 77 static driver_t rgephy_driver = { 78 "rgephy", 79 rgephy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 84 85 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 86 static void rgephy_status(struct mii_softc *); 87 static int rgephy_mii_phy_auto(struct mii_softc *); 88 static void rgephy_reset(struct mii_softc *); 89 static void rgephy_loop(struct mii_softc *); 90 static void rgephy_load_dspcode(struct mii_softc *); 91 static int rgephy_mii_model; 92 93 static int 94 rgephy_probe(device_t dev) 95 { 96 struct mii_attach_args *ma; 97 98 ma = device_get_ivars(dev); 99 100 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK && 101 MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) { 102 device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S); 103 return(BUS_PROBE_DEFAULT); 104 } 105 106 return(ENXIO); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct mii_softc *sc; 113 struct mii_attach_args *ma; 114 struct mii_data *mii; 115 const char *sep = ""; 116 117 sc = device_get_softc(dev); 118 ma = device_get_ivars(dev); 119 sc->mii_dev = device_get_parent(dev); 120 mii = device_get_softc(sc->mii_dev); 121 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 122 123 sc->mii_inst = mii->mii_instance; 124 sc->mii_phy = ma->mii_phyno; 125 sc->mii_service = rgephy_service; 126 sc->mii_pdata = mii; 127 128 sc->mii_flags |= MIIF_NOISOLATE; 129 mii->mii_instance++; 130 131 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 132 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 133 134 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 135 BMCR_ISO); 136 #if 0 137 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 138 BMCR_LOOP|BMCR_S100); 139 #endif 140 141 rgephy_mii_model = MII_MODEL(ma->mii_id2); 142 143 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 144 sc->mii_capabilities &= ~BMSR_ANEG; 145 146 device_printf(dev, " "); 147 mii_add_media(sc); 148 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 149 RGEPHY_BMCR_FDX); 150 PRINT(", 1000baseTX"); 151 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 152 PRINT("1000baseTX-FDX"); 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 154 PRINT("auto"); 155 156 printf("\n"); 157 #undef ADD 158 #undef PRINT 159 160 rgephy_reset(sc); 161 MIIBUS_MEDIAINIT(sc->mii_dev); 162 return(0); 163 } 164 165 static int 166 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 167 { 168 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 169 int reg, speed, gig, anar; 170 171 switch (cmd) { 172 case MII_POLLSTAT: 173 /* 174 * If we're not polling our PHY instance, just return. 175 */ 176 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 177 return (0); 178 break; 179 180 case MII_MEDIACHG: 181 /* 182 * If the media indicates a different PHY instance, 183 * isolate ourselves. 184 */ 185 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 186 reg = PHY_READ(sc, MII_BMCR); 187 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 188 return (0); 189 } 190 191 /* 192 * If the interface is not up, don't do anything. 193 */ 194 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 195 break; 196 197 rgephy_reset(sc); /* XXX hardware bug work-around */ 198 199 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 200 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 201 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 202 203 switch (IFM_SUBTYPE(ife->ifm_media)) { 204 case IFM_AUTO: 205 #ifdef foo 206 /* 207 * If we're already in auto mode, just return. 208 */ 209 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 210 return (0); 211 #endif 212 (void) rgephy_mii_phy_auto(sc); 213 break; 214 case IFM_1000_T: 215 speed = RGEPHY_S1000; 216 goto setit; 217 case IFM_100_TX: 218 speed = RGEPHY_S100; 219 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 220 goto setit; 221 case IFM_10_T: 222 speed = RGEPHY_S10; 223 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 224 setit: 225 rgephy_loop(sc); 226 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 227 speed |= RGEPHY_BMCR_FDX; 228 gig = RGEPHY_1000CTL_AFD; 229 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 230 } else { 231 gig = RGEPHY_1000CTL_AHD; 232 anar &= 233 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 234 } 235 236 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 237 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 238 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 239 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 240 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 241 break; 242 } 243 244 /* 245 * When settning the link manually, one side must 246 * be the master and the other the slave. However 247 * ifmedia doesn't give us a good way to specify 248 * this, so we fake it by using one of the LINK 249 * flags. If LINK0 is set, we program the PHY to 250 * be a master, otherwise it's a slave. 251 */ 252 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 253 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 254 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 255 } else { 256 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 257 gig|RGEPHY_1000CTL_MSE); 258 } 259 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 260 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 261 break; 262 #ifdef foo 263 case IFM_NONE: 264 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 265 break; 266 #endif 267 case IFM_100_T4: 268 default: 269 return (EINVAL); 270 } 271 break; 272 273 case MII_TICK: 274 /* 275 * If we're not currently selected, just return. 276 */ 277 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 278 return (0); 279 280 /* 281 * Is the interface even up? 282 */ 283 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 284 return (0); 285 286 /* 287 * Only used for autonegotiation. 288 */ 289 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 290 break; 291 292 /* 293 * Check to see if we have link. If we do, we don't 294 * need to restart the autonegotiation process. Read 295 * the BMSR twice in case it's latched. 296 */ 297 reg = PHY_READ(sc, RL_GMEDIASTAT); 298 if (reg & RL_GMEDIASTAT_LINK) 299 break; 300 301 /* 302 * Only retry autonegotiation every 5 seconds. 303 */ 304 if (++sc->mii_ticks <= 5/*10*/) 305 break; 306 307 sc->mii_ticks = 0; 308 rgephy_mii_phy_auto(sc); 309 return (0); 310 } 311 312 /* Update the media status. */ 313 rgephy_status(sc); 314 315 /* 316 * Callback if something changed. Note that we need to poke 317 * the DSP on the RealTek PHYs if the media changes. 318 * 319 */ 320 if (sc->mii_media_active != mii->mii_media_active || 321 sc->mii_media_status != mii->mii_media_status || 322 cmd == MII_MEDIACHG) { 323 rgephy_load_dspcode(sc); 324 } 325 mii_phy_update(sc, cmd); 326 return (0); 327 } 328 329 static void 330 rgephy_status(struct mii_softc *sc) 331 { 332 struct mii_data *mii = sc->mii_pdata; 333 int bmsr, bmcr; 334 335 mii->mii_media_status = IFM_AVALID; 336 mii->mii_media_active = IFM_ETHER; 337 338 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 339 340 if (bmsr & RL_GMEDIASTAT_LINK) 341 mii->mii_media_status |= IFM_ACTIVE; 342 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 343 344 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 345 346 if (bmcr & RGEPHY_BMCR_LOOP) 347 mii->mii_media_active |= IFM_LOOP; 348 349 if (bmcr & RGEPHY_BMCR_AUTOEN) { 350 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 351 /* Erg, still trying, I guess... */ 352 mii->mii_media_active |= IFM_NONE; 353 return; 354 } 355 } 356 357 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 358 if (bmsr & RL_GMEDIASTAT_1000MBPS) 359 mii->mii_media_active |= IFM_1000_T; 360 else if (bmsr & RL_GMEDIASTAT_100MBPS) 361 mii->mii_media_active |= IFM_100_TX; 362 else if (bmsr & RL_GMEDIASTAT_10MBPS) 363 mii->mii_media_active |= IFM_10_T; 364 else 365 mii->mii_media_active |= IFM_NONE; 366 if (bmsr & RL_GMEDIASTAT_FDX) 367 mii->mii_media_active |= IFM_FDX; 368 369 return; 370 } 371 372 373 static int 374 rgephy_mii_phy_auto(struct mii_softc *mii) 375 { 376 rgephy_loop(mii); 377 rgephy_reset(mii); 378 379 PHY_WRITE(mii, RGEPHY_MII_ANAR, 380 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 381 DELAY(1000); 382 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 383 RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD); 384 DELAY(1000); 385 PHY_WRITE(mii, RGEPHY_MII_BMCR, 386 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 387 DELAY(100); 388 389 return (EJUSTRETURN); 390 } 391 392 static void 393 rgephy_loop(struct mii_softc *sc) 394 { 395 u_int32_t bmsr; 396 int i; 397 398 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 399 DELAY(1000); 400 401 for (i = 0; i < 15000; i++) { 402 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 403 if (!(bmsr & RGEPHY_BMSR_LINK)) { 404 #if 0 405 device_printf(sc->mii_dev, "looped %d\n", i); 406 #endif 407 break; 408 } 409 DELAY(10); 410 } 411 } 412 413 #define PHY_SETBIT(x, y, z) \ 414 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 415 #define PHY_CLRBIT(x, y, z) \ 416 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 417 418 /* 419 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 420 * existing revisions of the 8169S/8110S chips need to be tuned in 421 * order to reliably negotiate a 1000Mbps link. This is only needed 422 * for rev 0 and rev 1 of the PHY. Later versions work without 423 * any fixups. 424 */ 425 static void 426 rgephy_load_dspcode(struct mii_softc *sc) 427 { 428 int val; 429 uint16_t id2; 430 431 id2 = PHY_READ(sc, MII_PHYIDR2); 432 433 if (MII_REV(id2) > 1) 434 return; 435 436 PHY_WRITE(sc, 31, 0x0001); 437 PHY_WRITE(sc, 21, 0x1000); 438 PHY_WRITE(sc, 24, 0x65C7); 439 PHY_CLRBIT(sc, 4, 0x0800); 440 val = PHY_READ(sc, 4) & 0xFFF; 441 PHY_WRITE(sc, 4, val); 442 PHY_WRITE(sc, 3, 0x00A1); 443 PHY_WRITE(sc, 2, 0x0008); 444 PHY_WRITE(sc, 1, 0x1020); 445 PHY_WRITE(sc, 0, 0x1000); 446 PHY_SETBIT(sc, 4, 0x0800); 447 PHY_CLRBIT(sc, 4, 0x0800); 448 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 449 PHY_WRITE(sc, 4, val); 450 PHY_WRITE(sc, 3, 0xFF41); 451 PHY_WRITE(sc, 2, 0xDE60); 452 PHY_WRITE(sc, 1, 0x0140); 453 PHY_WRITE(sc, 0, 0x0077); 454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 455 PHY_WRITE(sc, 4, val); 456 PHY_WRITE(sc, 3, 0xDF01); 457 PHY_WRITE(sc, 2, 0xDF20); 458 PHY_WRITE(sc, 1, 0xFF95); 459 PHY_WRITE(sc, 0, 0xFA00); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xFF41); 463 PHY_WRITE(sc, 2, 0xDE20); 464 PHY_WRITE(sc, 1, 0x0140); 465 PHY_WRITE(sc, 0, 0x00BB); 466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 467 PHY_WRITE(sc, 4, val); 468 PHY_WRITE(sc, 3, 0xDF01); 469 PHY_WRITE(sc, 2, 0xDF20); 470 PHY_WRITE(sc, 1, 0xFF95); 471 PHY_WRITE(sc, 0, 0xBF00); 472 PHY_SETBIT(sc, 4, 0x0800); 473 PHY_CLRBIT(sc, 4, 0x0800); 474 PHY_WRITE(sc, 31, 0x0000); 475 476 DELAY(40); 477 } 478 479 static void 480 rgephy_reset(struct mii_softc *sc) 481 { 482 mii_phy_reset(sc); 483 DELAY(1000); 484 rgephy_load_dspcode(sc); 485 486 return; 487 } 488