1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <machine/clock.h> 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include "miibus_if.h" 60 61 #include <machine/bus.h> 62 #include <pci/if_rlreg.h> 63 64 static int rgephy_probe(device_t); 65 static int rgephy_attach(device_t); 66 67 static device_method_t rgephy_methods[] = { 68 /* device interface */ 69 DEVMETHOD(device_probe, rgephy_probe), 70 DEVMETHOD(device_attach, rgephy_attach), 71 DEVMETHOD(device_detach, mii_phy_detach), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 { 0, 0 } 74 }; 75 76 static devclass_t rgephy_devclass; 77 78 static driver_t rgephy_driver = { 79 "rgephy", 80 rgephy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 85 86 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 87 static void rgephy_status(struct mii_softc *); 88 static int rgephy_mii_phy_auto(struct mii_softc *); 89 static void rgephy_reset(struct mii_softc *); 90 static void rgephy_loop(struct mii_softc *); 91 static void rgephy_load_dspcode(struct mii_softc *); 92 static int rgephy_mii_model; 93 94 static int 95 rgephy_probe(device_t dev) 96 { 97 struct mii_attach_args *ma; 98 99 ma = device_get_ivars(dev); 100 101 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK && 102 MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) { 103 device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S); 104 return(0); 105 } 106 107 return(ENXIO); 108 } 109 110 static int 111 rgephy_attach(device_t dev) 112 { 113 struct mii_softc *sc; 114 struct mii_attach_args *ma; 115 struct mii_data *mii; 116 const char *sep = ""; 117 118 sc = device_get_softc(dev); 119 ma = device_get_ivars(dev); 120 sc->mii_dev = device_get_parent(dev); 121 mii = device_get_softc(sc->mii_dev); 122 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 123 124 sc->mii_inst = mii->mii_instance; 125 sc->mii_phy = ma->mii_phyno; 126 sc->mii_service = rgephy_service; 127 sc->mii_pdata = mii; 128 129 sc->mii_flags |= MIIF_NOISOLATE; 130 mii->mii_instance++; 131 132 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 133 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 134 135 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 136 BMCR_ISO); 137 #if 0 138 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 139 BMCR_LOOP|BMCR_S100); 140 #endif 141 142 rgephy_mii_model = MII_MODEL(ma->mii_id2); 143 rgephy_reset(sc); 144 145 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 146 sc->mii_capabilities &= ~BMSR_ANEG; 147 148 device_printf(dev, " "); 149 mii_add_media(sc); 150 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 151 RGEPHY_BMCR_FDX); 152 PRINT(", 1000baseTX"); 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 154 PRINT("1000baseTX-FDX"); 155 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 156 PRINT("auto"); 157 158 printf("\n"); 159 #undef ADD 160 #undef PRINT 161 162 MIIBUS_MEDIAINIT(sc->mii_dev); 163 return(0); 164 } 165 166 static int 167 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 168 { 169 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 170 int reg, speed, gig; 171 172 switch (cmd) { 173 case MII_POLLSTAT: 174 /* 175 * If we're not polling our PHY instance, just return. 176 */ 177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 178 return (0); 179 break; 180 181 case MII_MEDIACHG: 182 /* 183 * If the media indicates a different PHY instance, 184 * isolate ourselves. 185 */ 186 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 187 reg = PHY_READ(sc, MII_BMCR); 188 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 189 return (0); 190 } 191 192 /* 193 * If the interface is not up, don't do anything. 194 */ 195 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 196 break; 197 198 rgephy_reset(sc); /* XXX hardware bug work-around */ 199 200 switch (IFM_SUBTYPE(ife->ifm_media)) { 201 case IFM_AUTO: 202 #ifdef foo 203 /* 204 * If we're already in auto mode, just return. 205 */ 206 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 207 return (0); 208 #endif 209 (void) rgephy_mii_phy_auto(sc); 210 break; 211 case IFM_1000_T: 212 speed = RGEPHY_S1000; 213 goto setit; 214 case IFM_100_TX: 215 speed = RGEPHY_S100; 216 goto setit; 217 case IFM_10_T: 218 speed = RGEPHY_S10; 219 setit: 220 rgephy_loop(sc); 221 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 222 speed |= RGEPHY_BMCR_FDX; 223 gig = RGEPHY_1000CTL_AFD; 224 } else { 225 gig = RGEPHY_1000CTL_AHD; 226 } 227 228 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 229 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 230 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 231 232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 233 break; 234 235 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 236 PHY_WRITE(sc, RGEPHY_MII_BMCR, 237 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 238 239 /* 240 * When settning the link manually, one side must 241 * be the master and the other the slave. However 242 * ifmedia doesn't give us a good way to specify 243 * this, so we fake it by using one of the LINK 244 * flags. If LINK0 is set, we program the PHY to 245 * be a master, otherwise it's a slave. 246 */ 247 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 248 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 249 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 250 } else { 251 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 252 gig|RGEPHY_1000CTL_MSE); 253 } 254 break; 255 #ifdef foo 256 case IFM_NONE: 257 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 258 break; 259 #endif 260 case IFM_100_T4: 261 default: 262 return (EINVAL); 263 } 264 break; 265 266 case MII_TICK: 267 /* 268 * If we're not currently selected, just return. 269 */ 270 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 271 return (0); 272 273 /* 274 * Is the interface even up? 275 */ 276 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 277 return (0); 278 279 /* 280 * Only used for autonegotiation. 281 */ 282 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 283 break; 284 285 /* 286 * Check to see if we have link. If we do, we don't 287 * need to restart the autonegotiation process. Read 288 * the BMSR twice in case it's latched. 289 */ 290 reg = PHY_READ(sc, RL_GMEDIASTAT); 291 if (reg & RL_GMEDIASTAT_LINK) 292 break; 293 294 /* 295 * Only retry autonegotiation every 5 seconds. 296 */ 297 if (++sc->mii_ticks <= 5/*10*/) 298 break; 299 300 sc->mii_ticks = 0; 301 rgephy_mii_phy_auto(sc); 302 return (0); 303 } 304 305 /* Update the media status. */ 306 rgephy_status(sc); 307 308 /* 309 * Callback if something changed. Note that we need to poke 310 * the DSP on the RealTek PHYs if the media changes. 311 * 312 */ 313 if (sc->mii_media_active != mii->mii_media_active || 314 sc->mii_media_status != mii->mii_media_status || 315 cmd == MII_MEDIACHG) { 316 rgephy_load_dspcode(sc); 317 } 318 mii_phy_update(sc, cmd); 319 return (0); 320 } 321 322 static void 323 rgephy_status(struct mii_softc *sc) 324 { 325 struct mii_data *mii = sc->mii_pdata; 326 int bmsr, bmcr; 327 328 mii->mii_media_status = IFM_AVALID; 329 mii->mii_media_active = IFM_ETHER; 330 331 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 332 333 if (bmsr & RL_GMEDIASTAT_LINK) 334 mii->mii_media_status |= IFM_ACTIVE; 335 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 336 337 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 338 339 if (bmcr & RGEPHY_BMCR_LOOP) 340 mii->mii_media_active |= IFM_LOOP; 341 342 if (bmcr & RGEPHY_BMCR_AUTOEN) { 343 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 344 /* Erg, still trying, I guess... */ 345 mii->mii_media_active |= IFM_NONE; 346 return; 347 } 348 } 349 350 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 351 if (bmsr & RL_GMEDIASTAT_10MBPS) 352 mii->mii_media_active |= IFM_10_T; 353 if (bmsr & RL_GMEDIASTAT_100MBPS) 354 mii->mii_media_active |= IFM_100_TX; 355 if (bmsr & RL_GMEDIASTAT_1000MBPS) 356 mii->mii_media_active |= IFM_1000_T; 357 if (bmsr & RL_GMEDIASTAT_FDX) 358 mii->mii_media_active |= IFM_FDX; 359 360 return; 361 } 362 363 364 static int 365 rgephy_mii_phy_auto(struct mii_softc *mii) 366 { 367 rgephy_loop(mii); 368 rgephy_reset(mii); 369 370 PHY_WRITE(mii, RGEPHY_MII_ANAR, 371 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 372 DELAY(1000); 373 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 374 DELAY(1000); 375 PHY_WRITE(mii, RGEPHY_MII_BMCR, 376 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 377 DELAY(100); 378 379 return (EJUSTRETURN); 380 } 381 382 static void 383 rgephy_loop(struct mii_softc *sc) 384 { 385 u_int32_t bmsr; 386 int i; 387 388 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 389 DELAY(1000); 390 391 for (i = 0; i < 15000; i++) { 392 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 393 if (!(bmsr & RGEPHY_BMSR_LINK)) { 394 #if 0 395 device_printf(sc->mii_dev, "looped %d\n", i); 396 #endif 397 break; 398 } 399 DELAY(10); 400 } 401 } 402 403 #define PHY_SETBIT(x, y, z) \ 404 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 405 #define PHY_CLRBIT(x, y, z) \ 406 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 407 408 /* 409 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 410 * existing revisions of the 8169S/8110S chips need to be tuned in 411 * order to reliably negotiate a 1000Mbps link. Later revs of the 412 * chips may not require this software tuning. 413 */ 414 static void 415 rgephy_load_dspcode(struct mii_softc *sc) 416 { 417 int val; 418 419 PHY_WRITE(sc, 31, 0x0001); 420 PHY_WRITE(sc, 21, 0x1000); 421 PHY_WRITE(sc, 24, 0x65C7); 422 PHY_CLRBIT(sc, 4, 0x0800); 423 val = PHY_READ(sc, 4) & 0xFFF; 424 PHY_WRITE(sc, 4, val); 425 PHY_WRITE(sc, 3, 0x00A1); 426 PHY_WRITE(sc, 2, 0x0008); 427 PHY_WRITE(sc, 1, 0x1020); 428 PHY_WRITE(sc, 0, 0x1000); 429 PHY_SETBIT(sc, 4, 0x0800); 430 PHY_CLRBIT(sc, 4, 0x0800); 431 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 432 PHY_WRITE(sc, 4, val); 433 PHY_WRITE(sc, 3, 0xFF41); 434 PHY_WRITE(sc, 2, 0xDE60); 435 PHY_WRITE(sc, 1, 0x0140); 436 PHY_WRITE(sc, 0, 0x0077); 437 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 438 PHY_WRITE(sc, 4, val); 439 PHY_WRITE(sc, 3, 0xDF01); 440 PHY_WRITE(sc, 2, 0xDF20); 441 PHY_WRITE(sc, 1, 0xFF95); 442 PHY_WRITE(sc, 0, 0xFA00); 443 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 444 PHY_WRITE(sc, 4, val); 445 PHY_WRITE(sc, 3, 0xFF41); 446 PHY_WRITE(sc, 2, 0xDE20); 447 PHY_WRITE(sc, 1, 0x0140); 448 PHY_WRITE(sc, 0, 0x00BB); 449 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 450 PHY_WRITE(sc, 4, val); 451 PHY_WRITE(sc, 3, 0xDF01); 452 PHY_WRITE(sc, 2, 0xDF20); 453 PHY_WRITE(sc, 1, 0xFF95); 454 PHY_WRITE(sc, 0, 0xBF00); 455 PHY_SETBIT(sc, 4, 0x0800); 456 PHY_CLRBIT(sc, 4, 0x0800); 457 PHY_WRITE(sc, 31, 0x0000); 458 459 DELAY(40); 460 } 461 462 static void 463 rgephy_reset(struct mii_softc *sc) 464 { 465 mii_phy_reset(sc); 466 DELAY(1000); 467 rgephy_load_dspcode(sc); 468 469 return; 470 } 471