1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/if_arp.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include "miibus_if.h" 59 60 #include <machine/bus.h> 61 #include <pci/if_rlreg.h> 62 63 static int rgephy_probe(device_t); 64 static int rgephy_attach(device_t); 65 66 static device_method_t rgephy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, rgephy_probe), 69 DEVMETHOD(device_attach, rgephy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 DEVMETHOD_END 73 }; 74 75 static devclass_t rgephy_devclass; 76 77 static driver_t rgephy_driver = { 78 "rgephy", 79 rgephy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 84 85 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 86 static void rgephy_status(struct mii_softc *); 87 static int rgephy_mii_phy_auto(struct mii_softc *, int); 88 static void rgephy_reset(struct mii_softc *); 89 static void rgephy_loop(struct mii_softc *); 90 static void rgephy_load_dspcode(struct mii_softc *); 91 92 static const struct mii_phydesc rgephys[] = { 93 MII_PHY_DESC(REALTEK, RTL8169S), 94 MII_PHY_DESC(REALTEK, RTL8251), 95 MII_PHY_END 96 }; 97 98 static const struct mii_phy_funcs rgephy_funcs = { 99 rgephy_service, 100 rgephy_status, 101 rgephy_reset 102 }; 103 104 static int 105 rgephy_probe(device_t dev) 106 { 107 108 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 109 } 110 111 static int 112 rgephy_attach(device_t dev) 113 { 114 struct mii_softc *sc; 115 struct mii_attach_args *ma; 116 u_int flags; 117 118 sc = device_get_softc(dev); 119 ma = device_get_ivars(dev); 120 flags = 0; 121 if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0) 122 flags |= MIIF_PHYPRIV0; 123 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 124 125 /* RTL8169S do not report auto-sense; add manually. */ 126 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 127 sc->mii_capmask; 128 if (sc->mii_capabilities & BMSR_EXTSTAT) 129 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 130 device_printf(dev, " "); 131 mii_phy_add_media(sc); 132 printf("\n"); 133 /* 134 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 135 * manual configuration, which is used to work around issues with 136 * certain setups by default, should not be triggered as it may in 137 * turn cause harm in some edge cases. 138 */ 139 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 140 141 PHY_RESET(sc); 142 143 MIIBUS_MEDIAINIT(sc->mii_dev); 144 return (0); 145 } 146 147 static int 148 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 149 { 150 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 151 int reg, speed, gig, anar; 152 153 switch (cmd) { 154 case MII_POLLSTAT: 155 break; 156 157 case MII_MEDIACHG: 158 PHY_RESET(sc); /* XXX hardware bug work-around */ 159 160 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 161 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 162 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 163 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 164 165 switch (IFM_SUBTYPE(ife->ifm_media)) { 166 case IFM_AUTO: 167 #ifdef foo 168 /* 169 * If we're already in auto mode, just return. 170 */ 171 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 172 return (0); 173 #endif 174 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 175 break; 176 case IFM_1000_T: 177 speed = RGEPHY_S1000; 178 goto setit; 179 case IFM_100_TX: 180 speed = RGEPHY_S100; 181 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 182 goto setit; 183 case IFM_10_T: 184 speed = RGEPHY_S10; 185 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 186 setit: 187 if ((ife->ifm_media & IFM_FLOW) != 0 && 188 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 189 return (EINVAL); 190 191 if ((ife->ifm_media & IFM_FDX) != 0) { 192 speed |= RGEPHY_BMCR_FDX; 193 gig = RGEPHY_1000CTL_AFD; 194 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 195 if ((ife->ifm_media & IFM_FLOW) != 0 || 196 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 197 anar |= 198 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 199 } else { 200 gig = RGEPHY_1000CTL_AHD; 201 anar &= 202 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 203 } 204 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 205 gig |= RGEPHY_1000CTL_MSE; 206 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 207 gig |= RGEPHY_1000CTL_MSC; 208 } else { 209 gig = 0; 210 anar &= ~RGEPHY_ANAR_ASP; 211 } 212 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 213 speed |= 214 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 215 rgephy_loop(sc); 216 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 217 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 218 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 219 break; 220 case IFM_NONE: 221 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 222 break; 223 default: 224 return (EINVAL); 225 } 226 break; 227 228 case MII_TICK: 229 /* 230 * Only used for autonegotiation. 231 */ 232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 233 sc->mii_ticks = 0; 234 break; 235 } 236 237 /* 238 * Check to see if we have link. If we do, we don't 239 * need to restart the autonegotiation process. 240 */ 241 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 242 sc->mii_mpd_rev >= 2) { 243 /* RTL8211B(L) */ 244 reg = PHY_READ(sc, RGEPHY_MII_SSR); 245 if (reg & RGEPHY_SSR_LINK) { 246 sc->mii_ticks = 0; 247 break; 248 } 249 } else { 250 reg = PHY_READ(sc, RL_GMEDIASTAT); 251 if (reg & RL_GMEDIASTAT_LINK) { 252 sc->mii_ticks = 0; 253 break; 254 } 255 } 256 257 /* Announce link loss right after it happens. */ 258 if (sc->mii_ticks++ == 0) 259 break; 260 261 /* Only retry autonegotiation every mii_anegticks seconds. */ 262 if (sc->mii_ticks <= sc->mii_anegticks) 263 return (0); 264 265 sc->mii_ticks = 0; 266 rgephy_mii_phy_auto(sc, ife->ifm_media); 267 break; 268 } 269 270 /* Update the media status. */ 271 PHY_STATUS(sc); 272 273 /* 274 * Callback if something changed. Note that we need to poke 275 * the DSP on the RealTek PHYs if the media changes. 276 * 277 */ 278 if (sc->mii_media_active != mii->mii_media_active || 279 sc->mii_media_status != mii->mii_media_status || 280 cmd == MII_MEDIACHG) { 281 rgephy_load_dspcode(sc); 282 } 283 mii_phy_update(sc, cmd); 284 return (0); 285 } 286 287 static void 288 rgephy_status(struct mii_softc *sc) 289 { 290 struct mii_data *mii = sc->mii_pdata; 291 int bmsr, bmcr; 292 uint16_t ssr; 293 294 mii->mii_media_status = IFM_AVALID; 295 mii->mii_media_active = IFM_ETHER; 296 297 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 298 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 299 if (ssr & RGEPHY_SSR_LINK) 300 mii->mii_media_status |= IFM_ACTIVE; 301 } else { 302 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 303 if (bmsr & RL_GMEDIASTAT_LINK) 304 mii->mii_media_status |= IFM_ACTIVE; 305 } 306 307 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 308 309 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 310 if (bmcr & RGEPHY_BMCR_ISO) { 311 mii->mii_media_active |= IFM_NONE; 312 mii->mii_media_status = 0; 313 return; 314 } 315 316 if (bmcr & RGEPHY_BMCR_LOOP) 317 mii->mii_media_active |= IFM_LOOP; 318 319 if (bmcr & RGEPHY_BMCR_AUTOEN) { 320 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 321 /* Erg, still trying, I guess... */ 322 mii->mii_media_active |= IFM_NONE; 323 return; 324 } 325 } 326 327 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 328 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 329 switch (ssr & RGEPHY_SSR_SPD_MASK) { 330 case RGEPHY_SSR_S1000: 331 mii->mii_media_active |= IFM_1000_T; 332 break; 333 case RGEPHY_SSR_S100: 334 mii->mii_media_active |= IFM_100_TX; 335 break; 336 case RGEPHY_SSR_S10: 337 mii->mii_media_active |= IFM_10_T; 338 break; 339 default: 340 mii->mii_media_active |= IFM_NONE; 341 break; 342 } 343 if (ssr & RGEPHY_SSR_FDX) 344 mii->mii_media_active |= IFM_FDX; 345 else 346 mii->mii_media_active |= IFM_HDX; 347 } else { 348 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 349 if (bmsr & RL_GMEDIASTAT_1000MBPS) 350 mii->mii_media_active |= IFM_1000_T; 351 else if (bmsr & RL_GMEDIASTAT_100MBPS) 352 mii->mii_media_active |= IFM_100_TX; 353 else if (bmsr & RL_GMEDIASTAT_10MBPS) 354 mii->mii_media_active |= IFM_10_T; 355 else 356 mii->mii_media_active |= IFM_NONE; 357 if (bmsr & RL_GMEDIASTAT_FDX) 358 mii->mii_media_active |= IFM_FDX; 359 else 360 mii->mii_media_active |= IFM_HDX; 361 } 362 363 if ((mii->mii_media_active & IFM_FDX) != 0) 364 mii->mii_media_active |= mii_phy_flowstatus(sc); 365 366 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 367 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 368 mii->mii_media_active |= IFM_ETH_MASTER; 369 } 370 371 static int 372 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 373 { 374 int anar; 375 376 rgephy_loop(sc); 377 PHY_RESET(sc); 378 379 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 380 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 381 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 382 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 383 DELAY(1000); 384 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 385 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 386 DELAY(1000); 387 PHY_WRITE(sc, RGEPHY_MII_BMCR, 388 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 389 DELAY(100); 390 391 return (EJUSTRETURN); 392 } 393 394 static void 395 rgephy_loop(struct mii_softc *sc) 396 { 397 int i; 398 399 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 400 sc->mii_mpd_rev < 2) { 401 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 402 DELAY(1000); 403 } 404 405 for (i = 0; i < 15000; i++) { 406 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 407 #if 0 408 device_printf(sc->mii_dev, "looped %d\n", i); 409 #endif 410 break; 411 } 412 DELAY(10); 413 } 414 } 415 416 #define PHY_SETBIT(x, y, z) \ 417 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 418 #define PHY_CLRBIT(x, y, z) \ 419 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 420 421 /* 422 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 423 * existing revisions of the 8169S/8110S chips need to be tuned in 424 * order to reliably negotiate a 1000Mbps link. This is only needed 425 * for rev 0 and rev 1 of the PHY. Later versions work without 426 * any fixups. 427 */ 428 static void 429 rgephy_load_dspcode(struct mii_softc *sc) 430 { 431 int val; 432 433 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 434 sc->mii_mpd_rev >= 2) 435 return; 436 437 PHY_WRITE(sc, 31, 0x0001); 438 PHY_WRITE(sc, 21, 0x1000); 439 PHY_WRITE(sc, 24, 0x65C7); 440 PHY_CLRBIT(sc, 4, 0x0800); 441 val = PHY_READ(sc, 4) & 0xFFF; 442 PHY_WRITE(sc, 4, val); 443 PHY_WRITE(sc, 3, 0x00A1); 444 PHY_WRITE(sc, 2, 0x0008); 445 PHY_WRITE(sc, 1, 0x1020); 446 PHY_WRITE(sc, 0, 0x1000); 447 PHY_SETBIT(sc, 4, 0x0800); 448 PHY_CLRBIT(sc, 4, 0x0800); 449 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 450 PHY_WRITE(sc, 4, val); 451 PHY_WRITE(sc, 3, 0xFF41); 452 PHY_WRITE(sc, 2, 0xDE60); 453 PHY_WRITE(sc, 1, 0x0140); 454 PHY_WRITE(sc, 0, 0x0077); 455 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 456 PHY_WRITE(sc, 4, val); 457 PHY_WRITE(sc, 3, 0xDF01); 458 PHY_WRITE(sc, 2, 0xDF20); 459 PHY_WRITE(sc, 1, 0xFF95); 460 PHY_WRITE(sc, 0, 0xFA00); 461 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 462 PHY_WRITE(sc, 4, val); 463 PHY_WRITE(sc, 3, 0xFF41); 464 PHY_WRITE(sc, 2, 0xDE20); 465 PHY_WRITE(sc, 1, 0x0140); 466 PHY_WRITE(sc, 0, 0x00BB); 467 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 468 PHY_WRITE(sc, 4, val); 469 PHY_WRITE(sc, 3, 0xDF01); 470 PHY_WRITE(sc, 2, 0xDF20); 471 PHY_WRITE(sc, 1, 0xFF95); 472 PHY_WRITE(sc, 0, 0xBF00); 473 PHY_SETBIT(sc, 4, 0x0800); 474 PHY_CLRBIT(sc, 4, 0x0800); 475 PHY_WRITE(sc, 31, 0x0000); 476 477 DELAY(40); 478 } 479 480 static void 481 rgephy_reset(struct mii_softc *sc) 482 { 483 uint16_t pcr, ssr; 484 485 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { 486 /* RTL8211C(L) */ 487 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 488 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 489 ssr &= ~RGEPHY_SSR_ALDPS; 490 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 491 } 492 } 493 494 if (sc->mii_mpd_rev >= 2) { 495 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 496 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 497 pcr &= ~RGEPHY_PCR_MDI_MASK; 498 pcr |= RGEPHY_PCR_MDIX_AUTO; 499 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 500 } 501 } 502 503 mii_phy_reset(sc); 504 DELAY(1000); 505 rgephy_load_dspcode(sc); 506 } 507