1 /* 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/bus.h> 45 46 #include <machine/clock.h> 47 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include "miibus_if.h" 59 60 #include <machine/bus.h> 61 #include <pci/if_rlreg.h> 62 63 static int rgephy_probe(device_t); 64 static int rgephy_attach(device_t); 65 66 static device_method_t rgephy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, rgephy_probe), 69 DEVMETHOD(device_attach, rgephy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t rgephy_devclass; 76 77 static driver_t rgephy_driver = { 78 "rgephy", 79 rgephy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 84 85 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 86 static void rgephy_status(struct mii_softc *); 87 static int rgephy_mii_phy_auto(struct mii_softc *); 88 static void rgephy_reset(struct mii_softc *); 89 static void rgephy_loop(struct mii_softc *); 90 static void rgephy_load_dspcode(struct mii_softc *); 91 static int rgephy_mii_model; 92 93 static int 94 rgephy_probe(dev) 95 device_t dev; 96 { 97 struct mii_attach_args *ma; 98 99 ma = device_get_ivars(dev); 100 101 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK && 102 MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) { 103 device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S); 104 return(0); 105 } 106 107 return(ENXIO); 108 } 109 110 static int 111 rgephy_attach(dev) 112 device_t dev; 113 { 114 struct mii_softc *sc; 115 struct mii_attach_args *ma; 116 struct mii_data *mii; 117 const char *sep = ""; 118 119 sc = device_get_softc(dev); 120 ma = device_get_ivars(dev); 121 sc->mii_dev = device_get_parent(dev); 122 mii = device_get_softc(sc->mii_dev); 123 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 124 125 sc->mii_inst = mii->mii_instance; 126 sc->mii_phy = ma->mii_phyno; 127 sc->mii_service = rgephy_service; 128 sc->mii_pdata = mii; 129 130 sc->mii_flags |= MIIF_NOISOLATE; 131 mii->mii_instance++; 132 133 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 134 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 135 136 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 137 BMCR_ISO); 138 #if 0 139 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 140 BMCR_LOOP|BMCR_S100); 141 #endif 142 143 rgephy_mii_model = MII_MODEL(ma->mii_id2); 144 rgephy_reset(sc); 145 146 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 147 sc->mii_capabilities &= ~BMSR_ANEG; 148 149 device_printf(dev, " "); 150 mii_add_media(sc); 151 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 152 RGEPHY_BMCR_FDX); 153 PRINT(", 1000baseTX"); 154 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 155 PRINT("1000baseTX-FDX"); 156 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 157 PRINT("auto"); 158 159 printf("\n"); 160 #undef ADD 161 #undef PRINT 162 163 MIIBUS_MEDIAINIT(sc->mii_dev); 164 return(0); 165 } 166 167 static int 168 rgephy_service(sc, mii, cmd) 169 struct mii_softc *sc; 170 struct mii_data *mii; 171 int cmd; 172 { 173 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 174 int reg, speed, gig; 175 176 switch (cmd) { 177 case MII_POLLSTAT: 178 /* 179 * If we're not polling our PHY instance, just return. 180 */ 181 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 182 return (0); 183 break; 184 185 case MII_MEDIACHG: 186 /* 187 * If the media indicates a different PHY instance, 188 * isolate ourselves. 189 */ 190 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 191 reg = PHY_READ(sc, MII_BMCR); 192 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 193 return (0); 194 } 195 196 /* 197 * If the interface is not up, don't do anything. 198 */ 199 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 200 break; 201 202 rgephy_reset(sc); /* XXX hardware bug work-around */ 203 204 switch (IFM_SUBTYPE(ife->ifm_media)) { 205 case IFM_AUTO: 206 #ifdef foo 207 /* 208 * If we're already in auto mode, just return. 209 */ 210 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 211 return (0); 212 #endif 213 (void) rgephy_mii_phy_auto(sc); 214 break; 215 case IFM_1000_T: 216 speed = RGEPHY_S1000; 217 goto setit; 218 case IFM_100_TX: 219 speed = RGEPHY_S100; 220 goto setit; 221 case IFM_10_T: 222 speed = RGEPHY_S10; 223 setit: 224 rgephy_loop(sc); 225 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 226 speed |= RGEPHY_BMCR_FDX; 227 gig = RGEPHY_1000CTL_AFD; 228 } else { 229 gig = RGEPHY_1000CTL_AHD; 230 } 231 232 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 233 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 234 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 235 236 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 237 break; 238 239 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 240 PHY_WRITE(sc, RGEPHY_MII_BMCR, 241 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 242 243 /* 244 * When settning the link manually, one side must 245 * be the master and the other the slave. However 246 * ifmedia doesn't give us a good way to specify 247 * this, so we fake it by using one of the LINK 248 * flags. If LINK0 is set, we program the PHY to 249 * be a master, otherwise it's a slave. 250 */ 251 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 252 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 253 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 254 } else { 255 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 256 gig|RGEPHY_1000CTL_MSE); 257 } 258 break; 259 #ifdef foo 260 case IFM_NONE: 261 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 262 break; 263 #endif 264 case IFM_100_T4: 265 default: 266 return (EINVAL); 267 } 268 break; 269 270 case MII_TICK: 271 /* 272 * If we're not currently selected, just return. 273 */ 274 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 275 return (0); 276 277 /* 278 * Is the interface even up? 279 */ 280 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 281 return (0); 282 283 /* 284 * Only used for autonegotiation. 285 */ 286 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 287 break; 288 289 /* 290 * Check to see if we have link. If we do, we don't 291 * need to restart the autonegotiation process. Read 292 * the BMSR twice in case it's latched. 293 */ 294 reg = PHY_READ(sc, RL_GMEDIASTAT); 295 if (reg & RL_GMEDIASTAT_LINK) 296 break; 297 298 /* 299 * Only retry autonegotiation every 5 seconds. 300 */ 301 if (++sc->mii_ticks != 5/*10*/) 302 return (0); 303 304 sc->mii_ticks = 0; 305 rgephy_mii_phy_auto(sc); 306 return (0); 307 } 308 309 /* Update the media status. */ 310 rgephy_status(sc); 311 312 /* 313 * Callback if something changed. Note that we need to poke 314 * the DSP on the RealTek PHYs if the media changes. 315 * 316 */ 317 if (sc->mii_media_active != mii->mii_media_active || 318 sc->mii_media_status != mii->mii_media_status || 319 cmd == MII_MEDIACHG) { 320 mii_phy_update(sc, cmd); 321 rgephy_load_dspcode(sc); 322 } 323 return (0); 324 } 325 326 static void 327 rgephy_status(sc) 328 struct mii_softc *sc; 329 { 330 struct mii_data *mii = sc->mii_pdata; 331 int bmsr, bmcr; 332 333 mii->mii_media_status = IFM_AVALID; 334 mii->mii_media_active = IFM_ETHER; 335 336 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 337 338 if (bmsr & RL_GMEDIASTAT_LINK) 339 mii->mii_media_status |= IFM_ACTIVE; 340 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 341 342 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 343 344 if (bmcr & RGEPHY_BMCR_LOOP) 345 mii->mii_media_active |= IFM_LOOP; 346 347 if (bmcr & RGEPHY_BMCR_AUTOEN) { 348 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 349 /* Erg, still trying, I guess... */ 350 mii->mii_media_active |= IFM_NONE; 351 return; 352 } 353 } 354 355 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 356 if (bmsr & RL_GMEDIASTAT_10MBPS) 357 mii->mii_media_active |= IFM_10_T; 358 if (bmsr & RL_GMEDIASTAT_100MBPS) 359 mii->mii_media_active |= IFM_100_TX; 360 if (bmsr & RL_GMEDIASTAT_1000MBPS) 361 mii->mii_media_active |= IFM_1000_T; 362 if (bmsr & RL_GMEDIASTAT_FDX) 363 mii->mii_media_active |= IFM_FDX; 364 365 return; 366 } 367 368 369 static int 370 rgephy_mii_phy_auto(mii) 371 struct mii_softc *mii; 372 { 373 rgephy_loop(mii); 374 rgephy_reset(mii); 375 376 PHY_WRITE(mii, RGEPHY_MII_ANAR, 377 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 378 DELAY(1000); 379 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 380 DELAY(1000); 381 PHY_WRITE(mii, RGEPHY_MII_BMCR, 382 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 383 DELAY(100); 384 385 return (EJUSTRETURN); 386 } 387 388 static void 389 rgephy_loop(struct mii_softc *sc) 390 { 391 u_int32_t bmsr; 392 int i; 393 394 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 395 DELAY(1000); 396 397 for (i = 0; i < 15000; i++) { 398 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 399 if (!(bmsr & RGEPHY_BMSR_LINK)) { 400 #if 0 401 device_printf(sc->mii_dev, "looped %d\n", i); 402 #endif 403 break; 404 } 405 DELAY(10); 406 } 407 } 408 409 #define PHY_SETBIT(x, y, z) \ 410 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 411 #define PHY_CLRBIT(x, y, z) \ 412 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 413 414 /* 415 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 416 * existing revisions of the 8169S/8110S chips need to be tuned in 417 * order to reliably negotiate a 1000Mbps link. Later revs of the 418 * chips may not require this software tuning. 419 */ 420 static void 421 rgephy_load_dspcode(struct mii_softc *sc) 422 { 423 int val; 424 425 PHY_WRITE(sc, 31, 0x0001); 426 PHY_WRITE(sc, 21, 0x1000); 427 PHY_WRITE(sc, 24, 0x65C7); 428 PHY_CLRBIT(sc, 4, 0x0800); 429 val = PHY_READ(sc, 4) & 0xFFF; 430 PHY_WRITE(sc, 4, val); 431 PHY_WRITE(sc, 3, 0x00A1); 432 PHY_WRITE(sc, 2, 0x0008); 433 PHY_WRITE(sc, 1, 0x1020); 434 PHY_WRITE(sc, 0, 0x1000); 435 PHY_SETBIT(sc, 4, 0x0800); 436 PHY_CLRBIT(sc, 4, 0x0800); 437 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 438 PHY_WRITE(sc, 4, val); 439 PHY_WRITE(sc, 3, 0xFF41); 440 PHY_WRITE(sc, 2, 0xDE60); 441 PHY_WRITE(sc, 1, 0x0140); 442 PHY_WRITE(sc, 0, 0x0077); 443 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 444 PHY_WRITE(sc, 4, val); 445 PHY_WRITE(sc, 3, 0xDF01); 446 PHY_WRITE(sc, 2, 0xDF20); 447 PHY_WRITE(sc, 1, 0xFF95); 448 PHY_WRITE(sc, 0, 0xFA00); 449 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 450 PHY_WRITE(sc, 4, val); 451 PHY_WRITE(sc, 3, 0xFF41); 452 PHY_WRITE(sc, 2, 0xDE20); 453 PHY_WRITE(sc, 1, 0x0140); 454 PHY_WRITE(sc, 0, 0x00BB); 455 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 456 PHY_WRITE(sc, 4, val); 457 PHY_WRITE(sc, 3, 0xDF01); 458 PHY_WRITE(sc, 2, 0xDF20); 459 PHY_WRITE(sc, 1, 0xFF95); 460 PHY_WRITE(sc, 0, 0xBF00); 461 PHY_SETBIT(sc, 4, 0x0800); 462 PHY_CLRBIT(sc, 4, 0x0800); 463 PHY_WRITE(sc, 31, 0x0000); 464 465 DELAY(40); 466 } 467 468 static void 469 rgephy_reset(struct mii_softc *sc) 470 { 471 mii_phy_reset(sc); 472 DELAY(1000); 473 rgephy_load_dspcode(sc); 474 475 return; 476 } 477