xref: /freebsd/sys/dev/mii/rgephy.c (revision 74bf4e164ba5851606a27d4feff27717452583e5)
1 /*
2  * Copyright (c) 2003
3  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /*
37  * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
38  */
39 
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46 
47 #include <machine/clock.h>
48 
49 #include <net/if.h>
50 #include <net/if_arp.h>
51 #include <net/if_media.h>
52 
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55 #include "miidevs.h"
56 
57 #include <dev/mii/rgephyreg.h>
58 
59 #include "miibus_if.h"
60 
61 #include <machine/bus.h>
62 #include <pci/if_rlreg.h>
63 
64 static int rgephy_probe(device_t);
65 static int rgephy_attach(device_t);
66 
67 static device_method_t rgephy_methods[] = {
68 	/* device interface */
69 	DEVMETHOD(device_probe,		rgephy_probe),
70 	DEVMETHOD(device_attach,	rgephy_attach),
71 	DEVMETHOD(device_detach,	mii_phy_detach),
72 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
73 	{ 0, 0 }
74 };
75 
76 static devclass_t rgephy_devclass;
77 
78 static driver_t rgephy_driver = {
79 	"rgephy",
80 	rgephy_methods,
81 	sizeof(struct mii_softc)
82 };
83 
84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
85 
86 static int	rgephy_service(struct mii_softc *, struct mii_data *, int);
87 static void	rgephy_status(struct mii_softc *);
88 static int	rgephy_mii_phy_auto(struct mii_softc *);
89 static void	rgephy_reset(struct mii_softc *);
90 static void	rgephy_loop(struct mii_softc *);
91 static void	rgephy_load_dspcode(struct mii_softc *);
92 static int	rgephy_mii_model;
93 
94 static int
95 rgephy_probe(dev)
96 	device_t		dev;
97 {
98 	struct mii_attach_args *ma;
99 
100 	ma = device_get_ivars(dev);
101 
102 	if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK &&
103 	    MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) {
104 		device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S);
105 		return(0);
106 	}
107 
108 	return(ENXIO);
109 }
110 
111 static int
112 rgephy_attach(dev)
113 	device_t		dev;
114 {
115 	struct mii_softc *sc;
116 	struct mii_attach_args *ma;
117 	struct mii_data *mii;
118 	const char *sep = "";
119 
120 	sc = device_get_softc(dev);
121 	ma = device_get_ivars(dev);
122 	sc->mii_dev = device_get_parent(dev);
123 	mii = device_get_softc(sc->mii_dev);
124 	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
125 
126 	sc->mii_inst = mii->mii_instance;
127 	sc->mii_phy = ma->mii_phyno;
128 	sc->mii_service = rgephy_service;
129 	sc->mii_pdata = mii;
130 
131 	sc->mii_flags |= MIIF_NOISOLATE;
132 	mii->mii_instance++;
133 
134 #define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
135 #define PRINT(s)	printf("%s%s", sep, s); sep = ", "
136 
137 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
138 	    BMCR_ISO);
139 #if 0
140 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
141 	    BMCR_LOOP|BMCR_S100);
142 #endif
143 
144 	rgephy_mii_model = MII_MODEL(ma->mii_id2);
145 	rgephy_reset(sc);
146 
147 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
148 	sc->mii_capabilities &= ~BMSR_ANEG;
149 
150 	device_printf(dev, " ");
151 	mii_add_media(sc);
152 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
153 	    RGEPHY_BMCR_FDX);
154 	PRINT(", 1000baseTX");
155 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
156 	PRINT("1000baseTX-FDX");
157 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
158 	PRINT("auto");
159 
160 	printf("\n");
161 #undef ADD
162 #undef PRINT
163 
164 	MIIBUS_MEDIAINIT(sc->mii_dev);
165 	return(0);
166 }
167 
168 static int
169 rgephy_service(sc, mii, cmd)
170 	struct mii_softc *sc;
171 	struct mii_data *mii;
172 	int cmd;
173 {
174 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
175 	int reg, speed, gig;
176 
177 	switch (cmd) {
178 	case MII_POLLSTAT:
179 		/*
180 		 * If we're not polling our PHY instance, just return.
181 		 */
182 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
183 			return (0);
184 		break;
185 
186 	case MII_MEDIACHG:
187 		/*
188 		 * If the media indicates a different PHY instance,
189 		 * isolate ourselves.
190 		 */
191 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
192 			reg = PHY_READ(sc, MII_BMCR);
193 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
194 			return (0);
195 		}
196 
197 		/*
198 		 * If the interface is not up, don't do anything.
199 		 */
200 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
201 			break;
202 
203 		rgephy_reset(sc);	/* XXX hardware bug work-around */
204 
205 		switch (IFM_SUBTYPE(ife->ifm_media)) {
206 		case IFM_AUTO:
207 #ifdef foo
208 			/*
209 			 * If we're already in auto mode, just return.
210 			 */
211 			if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
212 				return (0);
213 #endif
214 			(void) rgephy_mii_phy_auto(sc);
215 			break;
216 		case IFM_1000_T:
217 			speed = RGEPHY_S1000;
218 			goto setit;
219 		case IFM_100_TX:
220 			speed = RGEPHY_S100;
221 			goto setit;
222 		case IFM_10_T:
223 			speed = RGEPHY_S10;
224 setit:
225 			rgephy_loop(sc);
226 			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
227 				speed |= RGEPHY_BMCR_FDX;
228 				gig = RGEPHY_1000CTL_AFD;
229 			} else {
230 				gig = RGEPHY_1000CTL_AHD;
231 			}
232 
233 			PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
234 			PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
235 			PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
236 
237 			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
238 				break;
239 
240 			PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
241 			PHY_WRITE(sc, RGEPHY_MII_BMCR,
242 			    speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
243 
244 			/*
245 			 * When settning the link manually, one side must
246 			 * be the master and the other the slave. However
247 			 * ifmedia doesn't give us a good way to specify
248 			 * this, so we fake it by using one of the LINK
249 			 * flags. If LINK0 is set, we program the PHY to
250 			 * be a master, otherwise it's a slave.
251 			 */
252 			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
253 				PHY_WRITE(sc, RGEPHY_MII_1000CTL,
254 				    gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
255 			} else {
256 				PHY_WRITE(sc, RGEPHY_MII_1000CTL,
257 				    gig|RGEPHY_1000CTL_MSE);
258 			}
259 			break;
260 #ifdef foo
261 		case IFM_NONE:
262 			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
263 			break;
264 #endif
265 		case IFM_100_T4:
266 		default:
267 			return (EINVAL);
268 		}
269 		break;
270 
271 	case MII_TICK:
272 		/*
273 		 * If we're not currently selected, just return.
274 		 */
275 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
276 			return (0);
277 
278 		/*
279 		 * Is the interface even up?
280 		 */
281 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
282 			return (0);
283 
284 		/*
285 		 * Only used for autonegotiation.
286 		 */
287 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
288 			break;
289 
290 		/*
291 		 * Check to see if we have link.  If we do, we don't
292 		 * need to restart the autonegotiation process.  Read
293 		 * the BMSR twice in case it's latched.
294 		 */
295 		reg = PHY_READ(sc, RL_GMEDIASTAT);
296 		if (reg & RL_GMEDIASTAT_LINK)
297 			break;
298 
299 		/*
300 		 * Only retry autonegotiation every 5 seconds.
301 		 */
302 		if (++sc->mii_ticks <= 5/*10*/)
303 			break;
304 
305 		sc->mii_ticks = 0;
306 		rgephy_mii_phy_auto(sc);
307 		return (0);
308 	}
309 
310 	/* Update the media status. */
311 	rgephy_status(sc);
312 
313 	/*
314 	 * Callback if something changed. Note that we need to poke
315 	 * the DSP on the RealTek PHYs if the media changes.
316 	 *
317 	 */
318 	if (sc->mii_media_active != mii->mii_media_active ||
319 	    sc->mii_media_status != mii->mii_media_status ||
320 	    cmd == MII_MEDIACHG) {
321 		rgephy_load_dspcode(sc);
322 	}
323 	mii_phy_update(sc, cmd);
324 	return (0);
325 }
326 
327 static void
328 rgephy_status(sc)
329 	struct mii_softc *sc;
330 {
331 	struct mii_data *mii = sc->mii_pdata;
332 	int bmsr, bmcr;
333 
334 	mii->mii_media_status = IFM_AVALID;
335 	mii->mii_media_active = IFM_ETHER;
336 
337 	bmsr = PHY_READ(sc, RL_GMEDIASTAT);
338 
339 	if (bmsr & RL_GMEDIASTAT_LINK)
340 		mii->mii_media_status |= IFM_ACTIVE;
341 	bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
342 
343 	bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
344 
345 	if (bmcr & RGEPHY_BMCR_LOOP)
346 		mii->mii_media_active |= IFM_LOOP;
347 
348 	if (bmcr & RGEPHY_BMCR_AUTOEN) {
349 		if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
350 			/* Erg, still trying, I guess... */
351 			mii->mii_media_active |= IFM_NONE;
352 			return;
353 		}
354 	}
355 
356 	bmsr = PHY_READ(sc, RL_GMEDIASTAT);
357 	if (bmsr & RL_GMEDIASTAT_10MBPS)
358 		mii->mii_media_active |= IFM_10_T;
359 	if (bmsr & RL_GMEDIASTAT_100MBPS)
360 		mii->mii_media_active |= IFM_100_TX;
361 	if (bmsr & RL_GMEDIASTAT_1000MBPS)
362 		mii->mii_media_active |= IFM_1000_T;
363 	if (bmsr & RL_GMEDIASTAT_FDX)
364 		mii->mii_media_active |= IFM_FDX;
365 
366 	return;
367 }
368 
369 
370 static int
371 rgephy_mii_phy_auto(mii)
372 	struct mii_softc *mii;
373 {
374 	rgephy_loop(mii);
375 	rgephy_reset(mii);
376 
377 	PHY_WRITE(mii, RGEPHY_MII_ANAR,
378 	    BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
379 	DELAY(1000);
380 	PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
381 	DELAY(1000);
382 	PHY_WRITE(mii, RGEPHY_MII_BMCR,
383 	    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
384 	DELAY(100);
385 
386 	return (EJUSTRETURN);
387 }
388 
389 static void
390 rgephy_loop(struct mii_softc *sc)
391 {
392 	u_int32_t bmsr;
393 	int i;
394 
395 	PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
396 	DELAY(1000);
397 
398 	for (i = 0; i < 15000; i++) {
399 		bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
400 		if (!(bmsr & RGEPHY_BMSR_LINK)) {
401 #if 0
402 			device_printf(sc->mii_dev, "looped %d\n", i);
403 #endif
404 			break;
405 		}
406 		DELAY(10);
407 	}
408 }
409 
410 #define PHY_SETBIT(x, y, z) \
411 	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
412 #define PHY_CLRBIT(x, y, z) \
413 	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
414 
415 /*
416  * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
417  * existing revisions of the 8169S/8110S chips need to be tuned in
418  * order to reliably negotiate a 1000Mbps link. Later revs of the
419  * chips may not require this software tuning.
420  */
421 static void
422 rgephy_load_dspcode(struct mii_softc *sc)
423 {
424 	int val;
425 
426 	PHY_WRITE(sc, 31, 0x0001);
427 	PHY_WRITE(sc, 21, 0x1000);
428 	PHY_WRITE(sc, 24, 0x65C7);
429 	PHY_CLRBIT(sc, 4, 0x0800);
430 	val = PHY_READ(sc, 4) & 0xFFF;
431 	PHY_WRITE(sc, 4, val);
432 	PHY_WRITE(sc, 3, 0x00A1);
433 	PHY_WRITE(sc, 2, 0x0008);
434 	PHY_WRITE(sc, 1, 0x1020);
435 	PHY_WRITE(sc, 0, 0x1000);
436 	PHY_SETBIT(sc, 4, 0x0800);
437 	PHY_CLRBIT(sc, 4, 0x0800);
438 	val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
439 	PHY_WRITE(sc, 4, val);
440 	PHY_WRITE(sc, 3, 0xFF41);
441 	PHY_WRITE(sc, 2, 0xDE60);
442 	PHY_WRITE(sc, 1, 0x0140);
443 	PHY_WRITE(sc, 0, 0x0077);
444 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
445 	PHY_WRITE(sc, 4, val);
446 	PHY_WRITE(sc, 3, 0xDF01);
447 	PHY_WRITE(sc, 2, 0xDF20);
448 	PHY_WRITE(sc, 1, 0xFF95);
449 	PHY_WRITE(sc, 0, 0xFA00);
450 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
451 	PHY_WRITE(sc, 4, val);
452 	PHY_WRITE(sc, 3, 0xFF41);
453 	PHY_WRITE(sc, 2, 0xDE20);
454 	PHY_WRITE(sc, 1, 0x0140);
455 	PHY_WRITE(sc, 0, 0x00BB);
456 	val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
457 	PHY_WRITE(sc, 4, val);
458 	PHY_WRITE(sc, 3, 0xDF01);
459 	PHY_WRITE(sc, 2, 0xDF20);
460 	PHY_WRITE(sc, 1, 0xFF95);
461 	PHY_WRITE(sc, 0, 0xBF00);
462 	PHY_SETBIT(sc, 4, 0x0800);
463 	PHY_CLRBIT(sc, 4, 0x0800);
464 	PHY_WRITE(sc, 31, 0x0000);
465 
466 	DELAY(40);
467 }
468 
469 static void
470 rgephy_reset(struct mii_softc *sc)
471 {
472 	mii_phy_reset(sc);
473 	DELAY(1000);
474 	rgephy_load_dspcode(sc);
475 
476 	return;
477 }
478